Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: xilinx - Add gcm(aes) support for AMD/Xilinx Versal device
Add gcm(aes) algorithm support for AMD/Xilinx Versal devices.
Signed-off-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Harsh Jain
and committed by
Herbert Xu
280bfc3e
856f0619
+421
-9
+421
-9
drivers/crypto/xilinx/zynqmp-aes-gcm.c
+421
-9
drivers/crypto/xilinx/zynqmp-aes-gcm.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
/*
3
3
* Xilinx ZynqMP AES Driver.
4
-
* Copyright (c) 2020 Xilinx Inc.
4
+
* Copyright (C) 2020-2022 Xilinx Inc.
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* Copyright (C) 2022-2025 Advanced Micro Devices, Inc.
5
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*/
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#include <crypto/aes.h>
···
20
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#include <linux/string.h>
21
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#define ZYNQMP_DMA_BIT_MASK 32U
22
+
#define VERSAL_DMA_BIT_MASK 64U
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#define XILINX_AES_AUTH_SIZE 16U
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#define XILINX_AES_BLK_SIZE 1U
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#define ZYNQMP_AES_MIN_INPUT_BLK_SIZE 4U
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#define ZYNQMP_AES_WORD_LEN 4U
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28
+
#define VERSAL_AES_QWORD_LEN 16U
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#define ZYNQMP_AES_GCM_TAG_MISMATCH_ERR 0x01
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#define ZYNQMP_AES_WRONG_KEY_SRC_ERR 0x13
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#define ZYNQMP_AES_PUF_NOT_PROGRAMMED 0xE300
···
52
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struct xilinx_aead_alg {
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struct xilinx_aead_dev *aead_dev;
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struct aead_engine_alg aead;
52
+
int (*aes_aead_cipher)(struct aead_request *areq);
55
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u8 dma_bit_mask;
56
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};
57
55
···
86
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};
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static struct xilinx_aead_dev *aead_dev;
85
+
86
+
enum versal_aead_keysrc {
87
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VERSAL_AES_BBRAM_KEY = 0,
88
+
VERSAL_AES_BBRAM_RED_KEY,
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+
VERSAL_AES_BH_KEY,
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VERSAL_AES_BH_RED_KEY,
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VERSAL_AES_EFUSE_KEY,
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VERSAL_AES_EFUSE_RED_KEY,
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VERSAL_AES_EFUSE_USER_KEY_0,
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VERSAL_AES_EFUSE_USER_KEY_1,
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VERSAL_AES_EFUSE_USER_RED_KEY_0,
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VERSAL_AES_EFUSE_USER_RED_KEY_1,
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VERSAL_AES_KUP_KEY,
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VERSAL_AES_PUF_KEY,
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VERSAL_AES_USER_KEY_0,
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VERSAL_AES_USER_KEY_1,
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VERSAL_AES_USER_KEY_2,
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VERSAL_AES_USER_KEY_3,
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VERSAL_AES_USER_KEY_4,
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VERSAL_AES_USER_KEY_5,
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VERSAL_AES_USER_KEY_6,
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VERSAL_AES_USER_KEY_7,
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VERSAL_AES_EXPANDED_KEYS,
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VERSAL_AES_ALL_KEYS,
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+
};
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+
111
+
enum versal_aead_op {
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VERSAL_AES_ENCRYPT = 0,
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VERSAL_AES_DECRYPT
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+
};
115
+
116
+
enum versal_aes_keysize {
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HW_AES_KEY_SIZE_128 = 0,
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HW_AES_KEY_SIZE_256 = 2,
119
+
};
120
+
121
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struct versal_init_ops {
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u64 iv;
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u32 op;
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+
u32 keysrc;
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u32 size;
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+
};
127
+
128
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struct versal_in_params {
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+
u64 in_data_addr;
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u32 size;
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u32 is_last;
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};
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static int zynqmp_aes_aead_cipher(struct aead_request *req)
91
135
{
···
239
187
return ret;
240
188
}
241
189
190
+
static int versal_aes_aead_cipher(struct aead_request *req)
191
+
{
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struct crypto_aead *aead = crypto_aead_reqtfm(req);
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+
struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
194
+
struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
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dma_addr_t dma_addr_data, dma_addr_hw_req, dma_addr_in;
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u32 total_len = req->assoclen + req->cryptlen;
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struct device *dev = tfm_ctx->dev;
198
+
struct versal_init_ops *hwreq;
199
+
struct versal_in_params *in;
200
+
u32 gcm_offset, out_len;
201
+
size_t dmabuf_size;
202
+
size_t kbuf_size;
203
+
void *dmabuf;
204
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char *kbuf;
205
+
int ret;
206
+
207
+
kbuf_size = total_len + XILINX_AES_AUTH_SIZE;
208
+
kbuf = kmalloc(kbuf_size, GFP_KERNEL);
209
+
if (unlikely(!kbuf)) {
210
+
ret = -ENOMEM;
211
+
goto err;
212
+
}
213
+
dmabuf_size = sizeof(struct versal_init_ops) +
214
+
sizeof(struct versal_in_params) +
215
+
GCM_AES_IV_SIZE;
216
+
dmabuf = kmalloc(dmabuf_size, GFP_KERNEL);
217
+
if (unlikely(!dmabuf)) {
218
+
ret = -ENOMEM;
219
+
goto buf1_free;
220
+
}
221
+
222
+
dma_addr_hw_req = dma_map_single(dev, dmabuf, dmabuf_size, DMA_BIDIRECTIONAL);
223
+
if (unlikely(dma_mapping_error(dev, dma_addr_hw_req))) {
224
+
ret = -ENOMEM;
225
+
goto buf2_free;
226
+
}
227
+
scatterwalk_map_and_copy(kbuf, req->src, 0, total_len, 0);
228
+
dma_addr_data = dma_map_single(dev, kbuf, kbuf_size, DMA_BIDIRECTIONAL);
229
+
if (unlikely(dma_mapping_error(dev, dma_addr_data))) {
230
+
dma_unmap_single(dev, dma_addr_hw_req, dmabuf_size, DMA_BIDIRECTIONAL);
231
+
ret = -ENOMEM;
232
+
goto buf2_free;
233
+
}
234
+
hwreq = dmabuf;
235
+
in = dmabuf + sizeof(struct versal_init_ops);
236
+
memcpy(dmabuf + sizeof(struct versal_init_ops) +
237
+
sizeof(struct versal_in_params), req->iv, GCM_AES_IV_SIZE);
238
+
hwreq->iv = dma_addr_hw_req + sizeof(struct versal_init_ops) +
239
+
sizeof(struct versal_in_params);
240
+
hwreq->keysrc = tfm_ctx->keysrc;
241
+
dma_addr_in = dma_addr_hw_req + sizeof(struct versal_init_ops);
242
+
if (rq_ctx->op == XILINX_AES_ENCRYPT) {
243
+
hwreq->op = VERSAL_AES_ENCRYPT;
244
+
out_len = total_len + crypto_aead_authsize(aead);
245
+
in->size = req->cryptlen;
246
+
} else {
247
+
hwreq->op = VERSAL_AES_DECRYPT;
248
+
out_len = total_len - XILINX_AES_AUTH_SIZE;
249
+
in->size = req->cryptlen - XILINX_AES_AUTH_SIZE;
250
+
}
251
+
252
+
if (tfm_ctx->keylen == AES_KEYSIZE_128)
253
+
hwreq->size = HW_AES_KEY_SIZE_128;
254
+
else
255
+
hwreq->size = HW_AES_KEY_SIZE_256;
256
+
257
+
/* Request aes key write for volatile user keys */
258
+
if (hwreq->keysrc >= VERSAL_AES_USER_KEY_0 && hwreq->keysrc <= VERSAL_AES_USER_KEY_7) {
259
+
ret = versal_pm_aes_key_write(hwreq->size, hwreq->keysrc,
260
+
tfm_ctx->key_dma_addr);
261
+
if (ret)
262
+
goto unmap;
263
+
}
264
+
265
+
in->in_data_addr = dma_addr_data + req->assoclen;
266
+
in->is_last = 1;
267
+
gcm_offset = req->assoclen + in->size;
268
+
dma_sync_single_for_device(dev, dma_addr_hw_req, dmabuf_size, DMA_BIDIRECTIONAL);
269
+
ret = versal_pm_aes_op_init(dma_addr_hw_req);
270
+
if (ret)
271
+
goto clearkey;
272
+
273
+
if (req->assoclen > 0) {
274
+
/* Currently GMAC is OFF by default */
275
+
ret = versal_pm_aes_update_aad(dma_addr_data, req->assoclen);
276
+
if (ret)
277
+
goto clearkey;
278
+
}
279
+
if (rq_ctx->op == XILINX_AES_ENCRYPT) {
280
+
ret = versal_pm_aes_enc_update(dma_addr_in,
281
+
dma_addr_data + req->assoclen);
282
+
if (ret)
283
+
goto clearkey;
284
+
285
+
ret = versal_pm_aes_enc_final(dma_addr_data + gcm_offset);
286
+
if (ret)
287
+
goto clearkey;
288
+
} else {
289
+
ret = versal_pm_aes_dec_update(dma_addr_in,
290
+
dma_addr_data + req->assoclen);
291
+
if (ret)
292
+
goto clearkey;
293
+
294
+
ret = versal_pm_aes_dec_final(dma_addr_data + gcm_offset);
295
+
if (ret) {
296
+
ret = -EBADMSG;
297
+
goto clearkey;
298
+
}
299
+
}
300
+
dma_unmap_single(dev, dma_addr_data, kbuf_size, DMA_BIDIRECTIONAL);
301
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dma_unmap_single(dev, dma_addr_hw_req, dmabuf_size, DMA_BIDIRECTIONAL);
302
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sg_copy_from_buffer(req->dst, sg_nents(req->dst),
303
+
kbuf, out_len);
304
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dma_addr_data = 0;
305
+
dma_addr_hw_req = 0;
306
+
307
+
clearkey:
308
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if (hwreq->keysrc >= VERSAL_AES_USER_KEY_0 && hwreq->keysrc <= VERSAL_AES_USER_KEY_7)
309
+
versal_pm_aes_key_zero(hwreq->keysrc);
310
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unmap:
311
+
if (unlikely(dma_addr_data))
312
+
dma_unmap_single(dev, dma_addr_data, kbuf_size, DMA_BIDIRECTIONAL);
313
+
if (unlikely(dma_addr_hw_req))
314
+
dma_unmap_single(dev, dma_addr_hw_req, dmabuf_size, DMA_BIDIRECTIONAL);
315
+
buf2_free:
316
+
memzero_explicit(dmabuf, dmabuf_size);
317
+
kfree(dmabuf);
318
+
buf1_free:
319
+
memzero_explicit(kbuf, kbuf_size);
320
+
kfree(kbuf);
321
+
err:
322
+
return ret;
323
+
}
324
+
242
325
static int zynqmp_fallback_check(struct xilinx_aead_tfm_ctx *tfm_ctx,
243
326
struct aead_request *req)
244
327
{
···
399
212
return 0;
400
213
}
401
214
215
+
static int versal_fallback_check(struct xilinx_aead_tfm_ctx *tfm_ctx,
216
+
struct aead_request *req)
217
+
{
218
+
struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
219
+
220
+
if (tfm_ctx->authsize != XILINX_AES_AUTH_SIZE && rq_ctx->op == XILINX_AES_DECRYPT)
221
+
return 1;
222
+
223
+
if (tfm_ctx->keylen == AES_KEYSIZE_192)
224
+
return 1;
225
+
226
+
if (req->cryptlen < ZYNQMP_AES_MIN_INPUT_BLK_SIZE ||
227
+
req->cryptlen % ZYNQMP_AES_WORD_LEN ||
228
+
req->assoclen % VERSAL_AES_QWORD_LEN)
229
+
return 1;
230
+
231
+
if (rq_ctx->op == XILINX_AES_DECRYPT &&
232
+
req->cryptlen <= XILINX_AES_AUTH_SIZE)
233
+
return 1;
234
+
235
+
return 0;
236
+
}
237
+
402
238
static int xilinx_handle_aes_req(struct crypto_engine *engine, void *req)
403
239
{
404
240
struct aead_request *areq =
405
241
container_of(req, struct aead_request, base);
242
+
struct crypto_aead *aead = crypto_aead_reqtfm(req);
243
+
struct aead_alg *alg = crypto_aead_alg(aead);
244
+
struct xilinx_aead_alg *drv_ctx;
406
245
int err;
407
246
408
-
err = zynqmp_aes_aead_cipher(areq);
247
+
drv_ctx = container_of(alg, struct xilinx_aead_alg, aead.base);
248
+
err = drv_ctx->aes_aead_cipher(areq);
409
249
local_bh_disable();
410
250
crypto_finalize_aead_request(engine, areq, err);
411
251
local_bh_enable();
···
492
278
return err;
493
279
}
494
280
281
+
static int versal_aes_aead_setkey(struct crypto_aead *aead, const u8 *key,
282
+
unsigned int keylen)
283
+
{
284
+
struct crypto_tfm *tfm = crypto_aead_tfm(aead);
285
+
struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_tfm_ctx(tfm);
286
+
struct xilinx_hwkey_info hwkey;
287
+
unsigned char keysrc;
288
+
int err;
289
+
290
+
tfm_ctx->keysrc = VERSAL_AES_USER_KEY_0;
291
+
if (keylen == sizeof(struct xilinx_hwkey_info)) {
292
+
memcpy(&hwkey, key, sizeof(struct xilinx_hwkey_info));
293
+
if (hwkey.magic != XILINX_KEY_MAGIC)
294
+
return -EINVAL;
295
+
296
+
keysrc = hwkey.type;
297
+
if (keysrc >= VERSAL_AES_USER_KEY_1 &&
298
+
keysrc <= VERSAL_AES_USER_KEY_7) {
299
+
tfm_ctx->keysrc = keysrc;
300
+
tfm_ctx->keylen = sizeof(struct xilinx_hwkey_info);
301
+
return 0;
302
+
}
303
+
return -EINVAL;
304
+
}
305
+
306
+
if (keylen == AES_KEYSIZE_256 || keylen == AES_KEYSIZE_128) {
307
+
tfm_ctx->keylen = keylen;
308
+
memcpy(tfm_ctx->key, key, keylen);
309
+
dma_sync_single_for_device(tfm_ctx->dev, tfm_ctx->key_dma_addr,
310
+
AES_KEYSIZE_256,
311
+
DMA_TO_DEVICE);
312
+
}
313
+
314
+
tfm_ctx->fbk_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
315
+
tfm_ctx->fbk_cipher->base.crt_flags |= (aead->base.crt_flags &
316
+
CRYPTO_TFM_REQ_MASK);
317
+
err = crypto_aead_setkey(tfm_ctx->fbk_cipher, key, keylen);
318
+
if (!err)
319
+
tfm_ctx->keylen = keylen;
320
+
321
+
return err;
322
+
}
323
+
324
+
static int versal_paes_aead_setkey(struct crypto_aead *aead, const u8 *key,
325
+
unsigned int keylen)
326
+
{
327
+
struct crypto_tfm *tfm = crypto_aead_tfm(aead);
328
+
struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_tfm_ctx(tfm);
329
+
struct xilinx_hwkey_info hwkey;
330
+
unsigned char keysrc;
331
+
int err = 0;
332
+
333
+
if (keylen != sizeof(struct xilinx_hwkey_info))
334
+
return -EINVAL;
335
+
336
+
memcpy(&hwkey, key, sizeof(struct xilinx_hwkey_info));
337
+
if (hwkey.magic != XILINX_KEY_MAGIC)
338
+
return -EINVAL;
339
+
340
+
keysrc = hwkey.type;
341
+
342
+
switch (keysrc) {
343
+
case VERSAL_AES_EFUSE_USER_KEY_0:
344
+
case VERSAL_AES_EFUSE_USER_KEY_1:
345
+
case VERSAL_AES_EFUSE_USER_RED_KEY_0:
346
+
case VERSAL_AES_EFUSE_USER_RED_KEY_1:
347
+
case VERSAL_AES_PUF_KEY:
348
+
tfm_ctx->keysrc = keysrc;
349
+
tfm_ctx->keylen = sizeof(struct xilinx_hwkey_info);
350
+
break;
351
+
default:
352
+
err = -EINVAL;
353
+
break;
354
+
}
355
+
356
+
return err;
357
+
}
358
+
495
359
static int xilinx_aes_aead_setauthsize(struct crypto_aead *aead,
496
360
unsigned int authsize)
497
361
{
···
620
328
return crypto_transfer_aead_request_to_engine(drv_ctx->aead_dev->engine, req);
621
329
}
622
330
331
+
static int versal_aes_aead_encrypt(struct aead_request *req)
332
+
{
333
+
struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
334
+
struct crypto_aead *aead = crypto_aead_reqtfm(req);
335
+
struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
336
+
struct aead_alg *alg = crypto_aead_alg(aead);
337
+
struct xilinx_aead_alg *drv_ctx;
338
+
int err;
339
+
340
+
drv_ctx = container_of(alg, struct xilinx_aead_alg, aead.base);
341
+
rq_ctx->op = XILINX_AES_ENCRYPT;
342
+
if (tfm_ctx->keysrc >= VERSAL_AES_USER_KEY_0 &&
343
+
tfm_ctx->keysrc <= VERSAL_AES_USER_KEY_7 &&
344
+
tfm_ctx->keylen == sizeof(struct xilinx_hwkey_info))
345
+
return -EINVAL;
346
+
err = versal_fallback_check(tfm_ctx, req);
347
+
if (err && (tfm_ctx->keysrc < VERSAL_AES_USER_KEY_0 ||
348
+
tfm_ctx->keysrc > VERSAL_AES_USER_KEY_7))
349
+
return -EOPNOTSUPP;
350
+
if (err)
351
+
return xilinx_aes_fallback_crypt(req, true);
352
+
353
+
return crypto_transfer_aead_request_to_engine(drv_ctx->aead_dev->engine, req);
354
+
}
355
+
623
356
static int zynqmp_aes_aead_decrypt(struct aead_request *req)
624
357
{
625
358
struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
···
685
368
return 0;
686
369
}
687
370
371
+
static int versal_aes_aead_decrypt(struct aead_request *req)
372
+
{
373
+
struct xilinx_aead_req_ctx *rq_ctx = aead_request_ctx(req);
374
+
struct crypto_aead *aead = crypto_aead_reqtfm(req);
375
+
struct xilinx_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
376
+
struct aead_alg *alg = crypto_aead_alg(aead);
377
+
struct xilinx_aead_alg *drv_ctx;
378
+
int err;
379
+
380
+
drv_ctx = container_of(alg, struct xilinx_aead_alg, aead.base);
381
+
rq_ctx->op = XILINX_AES_DECRYPT;
382
+
if (tfm_ctx->keysrc >= VERSAL_AES_USER_KEY_0 &&
383
+
tfm_ctx->keysrc <= VERSAL_AES_USER_KEY_7 &&
384
+
tfm_ctx->keylen == sizeof(struct xilinx_hwkey_info))
385
+
return -EINVAL;
386
+
387
+
err = versal_fallback_check(tfm_ctx, req);
388
+
if (err &&
389
+
(tfm_ctx->keysrc < VERSAL_AES_USER_KEY_0 ||
390
+
tfm_ctx->keysrc > VERSAL_AES_USER_KEY_7))
391
+
return -EOPNOTSUPP;
392
+
if (err)
393
+
return xilinx_aes_fallback_crypt(req, false);
394
+
395
+
return crypto_transfer_aead_request_to_engine(drv_ctx->aead_dev->engine, req);
396
+
}
397
+
688
398
static int xilinx_aes_aead_init(struct crypto_aead *aead)
689
399
{
690
400
struct crypto_tfm *tfm = crypto_aead_tfm(aead);
···
728
384
CRYPTO_ALG_NEED_FALLBACK);
729
385
730
386
if (IS_ERR(tfm_ctx->fbk_cipher)) {
731
-
pr_err("%s() Error: failed to allocate fallback for %s\n",
732
-
__func__, drv_ctx->aead.base.base.cra_name);
387
+
dev_err(tfm_ctx->dev, "failed to allocate fallback for %s\n",
388
+
drv_ctx->aead.base.base.cra_name);
733
389
return PTR_ERR(tfm_ctx->fbk_cipher);
734
390
}
735
391
tfm_ctx->key = kmalloc(AES_KEYSIZE_256, GFP_KERNEL);
···
777
433
778
434
static struct xilinx_aead_alg zynqmp_aes_algs[] = {
779
435
{
436
+
.aes_aead_cipher = zynqmp_aes_aead_cipher,
780
437
.aead.base = {
781
438
.setkey = zynqmp_aes_aead_setkey,
782
439
.setauthsize = xilinx_aes_aead_setauthsize,
···
807
462
.dma_bit_mask = ZYNQMP_DMA_BIT_MASK,
808
463
},
809
464
{
465
+
.aes_aead_cipher = zynqmp_aes_aead_cipher,
810
466
.aead.base = {
811
467
.setkey = zynqmp_paes_aead_setkey,
812
468
.setauthsize = xilinx_aes_aead_setauthsize,
···
838
492
{ /* sentinel */ }
839
493
};
840
494
495
+
static struct xilinx_aead_alg versal_aes_algs[] = {
496
+
{
497
+
.aes_aead_cipher = versal_aes_aead_cipher,
498
+
.aead.base = {
499
+
.setkey = versal_aes_aead_setkey,
500
+
.setauthsize = xilinx_aes_aead_setauthsize,
501
+
.encrypt = versal_aes_aead_encrypt,
502
+
.decrypt = versal_aes_aead_decrypt,
503
+
.init = xilinx_aes_aead_init,
504
+
.exit = xilinx_aes_aead_exit,
505
+
.ivsize = GCM_AES_IV_SIZE,
506
+
.maxauthsize = XILINX_AES_AUTH_SIZE,
507
+
.base = {
508
+
.cra_name = "gcm(aes)",
509
+
.cra_driver_name = "versal-aes-gcm",
510
+
.cra_priority = 300,
511
+
.cra_flags = CRYPTO_ALG_TYPE_AEAD |
512
+
CRYPTO_ALG_ASYNC |
513
+
CRYPTO_ALG_ALLOCATES_MEMORY |
514
+
CRYPTO_ALG_KERN_DRIVER_ONLY |
515
+
CRYPTO_ALG_NEED_FALLBACK,
516
+
.cra_blocksize = XILINX_AES_BLK_SIZE,
517
+
.cra_ctxsize = sizeof(struct xilinx_aead_tfm_ctx),
518
+
.cra_module = THIS_MODULE,
519
+
}
520
+
},
521
+
.aead.op = {
522
+
.do_one_request = xilinx_handle_aes_req,
523
+
},
524
+
.dma_bit_mask = VERSAL_DMA_BIT_MASK,
525
+
},
526
+
{
527
+
.aes_aead_cipher = versal_aes_aead_cipher,
528
+
.aead.base = {
529
+
.setkey = versal_paes_aead_setkey,
530
+
.setauthsize = xilinx_aes_aead_setauthsize,
531
+
.encrypt = versal_aes_aead_encrypt,
532
+
.decrypt = versal_aes_aead_decrypt,
533
+
.init = xilinx_paes_aead_init,
534
+
.exit = xilinx_paes_aead_exit,
535
+
.ivsize = GCM_AES_IV_SIZE,
536
+
.maxauthsize = XILINX_AES_AUTH_SIZE,
537
+
.base = {
538
+
.cra_name = "gcm(paes)",
539
+
.cra_driver_name = "versal-paes-gcm",
540
+
.cra_priority = 300,
541
+
.cra_flags = CRYPTO_ALG_TYPE_AEAD |
542
+
CRYPTO_ALG_ASYNC |
543
+
CRYPTO_ALG_ALLOCATES_MEMORY |
544
+
CRYPTO_ALG_KERN_DRIVER_ONLY,
545
+
.cra_blocksize = XILINX_AES_BLK_SIZE,
546
+
.cra_ctxsize = sizeof(struct xilinx_aead_tfm_ctx),
547
+
.cra_module = THIS_MODULE,
548
+
}
549
+
},
550
+
.aead.op = {
551
+
.do_one_request = xilinx_handle_aes_req,
552
+
},
553
+
.dma_bit_mask = VERSAL_DMA_BIT_MASK,
554
+
},
555
+
{ /* sentinel */ }
556
+
};
557
+
841
558
static struct xlnx_feature aes_feature_map[] = {
842
559
{
843
560
.family = PM_ZYNQMP_FAMILY_CODE,
844
561
.feature_id = PM_SECURE_AES,
845
562
.data = zynqmp_aes_algs,
563
+
},
564
+
{
565
+
.family = PM_VERSAL_FAMILY_CODE,
566
+
.feature_id = XSECURE_API_AES_OP_INIT,
567
+
.data = versal_aes_algs,
846
568
},
847
569
{ /* sentinel */ }
848
570
};
···
948
534
aead_dev->engine = crypto_engine_alloc_init(dev, 1);
949
535
if (!aead_dev->engine) {
950
536
dev_err(dev, "Cannot alloc AES engine\n");
951
-
err = -ENOMEM;
952
-
goto err_engine;
537
+
return -ENOMEM;
953
538
}
954
539
955
540
err = crypto_engine_start(aead_dev->engine);
956
541
if (err) {
957
542
dev_err(dev, "Cannot start AES engine\n");
958
-
goto err_engine;
543
+
goto err_engine_start;
959
544
}
960
545
961
546
for (i = 0; aead_dev->aead_algs[i].dma_bit_mask; i++) {
···
965
552
goto err_alg_register;
966
553
}
967
554
}
968
-
return 0;
969
555
970
556
return 0;
971
557
972
558
err_alg_register:
973
559
while (i > 0)
974
560
crypto_engine_unregister_aead(&aead_dev->aead_algs[--i].aead);
975
-
err_engine:
561
+
err_engine_start:
976
562
crypto_engine_exit(aead_dev->engine);
977
563
978
564
return err;