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drm/i915/power: Remove i915_power_well_desc::has_vga

We no longer have any need for the has_vga flag in the
display power well descriptor. Get rid of it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251208182637.334-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

+2 -18
-13
drivers/gpu/drm/i915/display/intel_display_power_map.c
··· 112 112 .id = HSW_DISP_PW_GLOBAL), 113 113 ), 114 114 .ops = &hsw_power_well_ops, 115 - .has_vga = true, 116 115 }, 117 116 }; 118 117 ··· 145 146 .id = HSW_DISP_PW_GLOBAL), 146 147 ), 147 148 .ops = &hsw_power_well_ops, 148 - .has_vga = true, 149 149 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 150 150 }, 151 151 }; ··· 388 390 .id = SKL_DISP_PW_2), 389 391 ), 390 392 .ops = &hsw_power_well_ops, 391 - .has_vga = true, 392 393 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 393 394 .has_fuses = true, 394 395 }, { ··· 466 469 .id = SKL_DISP_PW_2), 467 470 ), 468 471 .ops = &hsw_power_well_ops, 469 - .has_vga = true, 470 472 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 471 473 .has_fuses = true, 472 474 }, { ··· 568 572 .id = SKL_DISP_PW_2), 569 573 ), 570 574 .ops = &hsw_power_well_ops, 571 - .has_vga = true, 572 575 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 573 576 .has_fuses = true, 574 577 }, { ··· 743 748 .id = ICL_DISP_PW_3), 744 749 ), 745 750 .ops = &hsw_power_well_ops, 746 - .has_vga = true, 747 751 .irq_pipe_mask = BIT(PIPE_B), 748 752 .has_fuses = true, 749 753 }, { ··· 908 914 .id = ICL_DISP_PW_3), 909 915 ), 910 916 .ops = &hsw_power_well_ops, 911 - .has_vga = true, 912 917 .irq_pipe_mask = BIT(PIPE_B), 913 918 .has_fuses = true, 914 919 }, { ··· 1064 1071 ), 1065 1072 .ops = &hsw_power_well_ops, 1066 1073 .irq_pipe_mask = BIT(PIPE_B), 1067 - .has_vga = true, 1068 1074 .has_fuses = true, 1069 1075 }, { 1070 1076 .instances = &I915_PW_INSTANCES( ··· 1158 1166 ), 1159 1167 .ops = &hsw_power_well_ops, 1160 1168 .irq_pipe_mask = BIT(PIPE_B), 1161 - .has_vga = true, 1162 1169 .has_fuses = true, 1163 1170 }, { 1164 1171 .instances = &I915_PW_INSTANCES( ··· 1316 1325 .id = SKL_DISP_PW_2), 1317 1326 ), 1318 1327 .ops = &hsw_power_well_ops, 1319 - .has_vga = true, 1320 1328 .has_fuses = true, 1321 1329 }, { 1322 1330 .instances = &I915_PW_INSTANCES( ··· 1472 1482 .id = SKL_DISP_PW_2), 1473 1483 ), 1474 1484 .ops = &hsw_power_well_ops, 1475 - .has_vga = true, 1476 1485 .has_fuses = true, 1477 1486 }, { 1478 1487 .instances = &I915_PW_INSTANCES( ··· 1638 1649 .id = SKL_DISP_PW_2), 1639 1650 ), 1640 1651 .ops = &hsw_power_well_ops, 1641 - .has_vga = true, 1642 1652 .has_fuses = true, 1643 1653 }, { 1644 1654 .instances = &I915_PW_INSTANCES( ··· 1710 1722 .id = SKL_DISP_PW_2), 1711 1723 ), 1712 1724 .ops = &hsw_power_well_ops, 1713 - .has_vga = true, 1714 1725 .has_fuses = true, 1715 1726 }, { 1716 1727 .instances = &I915_PW_INSTANCES(
+2 -3
drivers/gpu/drm/i915/display/intel_display_power_well.c
··· 202 202 * requesting it to be enabled. 203 203 */ 204 204 static void hsw_power_well_post_enable(struct intel_display *display, 205 - u8 irq_pipe_mask, bool has_vga) 205 + u8 irq_pipe_mask) 206 206 { 207 207 if (irq_pipe_mask) 208 208 gen8_irq_power_well_post_enable(display, irq_pipe_mask); ··· 415 415 } 416 416 417 417 hsw_power_well_post_enable(display, 418 - power_well->desc->irq_pipe_mask, 419 - power_well->desc->has_vga); 418 + power_well->desc->irq_pipe_mask); 420 419 } 421 420 422 421 static void hsw_power_well_disable(struct intel_display *display,
-2
drivers/gpu/drm/i915/display/intel_display_power_well.h
··· 103 103 * the well enabled. 104 104 */ 105 105 u16 fixed_enable_delay:1; 106 - /* The pw is backing the VGA functionality */ 107 - u16 has_vga:1; 108 106 u16 has_fuses:1; 109 107 /* 110 108 * The pw is for an ICL+ TypeC PHY port in