Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-5.6-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
"Some more powerpc fixes for 5.6. This is two weeks worth as I was out
sick last week:
- Three fixes for the recently added VMAP_STACK on 32-bit.
- Three fixes related to hugepages on 8xx (32-bit).
- A fix for a bug in our transactional memory handling that could
lead to a kernel crash if we saw a page fault during signal
delivery.
- A fix for a deadlock in our PCI EEH (Enhanced Error Handling) code.
- A couple of other minor fixes.
Thanks to: Christophe Leroy, Erhard F, Frederic Barrat, Gustavo Luiz
Duarte, Larry Finger, Leonardo Bras, Oliver O'Halloran, Sam Bobroff"
* tag 'powerpc-5.6-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/entry: Fix an #if which should be an #ifdef in entry_32.S
powerpc/xmon: Fix whitespace handling in getstring()
powerpc/6xx: Fix power_save_ppc32_restore() with CONFIG_VMAP_STACK
powerpc/chrp: Fix enter_rtas() with CONFIG_VMAP_STACK
powerpc/32s: Fix DSI and ISI exceptions for CONFIG_VMAP_STACK
powerpc/tm: Fix clearing MSR[TS] in current when reclaiming on signal delivery
powerpc/8xx: Fix clearing of bits 20-23 in ITLB miss
powerpc/hugetlb: Fix 8M hugepages on 8xx
powerpc/hugetlb: Fix 512k hugepages on 8xx with 16k page size
powerpc/eeh: Fix deadlock handling dead PHB
+308
-99
+5
arch/powerpc/include/asm/page.h
+5
arch/powerpc/include/asm/page.h
···
295
295
/*
296
296
* Some number of bits at the level of the page table that points to
297
297
* a hugepte are used to encode the size. This masks those bits.
298
+
* On 8xx, HW assistance requires 4k alignment for the hugepte.
298
299
*/
300
+
#ifdef CONFIG_PPC_8xx
301
+
#define HUGEPD_SHIFT_MASK 0xfff
302
+
#else
299
303
#define HUGEPD_SHIFT_MASK 0x3f
304
+
#endif
300
305
301
306
#ifndef __ASSEMBLY__
302
307
+4
arch/powerpc/include/asm/processor.h
+4
arch/powerpc/include/asm/processor.h
+12
arch/powerpc/kernel/asm-offsets.c
+12
arch/powerpc/kernel/asm-offsets.c
···
132
132
OFFSET(SRR1, thread_struct, srr1);
133
133
OFFSET(DAR, thread_struct, dar);
134
134
OFFSET(DSISR, thread_struct, dsisr);
135
+
#ifdef CONFIG_PPC_BOOK3S_32
136
+
OFFSET(THR0, thread_struct, r0);
137
+
OFFSET(THR3, thread_struct, r3);
138
+
OFFSET(THR4, thread_struct, r4);
139
+
OFFSET(THR5, thread_struct, r5);
140
+
OFFSET(THR6, thread_struct, r6);
141
+
OFFSET(THR8, thread_struct, r8);
142
+
OFFSET(THR9, thread_struct, r9);
143
+
OFFSET(THR11, thread_struct, r11);
144
+
OFFSET(THLR, thread_struct, lr);
145
+
OFFSET(THCTR, thread_struct, ctr);
146
+
#endif
135
147
#endif
136
148
#ifdef CONFIG_SPE
137
149
OFFSET(THREAD_EVR0, thread_struct, evr[0]);
+11
-10
arch/powerpc/kernel/eeh_driver.c
+11
-10
arch/powerpc/kernel/eeh_driver.c
···
1184
1184
eeh_pe_state_mark(pe, EEH_PE_RECOVERING);
1185
1185
eeh_handle_normal_event(pe);
1186
1186
} else {
1187
+
eeh_for_each_pe(pe, tmp_pe)
1188
+
eeh_pe_for_each_dev(tmp_pe, edev, tmp_edev)
1189
+
edev->mode &= ~EEH_DEV_NO_HANDLER;
1190
+
1191
+
/* Notify all devices to be down */
1192
+
eeh_pe_state_clear(pe, EEH_PE_PRI_BUS, true);
1193
+
eeh_set_channel_state(pe, pci_channel_io_perm_failure);
1194
+
eeh_pe_report(
1195
+
"error_detected(permanent failure)", pe,
1196
+
eeh_report_failure, NULL);
1197
+
1187
1198
pci_lock_rescan_remove();
1188
1199
list_for_each_entry(hose, &hose_list, list_node) {
1189
1200
phb_pe = eeh_phb_pe_get(hose);
···
1203
1192
(phb_pe->state & EEH_PE_RECOVERING))
1204
1193
continue;
1205
1194
1206
-
eeh_for_each_pe(pe, tmp_pe)
1207
-
eeh_pe_for_each_dev(tmp_pe, edev, tmp_edev)
1208
-
edev->mode &= ~EEH_DEV_NO_HANDLER;
1209
-
1210
-
/* Notify all devices to be down */
1211
-
eeh_pe_state_clear(pe, EEH_PE_PRI_BUS, true);
1212
-
eeh_set_channel_state(pe, pci_channel_io_perm_failure);
1213
-
eeh_pe_report(
1214
-
"error_detected(permanent failure)", pe,
1215
-
eeh_report_failure, NULL);
1216
1195
bus = eeh_pe_bus_get(phb_pe);
1217
1196
if (!bus) {
1218
1197
pr_err("%s: Cannot find PCI bus for "
+9
-4
arch/powerpc/kernel/entry_32.S
+9
-4
arch/powerpc/kernel/entry_32.S
···
783
783
1: lis r3,exc_exit_restart_end@ha
784
784
addi r3,r3,exc_exit_restart_end@l
785
785
cmplw r12,r3
786
-
#if CONFIG_PPC_BOOK3S_601
786
+
#ifdef CONFIG_PPC_BOOK3S_601
787
787
bge 2b
788
788
#else
789
789
bge 3f
···
791
791
lis r4,exc_exit_restart@ha
792
792
addi r4,r4,exc_exit_restart@l
793
793
cmplw r12,r4
794
-
#if CONFIG_PPC_BOOK3S_601
794
+
#ifdef CONFIG_PPC_BOOK3S_601
795
795
blt 2b
796
796
#else
797
797
blt 3f
···
1354
1354
mtspr SPRN_SRR0,r8
1355
1355
mtspr SPRN_SRR1,r9
1356
1356
RFI
1357
-
1: tophys(r9,r1)
1357
+
1: tophys_novmstack r9, r1
1358
+
#ifdef CONFIG_VMAP_STACK
1359
+
li r0, MSR_KERNEL & ~MSR_IR /* can take DTLB miss */
1360
+
mtmsr r0
1361
+
isync
1362
+
#endif
1358
1363
lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1359
1364
lwz r9,8(r9) /* original msr value */
1360
1365
addi r1,r1,INT_FRAME_SIZE
1361
1366
li r0,0
1362
-
tophys(r7, r2)
1367
+
tophys_novmstack r7, r2
1363
1368
stw r0, THREAD + RTAS_SP(r7)
1364
1369
mtspr SPRN_SRR0,r8
1365
1370
mtspr SPRN_SRR1,r9
+150
-5
arch/powerpc/kernel/head_32.S
+150
-5
arch/powerpc/kernel/head_32.S
···
290
290
7: EXCEPTION_PROLOG_2
291
291
addi r3,r1,STACK_FRAME_OVERHEAD
292
292
#ifdef CONFIG_PPC_CHRP
293
-
bne cr1,1f
293
+
#ifdef CONFIG_VMAP_STACK
294
+
mfspr r4, SPRN_SPRG_THREAD
295
+
tovirt(r4, r4)
296
+
lwz r4, RTAS_SP(r4)
297
+
cmpwi cr1, r4, 0
294
298
#endif
295
-
EXC_XFER_STD(0x200, machine_check_exception)
296
-
#ifdef CONFIG_PPC_CHRP
297
-
1: b machine_check_in_rtas
299
+
beq cr1, machine_check_tramp
300
+
b machine_check_in_rtas
301
+
#else
302
+
b machine_check_tramp
298
303
#endif
299
304
300
305
/* Data access exception. */
301
306
. = 0x300
302
307
DO_KVM 0x300
303
308
DataAccess:
309
+
#ifdef CONFIG_VMAP_STACK
310
+
mtspr SPRN_SPRG_SCRATCH0,r10
311
+
mfspr r10, SPRN_SPRG_THREAD
312
+
BEGIN_MMU_FTR_SECTION
313
+
stw r11, THR11(r10)
314
+
mfspr r10, SPRN_DSISR
315
+
mfcr r11
316
+
#ifdef CONFIG_PPC_KUAP
317
+
andis. r10, r10, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH | DSISR_PROTFAULT)@h
318
+
#else
319
+
andis. r10, r10, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
320
+
#endif
321
+
mfspr r10, SPRN_SPRG_THREAD
322
+
beq hash_page_dsi
323
+
.Lhash_page_dsi_cont:
324
+
mtcr r11
325
+
lwz r11, THR11(r10)
326
+
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
327
+
mtspr SPRN_SPRG_SCRATCH1,r11
328
+
mfspr r11, SPRN_DAR
329
+
stw r11, DAR(r10)
330
+
mfspr r11, SPRN_DSISR
331
+
stw r11, DSISR(r10)
332
+
mfspr r11, SPRN_SRR0
333
+
stw r11, SRR0(r10)
334
+
mfspr r11, SPRN_SRR1 /* check whether user or kernel */
335
+
stw r11, SRR1(r10)
336
+
mfcr r10
337
+
andi. r11, r11, MSR_PR
338
+
339
+
EXCEPTION_PROLOG_1
340
+
b handle_page_fault_tramp_1
341
+
#else /* CONFIG_VMAP_STACK */
304
342
EXCEPTION_PROLOG handle_dar_dsisr=1
305
343
get_and_save_dar_dsisr_on_stack r4, r5, r11
306
344
BEGIN_MMU_FTR_SECTION
···
354
316
FTR_SECTION_ELSE
355
317
b handle_page_fault_tramp_2
356
318
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
319
+
#endif /* CONFIG_VMAP_STACK */
357
320
358
321
/* Instruction access exception. */
359
322
. = 0x400
360
323
DO_KVM 0x400
361
324
InstructionAccess:
325
+
#ifdef CONFIG_VMAP_STACK
326
+
mtspr SPRN_SPRG_SCRATCH0,r10
327
+
mtspr SPRN_SPRG_SCRATCH1,r11
328
+
mfspr r10, SPRN_SPRG_THREAD
329
+
mfspr r11, SPRN_SRR0
330
+
stw r11, SRR0(r10)
331
+
mfspr r11, SPRN_SRR1 /* check whether user or kernel */
332
+
stw r11, SRR1(r10)
333
+
mfcr r10
334
+
BEGIN_MMU_FTR_SECTION
335
+
andis. r11, r11, SRR1_ISI_NOPT@h /* no pte found? */
336
+
bne hash_page_isi
337
+
.Lhash_page_isi_cont:
338
+
mfspr r11, SPRN_SRR1 /* check whether user or kernel */
339
+
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
340
+
andi. r11, r11, MSR_PR
341
+
342
+
EXCEPTION_PROLOG_1
343
+
EXCEPTION_PROLOG_2
344
+
#else /* CONFIG_VMAP_STACK */
362
345
EXCEPTION_PROLOG
363
346
andis. r0,r9,SRR1_ISI_NOPT@h /* no pte found? */
364
347
beq 1f /* if so, try to put a PTE */
···
388
329
BEGIN_MMU_FTR_SECTION
389
330
bl hash_page
390
331
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
332
+
#endif /* CONFIG_VMAP_STACK */
391
333
1: mr r4,r12
392
334
andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
393
335
stw r4, _DAR(r11)
···
404
344
EXCEPTION_PROLOG handle_dar_dsisr=1
405
345
save_dar_dsisr_on_stack r4, r5, r11
406
346
addi r3,r1,STACK_FRAME_OVERHEAD
407
-
EXC_XFER_STD(0x600, alignment_exception)
347
+
b alignment_exception_tramp
408
348
409
349
/* Program check exception */
410
350
EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
···
705
645
706
646
. = 0x3000
707
647
648
+
machine_check_tramp:
649
+
EXC_XFER_STD(0x200, machine_check_exception)
650
+
651
+
alignment_exception_tramp:
652
+
EXC_XFER_STD(0x600, alignment_exception)
653
+
708
654
handle_page_fault_tramp_1:
655
+
#ifdef CONFIG_VMAP_STACK
656
+
EXCEPTION_PROLOG_2 handle_dar_dsisr=1
657
+
#endif
709
658
lwz r4, _DAR(r11)
710
659
lwz r5, _DSISR(r11)
711
660
/* fall through */
712
661
handle_page_fault_tramp_2:
713
662
EXC_XFER_LITE(0x300, handle_page_fault)
714
663
664
+
#ifdef CONFIG_VMAP_STACK
665
+
.macro save_regs_thread thread
666
+
stw r0, THR0(\thread)
667
+
stw r3, THR3(\thread)
668
+
stw r4, THR4(\thread)
669
+
stw r5, THR5(\thread)
670
+
stw r6, THR6(\thread)
671
+
stw r8, THR8(\thread)
672
+
stw r9, THR9(\thread)
673
+
mflr r0
674
+
stw r0, THLR(\thread)
675
+
mfctr r0
676
+
stw r0, THCTR(\thread)
677
+
.endm
678
+
679
+
.macro restore_regs_thread thread
680
+
lwz r0, THLR(\thread)
681
+
mtlr r0
682
+
lwz r0, THCTR(\thread)
683
+
mtctr r0
684
+
lwz r0, THR0(\thread)
685
+
lwz r3, THR3(\thread)
686
+
lwz r4, THR4(\thread)
687
+
lwz r5, THR5(\thread)
688
+
lwz r6, THR6(\thread)
689
+
lwz r8, THR8(\thread)
690
+
lwz r9, THR9(\thread)
691
+
.endm
692
+
693
+
hash_page_dsi:
694
+
save_regs_thread r10
695
+
mfdsisr r3
696
+
mfdar r4
697
+
mfsrr0 r5
698
+
mfsrr1 r9
699
+
rlwinm r3, r3, 32 - 15, _PAGE_RW /* DSISR_STORE -> _PAGE_RW */
700
+
bl hash_page
701
+
mfspr r10, SPRN_SPRG_THREAD
702
+
restore_regs_thread r10
703
+
b .Lhash_page_dsi_cont
704
+
705
+
hash_page_isi:
706
+
mr r11, r10
707
+
mfspr r10, SPRN_SPRG_THREAD
708
+
save_regs_thread r10
709
+
li r3, 0
710
+
lwz r4, SRR0(r10)
711
+
lwz r9, SRR1(r10)
712
+
bl hash_page
713
+
mfspr r10, SPRN_SPRG_THREAD
714
+
restore_regs_thread r10
715
+
mr r10, r11
716
+
b .Lhash_page_isi_cont
717
+
718
+
.globl fast_hash_page_return
719
+
fast_hash_page_return:
720
+
andis. r10, r9, SRR1_ISI_NOPT@h /* Set on ISI, cleared on DSI */
721
+
mfspr r10, SPRN_SPRG_THREAD
722
+
restore_regs_thread r10
723
+
bne 1f
724
+
725
+
/* DSI */
726
+
mtcr r11
727
+
lwz r11, THR11(r10)
728
+
mfspr r10, SPRN_SPRG_SCRATCH0
729
+
SYNC
730
+
RFI
731
+
732
+
1: /* ISI */
733
+
mtcr r11
734
+
mfspr r11, SPRN_SPRG_SCRATCH1
735
+
mfspr r10, SPRN_SPRG_SCRATCH0
736
+
SYNC
737
+
RFI
738
+
715
739
stack_overflow:
716
740
vmap_stack_overflow_exception
741
+
#endif
717
742
718
743
AltiVecUnavailable:
719
744
EXCEPTION_PROLOG
+20
-1
arch/powerpc/kernel/head_32.h
+20
-1
arch/powerpc/kernel/head_32.h
···
64
64
.endm
65
65
66
66
.macro EXCEPTION_PROLOG_2 handle_dar_dsisr=0
67
+
#if defined(CONFIG_VMAP_STACK) && defined(CONFIG_PPC_BOOK3S)
68
+
BEGIN_MMU_FTR_SECTION
69
+
mtcr r10
70
+
FTR_SECTION_ELSE
71
+
stw r10, _CCR(r11)
72
+
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
73
+
#else
67
74
stw r10,_CCR(r11) /* save registers */
75
+
#endif
76
+
mfspr r10, SPRN_SPRG_SCRATCH0
68
77
stw r12,GPR12(r11)
69
78
stw r9,GPR9(r11)
70
-
mfspr r10,SPRN_SPRG_SCRATCH0
71
79
stw r10,GPR10(r11)
80
+
#if defined(CONFIG_VMAP_STACK) && defined(CONFIG_PPC_BOOK3S)
81
+
BEGIN_MMU_FTR_SECTION
82
+
mfcr r10
83
+
stw r10, _CCR(r11)
84
+
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
85
+
#endif
72
86
mfspr r12,SPRN_SPRG_SCRATCH1
73
87
stw r12,GPR11(r11)
74
88
mflr r10
···
97
83
stw r10, _DSISR(r11)
98
84
.endif
99
85
lwz r9, SRR1(r12)
86
+
#if defined(CONFIG_VMAP_STACK) && defined(CONFIG_PPC_BOOK3S)
87
+
BEGIN_MMU_FTR_SECTION
88
+
andi. r10, r9, MSR_PR
89
+
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
90
+
#endif
100
91
lwz r12, SRR0(r12)
101
92
#else
102
93
mfspr r12,SPRN_SRR0
+1
-1
arch/powerpc/kernel/head_8xx.S
+1
-1
arch/powerpc/kernel/head_8xx.S
···
256
256
* set. All other Linux PTE bits control the behavior
257
257
* of the MMU.
258
258
*/
259
-
rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
259
+
rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
260
260
rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
261
261
ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
262
262
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
+8
arch/powerpc/kernel/idle_6xx.S
+8
arch/powerpc/kernel/idle_6xx.S
···
166
166
mfspr r9,SPRN_HID0
167
167
andis. r9,r9,HID0_NAP@h
168
168
beq 1f
169
+
#ifdef CONFIG_VMAP_STACK
170
+
addis r9, r11, nap_save_msscr0@ha
171
+
#else
169
172
addis r9,r11,(nap_save_msscr0-KERNELBASE)@ha
173
+
#endif
170
174
lwz r9,nap_save_msscr0@l(r9)
171
175
mtspr SPRN_MSSCR0, r9
172
176
sync
···
178
174
1:
179
175
END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
180
176
BEGIN_FTR_SECTION
177
+
#ifdef CONFIG_VMAP_STACK
178
+
addis r9, r11, nap_save_hid1@ha
179
+
#else
181
180
addis r9,r11,(nap_save_hid1-KERNELBASE)@ha
181
+
#endif
182
182
lwz r9,nap_save_hid1@l(r9)
183
183
mtspr SPRN_HID1, r9
184
184
END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX)
+15
-2
arch/powerpc/kernel/signal.c
+15
-2
arch/powerpc/kernel/signal.c
···
200
200
* normal/non-checkpointed stack pointer.
201
201
*/
202
202
203
+
unsigned long ret = tsk->thread.regs->gpr[1];
204
+
203
205
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
204
206
BUG_ON(tsk != current);
205
207
206
208
if (MSR_TM_ACTIVE(tsk->thread.regs->msr)) {
209
+
preempt_disable();
207
210
tm_reclaim_current(TM_CAUSE_SIGNAL);
208
211
if (MSR_TM_TRANSACTIONAL(tsk->thread.regs->msr))
209
-
return tsk->thread.ckpt_regs.gpr[1];
212
+
ret = tsk->thread.ckpt_regs.gpr[1];
213
+
214
+
/*
215
+
* If we treclaim, we must clear the current thread's TM bits
216
+
* before re-enabling preemption. Otherwise we might be
217
+
* preempted and have the live MSR[TS] changed behind our back
218
+
* (tm_recheckpoint_new_task() would recheckpoint). Besides, we
219
+
* enter the signal handler in non-transactional state.
220
+
*/
221
+
tsk->thread.regs->msr &= ~MSR_TS_MASK;
222
+
preempt_enable();
210
223
}
211
224
#endif
212
-
return tsk->thread.regs->gpr[1];
225
+
return ret;
213
226
}
+14
-14
arch/powerpc/kernel/signal_32.c
+14
-14
arch/powerpc/kernel/signal_32.c
···
489
489
*/
490
490
static int save_tm_user_regs(struct pt_regs *regs,
491
491
struct mcontext __user *frame,
492
-
struct mcontext __user *tm_frame, int sigret)
492
+
struct mcontext __user *tm_frame, int sigret,
493
+
unsigned long msr)
493
494
{
494
-
unsigned long msr = regs->msr;
495
-
496
495
WARN_ON(tm_suspend_disabled);
497
-
498
-
/* Remove TM bits from thread's MSR. The MSR in the sigcontext
499
-
* just indicates to userland that we were doing a transaction, but we
500
-
* don't want to return in transactional state. This also ensures
501
-
* that flush_fp_to_thread won't set TIF_RESTORE_TM again.
502
-
*/
503
-
regs->msr &= ~MSR_TS_MASK;
504
496
505
497
/* Save both sets of general registers */
506
498
if (save_general_regs(¤t->thread.ckpt_regs, frame)
···
904
912
int sigret;
905
913
unsigned long tramp;
906
914
struct pt_regs *regs = tsk->thread.regs;
915
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
916
+
/* Save the thread's msr before get_tm_stackpointer() changes it */
917
+
unsigned long msr = regs->msr;
918
+
#endif
907
919
908
920
BUG_ON(tsk != current);
909
921
···
940
944
941
945
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
942
946
tm_frame = &rt_sf->uc_transact.uc_mcontext;
943
-
if (MSR_TM_ACTIVE(regs->msr)) {
947
+
if (MSR_TM_ACTIVE(msr)) {
944
948
if (__put_user((unsigned long)&rt_sf->uc_transact,
945
949
&rt_sf->uc.uc_link) ||
946
950
__put_user((unsigned long)tm_frame,
947
951
&rt_sf->uc_transact.uc_regs))
948
952
goto badframe;
949
-
if (save_tm_user_regs(regs, frame, tm_frame, sigret))
953
+
if (save_tm_user_regs(regs, frame, tm_frame, sigret, msr))
950
954
goto badframe;
951
955
}
952
956
else
···
1365
1369
int sigret;
1366
1370
unsigned long tramp;
1367
1371
struct pt_regs *regs = tsk->thread.regs;
1372
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1373
+
/* Save the thread's msr before get_tm_stackpointer() changes it */
1374
+
unsigned long msr = regs->msr;
1375
+
#endif
1368
1376
1369
1377
BUG_ON(tsk != current);
1370
1378
···
1402
1402
1403
1403
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1404
1404
tm_mctx = &frame->mctx_transact;
1405
-
if (MSR_TM_ACTIVE(regs->msr)) {
1405
+
if (MSR_TM_ACTIVE(msr)) {
1406
1406
if (save_tm_user_regs(regs, &frame->mctx, &frame->mctx_transact,
1407
-
sigret))
1407
+
sigret, msr))
1408
1408
goto badframe;
1409
1409
}
1410
1410
else
+10
-12
arch/powerpc/kernel/signal_64.c
+10
-12
arch/powerpc/kernel/signal_64.c
···
192
192
static long setup_tm_sigcontexts(struct sigcontext __user *sc,
193
193
struct sigcontext __user *tm_sc,
194
194
struct task_struct *tsk,
195
-
int signr, sigset_t *set, unsigned long handler)
195
+
int signr, sigset_t *set, unsigned long handler,
196
+
unsigned long msr)
196
197
{
197
198
/* When CONFIG_ALTIVEC is set, we _always_ setup v_regs even if the
198
199
* process never used altivec yet (MSR_VEC is zero in pt_regs of
···
208
207
elf_vrreg_t __user *tm_v_regs = sigcontext_vmx_regs(tm_sc);
209
208
#endif
210
209
struct pt_regs *regs = tsk->thread.regs;
211
-
unsigned long msr = tsk->thread.regs->msr;
212
210
long err = 0;
213
211
214
212
BUG_ON(tsk != current);
215
213
216
-
BUG_ON(!MSR_TM_ACTIVE(regs->msr));
214
+
BUG_ON(!MSR_TM_ACTIVE(msr));
217
215
218
216
WARN_ON(tm_suspend_disabled);
219
217
···
221
221
* the transaction and giveup_all() was called on reclaiming.
222
222
*/
223
223
msr |= tsk->thread.ckpt_regs.msr & (MSR_FP | MSR_VEC | MSR_VSX);
224
-
225
-
/* Remove TM bits from thread's MSR. The MSR in the sigcontext
226
-
* just indicates to userland that we were doing a transaction, but we
227
-
* don't want to return in transactional state. This also ensures
228
-
* that flush_fp_to_thread won't set TIF_RESTORE_TM again.
229
-
*/
230
-
regs->msr &= ~MSR_TS_MASK;
231
224
232
225
#ifdef CONFIG_ALTIVEC
233
226
err |= __put_user(v_regs, &sc->v_regs);
···
817
824
unsigned long newsp = 0;
818
825
long err = 0;
819
826
struct pt_regs *regs = tsk->thread.regs;
827
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
828
+
/* Save the thread's msr before get_tm_stackpointer() changes it */
829
+
unsigned long msr = regs->msr;
830
+
#endif
820
831
821
832
BUG_ON(tsk != current);
822
833
···
838
841
err |= __put_user(0, &frame->uc.uc_flags);
839
842
err |= __save_altstack(&frame->uc.uc_stack, regs->gpr[1]);
840
843
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
841
-
if (MSR_TM_ACTIVE(regs->msr)) {
844
+
if (MSR_TM_ACTIVE(msr)) {
842
845
/* The ucontext_t passed to userland points to the second
843
846
* ucontext_t (for transactional state) with its uc_link ptr.
844
847
*/
···
846
849
err |= setup_tm_sigcontexts(&frame->uc.uc_mcontext,
847
850
&frame->uc_transact.uc_mcontext,
848
851
tsk, ksig->sig, NULL,
849
-
(unsigned long)ksig->ka.sa.sa_handler);
852
+
(unsigned long)ksig->ka.sa.sa_handler,
853
+
msr);
850
854
} else
851
855
#endif
852
856
{
+23
-29
arch/powerpc/mm/book3s32/hash_low.S
+23
-29
arch/powerpc/mm/book3s32/hash_low.S
···
25
25
#include <asm/feature-fixups.h>
26
26
#include <asm/code-patching-asm.h>
27
27
28
-
#ifdef CONFIG_VMAP_STACK
29
-
#define ADDR_OFFSET 0
30
-
#else
31
-
#define ADDR_OFFSET PAGE_OFFSET
32
-
#endif
33
-
34
28
#ifdef CONFIG_SMP
35
29
.section .bss
36
30
.align 2
···
47
53
.text
48
54
_GLOBAL(hash_page)
49
55
#ifdef CONFIG_SMP
50
-
lis r8, (mmu_hash_lock - ADDR_OFFSET)@h
51
-
ori r8, r8, (mmu_hash_lock - ADDR_OFFSET)@l
56
+
lis r8, (mmu_hash_lock - PAGE_OFFSET)@h
57
+
ori r8, r8, (mmu_hash_lock - PAGE_OFFSET)@l
52
58
lis r0,0x0fff
53
59
b 10f
54
60
11: lwz r6,0(r8)
···
66
72
cmplw 0,r4,r0
67
73
ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
68
74
mfspr r5, SPRN_SPRG_PGDIR /* phys page-table root */
69
-
#ifdef CONFIG_VMAP_STACK
70
-
tovirt(r5, r5)
71
-
#endif
72
75
blt+ 112f /* assume user more likely */
73
-
lis r5, (swapper_pg_dir - ADDR_OFFSET)@ha /* if kernel address, use */
74
-
addi r5 ,r5 ,(swapper_pg_dir - ADDR_OFFSET)@l /* kernel page table */
76
+
lis r5, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
77
+
addi r5 ,r5 ,(swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
75
78
rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
76
79
112:
77
80
#ifndef CONFIG_PTE_64BIT
···
79
88
rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */
80
89
lwzx r8,r8,r5 /* Get L1 entry */
81
90
rlwinm. r8,r8,0,0,20 /* extract pt base address */
82
-
#endif
83
-
#ifdef CONFIG_VMAP_STACK
84
-
tovirt(r8, r8)
85
91
#endif
86
92
#ifdef CONFIG_SMP
87
93
beq- hash_page_out /* return if no mapping */
···
131
143
bne- retry /* retry if someone got there first */
132
144
133
145
mfsrin r3,r4 /* get segment reg for segment */
146
+
#ifndef CONFIG_VMAP_STACK
134
147
mfctr r0
135
148
stw r0,_CTR(r11)
149
+
#endif
136
150
bl create_hpte /* add the hash table entry */
137
151
138
152
#ifdef CONFIG_SMP
139
153
eieio
140
-
lis r8, (mmu_hash_lock - ADDR_OFFSET)@ha
154
+
lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha
141
155
li r0,0
142
-
stw r0, (mmu_hash_lock - ADDR_OFFSET)@l(r8)
156
+
stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
143
157
#endif
144
158
159
+
#ifdef CONFIG_VMAP_STACK
160
+
b fast_hash_page_return
161
+
#else
145
162
/* Return from the exception */
146
163
lwz r5,_CTR(r11)
147
164
mtctr r5
148
165
lwz r0,GPR0(r11)
149
166
lwz r8,GPR8(r11)
150
167
b fast_exception_return
168
+
#endif
151
169
152
170
#ifdef CONFIG_SMP
153
171
hash_page_out:
154
172
eieio
155
-
lis r8, (mmu_hash_lock - ADDR_OFFSET)@ha
173
+
lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha
156
174
li r0,0
157
-
stw r0, (mmu_hash_lock - ADDR_OFFSET)@l(r8)
175
+
stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
158
176
blr
159
177
#endif /* CONFIG_SMP */
160
178
···
335
341
patch_site 1f, patch__hash_page_A1
336
342
patch_site 2f, patch__hash_page_A2
337
343
/* Get the address of the primary PTE group in the hash table (r3) */
338
-
0: lis r0, (Hash_base - ADDR_OFFSET)@h /* base address of hash table */
344
+
0: lis r0, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */
339
345
1: rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
340
346
2: rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
341
347
xor r3,r3,r0 /* make primary hash */
···
349
355
beq+ 10f /* no PTE: go look for an empty slot */
350
356
tlbie r4
351
357
352
-
lis r4, (htab_hash_searches - ADDR_OFFSET)@ha
353
-
lwz r6, (htab_hash_searches - ADDR_OFFSET)@l(r4)
358
+
lis r4, (htab_hash_searches - PAGE_OFFSET)@ha
359
+
lwz r6, (htab_hash_searches - PAGE_OFFSET)@l(r4)
354
360
addi r6,r6,1 /* count how many searches we do */
355
-
stw r6, (htab_hash_searches - ADDR_OFFSET)@l(r4)
361
+
stw r6, (htab_hash_searches - PAGE_OFFSET)@l(r4)
356
362
357
363
/* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
358
364
mtctr r0
···
384
390
beq+ found_empty
385
391
386
392
/* update counter of times that the primary PTEG is full */
387
-
lis r4, (primary_pteg_full - ADDR_OFFSET)@ha
388
-
lwz r6, (primary_pteg_full - ADDR_OFFSET)@l(r4)
393
+
lis r4, (primary_pteg_full - PAGE_OFFSET)@ha
394
+
lwz r6, (primary_pteg_full - PAGE_OFFSET)@l(r4)
389
395
addi r6,r6,1
390
-
stw r6, (primary_pteg_full - ADDR_OFFSET)@l(r4)
396
+
stw r6, (primary_pteg_full - PAGE_OFFSET)@l(r4)
391
397
392
398
patch_site 0f, patch__hash_page_C
393
399
/* Search the secondary PTEG for an empty slot */
···
421
427
* lockup here but that shouldn't happen
422
428
*/
423
429
424
-
1: lis r4, (next_slot - ADDR_OFFSET)@ha /* get next evict slot */
425
-
lwz r6, (next_slot - ADDR_OFFSET)@l(r4)
430
+
1: lis r4, (next_slot - PAGE_OFFSET)@ha /* get next evict slot */
431
+
lwz r6, (next_slot - PAGE_OFFSET)@l(r4)
426
432
addi r6,r6,HPTE_SIZE /* search for candidate */
427
433
andi. r6,r6,7*HPTE_SIZE
428
434
stw r6,next_slot@l(r4)
+2
-8
arch/powerpc/mm/book3s32/mmu.c
+2
-8
arch/powerpc/mm/book3s32/mmu.c
···
413
413
void __init MMU_init_hw_patch(void)
414
414
{
415
415
unsigned int hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
416
-
unsigned int hash;
416
+
unsigned int hash = (unsigned int)Hash - PAGE_OFFSET;
417
417
418
418
if (ppc_md.progress)
419
419
ppc_md.progress("hash:patch", 0x345);
···
425
425
/*
426
426
* Patch up the instructions in hashtable.S:create_hpte
427
427
*/
428
-
if (IS_ENABLED(CONFIG_VMAP_STACK))
429
-
hash = (unsigned int)Hash;
430
-
else
431
-
hash = (unsigned int)Hash - PAGE_OFFSET;
432
-
433
428
modify_instruction_site(&patch__hash_page_A0, 0xffff, hash >> 16);
434
429
modify_instruction_site(&patch__hash_page_A1, 0x7c0, hash_mb << 6);
435
430
modify_instruction_site(&patch__hash_page_A2, 0x7c0, hash_mb2 << 6);
···
434
439
/*
435
440
* Patch up the instructions in hashtable.S:flush_hash_page
436
441
*/
437
-
modify_instruction_site(&patch__flush_hash_A0, 0xffff,
438
-
((unsigned int)Hash - PAGE_OFFSET) >> 16);
442
+
modify_instruction_site(&patch__flush_hash_A0, 0xffff, hash >> 16);
439
443
modify_instruction_site(&patch__flush_hash_A1, 0x7c0, hash_mb << 6);
440
444
modify_instruction_site(&patch__flush_hash_A2, 0x7c0, hash_mb2 << 6);
441
445
modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);
+18
-11
arch/powerpc/mm/hugetlbpage.c
+18
-11
arch/powerpc/mm/hugetlbpage.c
···
53
53
if (pshift >= pdshift) {
54
54
cachep = PGT_CACHE(PTE_T_ORDER);
55
55
num_hugepd = 1 << (pshift - pdshift);
56
+
new = NULL;
56
57
} else if (IS_ENABLED(CONFIG_PPC_8xx)) {
57
-
cachep = PGT_CACHE(PTE_INDEX_SIZE);
58
+
cachep = NULL;
58
59
num_hugepd = 1;
60
+
new = pte_alloc_one(mm);
59
61
} else {
60
62
cachep = PGT_CACHE(pdshift - pshift);
61
63
num_hugepd = 1;
64
+
new = NULL;
62
65
}
63
66
64
-
if (!cachep) {
67
+
if (!cachep && !new) {
65
68
WARN_ONCE(1, "No page table cache created for hugetlb tables");
66
69
return -ENOMEM;
67
70
}
68
71
69
-
new = kmem_cache_alloc(cachep, pgtable_gfp_flags(mm, GFP_KERNEL));
72
+
if (cachep)
73
+
new = kmem_cache_alloc(cachep, pgtable_gfp_flags(mm, GFP_KERNEL));
70
74
71
75
BUG_ON(pshift > HUGEPD_SHIFT_MASK);
72
76
BUG_ON((unsigned long)new & HUGEPD_SHIFT_MASK);
···
101
97
if (i < num_hugepd) {
102
98
for (i = i - 1 ; i >= 0; i--, hpdp--)
103
99
*hpdp = __hugepd(0);
104
-
kmem_cache_free(cachep, new);
100
+
if (cachep)
101
+
kmem_cache_free(cachep, new);
102
+
else
103
+
pte_free(mm, new);
105
104
} else {
106
105
kmemleak_ignore(new);
107
106
}
···
331
324
if (shift >= pdshift)
332
325
hugepd_free(tlb, hugepte);
333
326
else if (IS_ENABLED(CONFIG_PPC_8xx))
334
-
pgtable_free_tlb(tlb, hugepte,
335
-
get_hugepd_cache_index(PTE_INDEX_SIZE));
327
+
pgtable_free_tlb(tlb, hugepte, 0);
336
328
else
337
329
pgtable_free_tlb(tlb, hugepte,
338
330
get_hugepd_cache_index(pdshift - shift));
···
645
639
* if we have pdshift and shift value same, we don't
646
640
* use pgt cache for hugepd.
647
641
*/
648
-
if (pdshift > shift && IS_ENABLED(CONFIG_PPC_8xx))
649
-
pgtable_cache_add(PTE_INDEX_SIZE);
650
-
else if (pdshift > shift)
651
-
pgtable_cache_add(pdshift - shift);
652
-
else if (IS_ENABLED(CONFIG_PPC_FSL_BOOK3E) || IS_ENABLED(CONFIG_PPC_8xx))
642
+
if (pdshift > shift) {
643
+
if (!IS_ENABLED(CONFIG_PPC_8xx))
644
+
pgtable_cache_add(pdshift - shift);
645
+
} else if (IS_ENABLED(CONFIG_PPC_FSL_BOOK3E) ||
646
+
IS_ENABLED(CONFIG_PPC_8xx)) {
653
647
pgtable_cache_add(PTE_T_ORDER);
648
+
}
654
649
655
650
configured = true;
656
651
}
+1
-2
arch/powerpc/mm/kasan/kasan_init_32.c
+1
-2
arch/powerpc/mm/kasan/kasan_init_32.c
···
185
185
186
186
static void __init kasan_early_hash_table(void)
187
187
{
188
-
unsigned int hash = IS_ENABLED(CONFIG_VMAP_STACK) ? (unsigned int)early_hash :
189
-
__pa(early_hash);
188
+
unsigned int hash = __pa(early_hash);
190
189
191
190
modify_instruction_site(&patch__hash_page_A0, 0xffff, hash >> 16);
192
191
modify_instruction_site(&patch__flush_hash_A0, 0xffff, hash >> 16);