Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-next-2026-03-30' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
drm/i915 feature pull #2 for v7.1:
Refactoring and cleanups:
- Refactor LT PHY PLL handling to use the DPLL framework (Mika)
- Implement display register polling and waits in display code (Ville)
- Move PCH clock gating in display PCH file (Luca)
- Add shared stepping info header for i915 and display (Jani)
- Clean up GVT I2C command decoding (Jonathan)
- NV12 plane unlinking cleanups (Ville)
- Clean up NV12 DDB/watermark handling for pre-ICL platforms (Ville)
Fixes:
- An assortment of DSI fixes (Ville)
- Handle PORT_NONE in assert_port_valid() (Jonathan)
- Fix link failure without FBDEV emulation (Arnd Bergmann)
- Quirk disable panel replay on certain Dell XPS models (Jouni)
- Check if VESA DPCD AUX backlight is possible (Suraj)
Other:
- Mailmap update for Christoph (Christoph)
Signed-off-by: Dave Airlie <airlied@redhat.com>
# Conflicts:
# drivers/gpu/drm/i915/display/intel_plane.c
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/ac9dfdb745d5a67c519ea150a6f36f8f74b8760e@intel.com
+1007
-671
+1
.mailmap
+1
.mailmap
···
196
196
Christophe Ricard <christophe.ricard@gmail.com>
197
197
Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>
198
198
Christoph Hellwig <hch@lst.de>
199
+
Christoph Manszewski <c.manszewski@gmail.com> <christoph.manszewski@intel.com>
199
200
Chuck Lever <chuck.lever@oracle.com> <cel@kernel.org>
200
201
Chuck Lever <chuck.lever@oracle.com> <cel@netapp.com>
201
202
Chuck Lever <chuck.lever@oracle.com> <cel@citi.umich.edu>
+1
drivers/gpu/drm/i915/Makefile
+1
drivers/gpu/drm/i915/Makefile
+14
-7
drivers/gpu/drm/i915/display/icl_dsi.c
+14
-7
drivers/gpu/drm/i915/display/icl_dsi.c
···
711
711
dsi_trans = dsi_port_to_transcoder(port);
712
712
tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
713
713
714
-
if (intel_dsi->eotp_pkt)
714
+
if (intel_dsi->eot_pkt)
715
715
tmp &= ~EOTP_DISABLED;
716
716
else
717
717
tmp |= EOTP_DISABLED;
···
728
728
tmp |= CLK_ENTER_LP_AFTER_DATA;
729
729
else
730
730
tmp |= CLK_HS_CONTINUOUS;
731
+
732
+
if (DISPLAY_VER(display) >= 12 &&
733
+
intel_dsi->lp_clock_during_lpm)
734
+
tmp |= LP_CLK_DURING_LPM;
735
+
else
736
+
tmp &= ~LP_CLK_DURING_LPM;
731
737
732
738
/* configure buffer threshold limit to minimum */
733
739
tmp &= ~PIX_BUF_THRESHOLD_MASK;
···
771
765
}
772
766
}
773
767
774
-
if (DISPLAY_VER(display) >= 12) {
775
-
if (is_vid_mode(intel_dsi))
776
-
tmp |= BLANKING_PACKET_ENABLE;
777
-
}
768
+
if (DISPLAY_VER(display) >= 12 &&
769
+
is_vid_mode(intel_dsi) && intel_dsi->blanking_pkt)
770
+
tmp |= BLANKING_PACKET_ENABLE;
771
+
else
772
+
tmp &= ~BLANKING_PACKET_ENABLE;
778
773
779
774
/* program DSI operation mode */
780
775
if (is_vid_mode(intel_dsi)) {
···
895
888
* non-compressed link speeds, and simplifies down to the ratio between
896
889
* compressed and non-compressed bpp.
897
890
*/
898
-
if (crtc_state->dsc.compression_enable) {
891
+
if (is_vid_mode(intel_dsi) && crtc_state->dsc.compression_enable) {
899
892
mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
900
893
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
901
894
}
···
1509
1502
struct drm_display_mode *adjusted_mode =
1510
1503
&pipe_config->hw.adjusted_mode;
1511
1504
1512
-
if (pipe_config->dsc.compressed_bpp_x16) {
1505
+
if (is_vid_mode(intel_dsi) && pipe_config->dsc.compressed_bpp_x16) {
1513
1506
int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
1514
1507
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1515
1508
+2
-1
drivers/gpu/drm/i915/display/icl_dsi_regs.h
+2
-1
drivers/gpu/drm/i915/display/icl_dsi_regs.h
···
227
227
#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
228
228
#define CLK_HS_OR_LP (0x2 << 8)
229
229
#define CLK_HS_CONTINUOUS (0x3 << 8)
230
+
#define LP_CLK_DURING_LPM (1 << 7) /* tgl+ */
230
231
#define LINK_CALIBRATION_MASK (0x3 << 4)
231
232
#define LINK_CALIBRATION_SHIFT 4
232
233
#define CALIBRATION_DISABLED (0x0 << 4)
233
234
#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
234
235
#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
235
-
#define BLANKING_PACKET_ENABLE (1 << 2)
236
+
#define BLANKING_PACKET_ENABLE (1 << 2) /* tgl+ */
236
237
#define S3D_ORIENTATION_LANDSCAPE (1 << 1)
237
238
#define EOTP_DISABLED (1 << 0)
238
239
+6
-4
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+6
-4
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
2180
2180
return 0;
2181
2181
}
2182
2182
2183
-
static int readout_enabled_lane_count(struct intel_encoder *encoder)
2183
+
int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1)
2184
2184
{
2185
2185
struct intel_display *display = to_intel_display(encoder);
2186
2186
u8 enabled_tx_lane_count = 0;
···
2212
2212
max_tx_lane_count = round_up(max_tx_lane_count, 2);
2213
2213
2214
2214
for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) {
2215
-
u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
2215
+
u8 phy_lane_mask = tx_lane < 2 ? lane0 : lane1;
2216
2216
int tx = tx_lane % 2 + 1;
2217
2217
u8 val;
2218
2218
···
2252
2252
*/
2253
2253
intel_c10_msgbus_access_begin(encoder, lane);
2254
2254
2255
-
cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
2255
+
cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,
2256
+
INTEL_CX0_LANE1);
2256
2257
2257
2258
for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
2258
2259
pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
···
2708
2707
2709
2708
wakeref = intel_cx0_phy_transaction_begin(encoder);
2710
2709
2711
-
cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
2710
+
cx0pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_CX0_LANE0,
2711
+
INTEL_CX0_LANE1);
2712
2712
2713
2713
/* 1. Read VDR params and current context selection */
2714
2714
intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
+1
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+1
drivers/gpu/drm/i915/display/intel_cx0_phy.h
···
28
28
void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
29
29
int lane);
30
30
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
31
+
int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1);
31
32
void intel_mtl_pll_enable(struct intel_encoder *encoder,
32
33
struct intel_dpll *pll,
33
34
const struct intel_dpll_hw_state *dpll_hw_state);
+7
-19
drivers/gpu/drm/i915/display/intel_ddi.c
+7
-19
drivers/gpu/drm/i915/display/intel_ddi.c
···
4243
4243
&crtc_state->dpll_hw_state);
4244
4244
}
4245
4245
4246
-
static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
4247
-
struct intel_crtc_state *crtc_state)
4248
-
{
4249
-
struct intel_display *display = to_intel_display(encoder);
4250
-
4251
-
intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll);
4252
-
4253
-
if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
4254
-
crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
4255
-
else
4256
-
crtc_state->port_clock =
4257
-
intel_lt_phy_calc_port_clock(display, &crtc_state->dpll_hw_state.ltpll);
4258
-
intel_ddi_get_config(encoder, crtc_state);
4259
-
}
4260
-
4261
4246
static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
4262
4247
{
4263
4248
return pll->info->id == DPLL_ID_ICL_TBTPLL;
···
5283
5298
encoder->pipe_mask = ~0;
5284
5299
5285
5300
if (HAS_LT_PHY(display)) {
5286
-
encoder->enable_clock = intel_xe3plpd_pll_enable;
5287
-
encoder->disable_clock = intel_xe3plpd_pll_disable;
5288
-
encoder->port_pll_type = intel_mtl_port_pll_type;
5289
-
encoder->get_config = xe3plpd_ddi_get_config;
5301
+
encoder->enable_clock = intel_mtl_pll_enable_clock;
5302
+
encoder->disable_clock = intel_mtl_pll_disable_clock;
5303
+
encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5304
+
if (intel_encoder_is_tc(encoder))
5305
+
encoder->get_config = mtl_ddi_tc_phy_get_config;
5306
+
else
5307
+
encoder->get_config = mtl_ddi_non_tc_phy_get_config;
5290
5308
} else if (DISPLAY_VER(display) >= 14) {
5291
5309
encoder->enable_clock = intel_mtl_pll_enable_clock;
5292
5310
encoder->disable_clock = intel_mtl_pll_disable_clock;
+178
drivers/gpu/drm/i915/display/intel_de.c
+178
drivers/gpu/drm/i915/display/intel_de.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright © 2026 Intel Corporation
4
+
*/
5
+
6
+
#include <linux/delay.h>
7
+
8
+
#include <drm/drm_print.h>
9
+
10
+
#include "intel_de.h"
11
+
12
+
static int __intel_de_wait_for_register(struct intel_display *display,
13
+
i915_reg_t reg, u32 mask, u32 value,
14
+
unsigned int timeout_us,
15
+
u32 (*read)(struct intel_display *display, i915_reg_t reg),
16
+
u32 *out_val, bool is_atomic)
17
+
{
18
+
const ktime_t end = ktime_add_us(ktime_get_raw(), timeout_us);
19
+
int wait_max = 1000;
20
+
int wait = 10;
21
+
u32 reg_value;
22
+
int ret;
23
+
24
+
might_sleep_if(!is_atomic);
25
+
26
+
if (timeout_us <= 10) {
27
+
is_atomic = true;
28
+
wait = 1;
29
+
}
30
+
31
+
for (;;) {
32
+
bool expired = ktime_after(ktime_get_raw(), end);
33
+
34
+
/* guarantee the condition is evaluated after timeout expired */
35
+
barrier();
36
+
37
+
reg_value = read(display, reg);
38
+
if ((reg_value & mask) == value) {
39
+
ret = 0;
40
+
break;
41
+
}
42
+
43
+
if (expired) {
44
+
ret = -ETIMEDOUT;
45
+
break;
46
+
}
47
+
48
+
if (is_atomic)
49
+
udelay(wait);
50
+
else
51
+
usleep_range(wait, wait << 1);
52
+
53
+
if (wait < wait_max)
54
+
wait <<= 1;
55
+
}
56
+
57
+
if (out_val)
58
+
*out_val = reg_value;
59
+
60
+
return ret;
61
+
}
62
+
63
+
static int intel_de_wait_for_register(struct intel_display *display,
64
+
i915_reg_t reg, u32 mask, u32 value,
65
+
unsigned int fast_timeout_us,
66
+
unsigned int slow_timeout_us,
67
+
u32 (*read)(struct intel_display *display, i915_reg_t reg),
68
+
u32 *out_value, bool is_atomic)
69
+
{
70
+
int ret = -EINVAL;
71
+
72
+
if (fast_timeout_us)
73
+
ret = __intel_de_wait_for_register(display, reg, mask, value,
74
+
fast_timeout_us, read,
75
+
out_value, is_atomic);
76
+
77
+
if (ret && slow_timeout_us)
78
+
ret = __intel_de_wait_for_register(display, reg, mask, value,
79
+
slow_timeout_us, read,
80
+
out_value, is_atomic);
81
+
82
+
return ret;
83
+
}
84
+
85
+
int intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
86
+
u32 mask, u32 value, unsigned int timeout_us,
87
+
u32 *out_value)
88
+
{
89
+
int ret;
90
+
91
+
intel_dmc_wl_get(display, reg);
92
+
93
+
ret = intel_de_wait_for_register(display, reg, mask, value,
94
+
timeout_us, 0,
95
+
intel_de_read,
96
+
out_value, false);
97
+
98
+
intel_dmc_wl_put(display, reg);
99
+
100
+
return ret;
101
+
}
102
+
103
+
int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
104
+
u32 mask, u32 value, unsigned int timeout_ms,
105
+
u32 *out_value)
106
+
{
107
+
int ret;
108
+
109
+
intel_dmc_wl_get(display, reg);
110
+
111
+
ret = intel_de_wait_for_register(display, reg, mask, value,
112
+
2, timeout_ms * 1000,
113
+
intel_de_read,
114
+
out_value, false);
115
+
116
+
intel_dmc_wl_put(display, reg);
117
+
118
+
return ret;
119
+
}
120
+
121
+
int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
122
+
u32 mask, u32 value, unsigned int timeout_ms,
123
+
u32 *out_value)
124
+
{
125
+
return intel_de_wait_for_register(display, reg, mask, value,
126
+
2, timeout_ms * 1000,
127
+
intel_de_read_fw,
128
+
out_value, false);
129
+
}
130
+
131
+
int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
132
+
u32 mask, u32 value, unsigned int timeout_us,
133
+
u32 *out_value)
134
+
{
135
+
return intel_de_wait_for_register(display, reg, mask, value,
136
+
timeout_us, 0,
137
+
intel_de_read_fw,
138
+
out_value, true);
139
+
}
140
+
141
+
int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
142
+
u32 mask, unsigned int timeout_us)
143
+
{
144
+
return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
145
+
}
146
+
147
+
int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
148
+
u32 mask, unsigned int timeout_us)
149
+
{
150
+
return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);
151
+
}
152
+
153
+
int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
154
+
u32 mask, unsigned int timeout_ms)
155
+
{
156
+
return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);
157
+
}
158
+
159
+
int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
160
+
u32 mask, unsigned int timeout_ms)
161
+
{
162
+
return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
163
+
}
164
+
165
+
u8 intel_de_read8(struct intel_display *display, i915_reg_t reg)
166
+
{
167
+
/* this is only used on VGA registers (possible on pre-g4x) */
168
+
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
169
+
170
+
return intel_uncore_read8(__to_uncore(display), reg);
171
+
}
172
+
173
+
void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val)
174
+
{
175
+
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
176
+
177
+
intel_uncore_write8(__to_uncore(display), reg, val);
178
+
}
+23
-98
drivers/gpu/drm/i915/display/intel_de.h
+23
-98
drivers/gpu/drm/i915/display/intel_de.h
···
6
6
#ifndef __INTEL_DE_H__
7
7
#define __INTEL_DE_H__
8
8
9
-
#include <drm/drm_print.h>
10
-
11
9
#include "intel_display_core.h"
12
10
#include "intel_dmc_wl.h"
13
11
#include "intel_dsb.h"
···
16
18
{
17
19
return to_intel_uncore(display->drm);
18
20
}
21
+
22
+
u8 intel_de_read8(struct intel_display *display, i915_reg_t reg);
23
+
void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val);
19
24
20
25
static inline u32
21
26
intel_de_read(struct intel_display *display, i915_reg_t reg)
···
32
31
intel_dmc_wl_put(display, reg);
33
32
34
33
return val;
35
-
}
36
-
37
-
static inline u8
38
-
intel_de_read8(struct intel_display *display, i915_reg_t reg)
39
-
{
40
-
/* this is only used on VGA registers (possible on pre-g4x) */
41
-
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
42
-
43
-
return intel_uncore_read8(__to_uncore(display), reg);
44
-
}
45
-
46
-
static inline void
47
-
intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val)
48
-
{
49
-
drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x);
50
-
51
-
intel_uncore_write8(__to_uncore(display), reg, val);
52
34
}
53
35
54
36
static inline u64
···
86
102
return val;
87
103
}
88
104
89
-
static inline int
90
-
intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
91
-
u32 mask, u32 value, unsigned int timeout_us,
92
-
u32 *out_value)
93
-
{
94
-
int ret;
95
-
96
-
intel_dmc_wl_get(display, reg);
97
-
98
-
ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
99
-
value, timeout_us, 0, out_value);
100
-
101
-
intel_dmc_wl_put(display, reg);
102
-
103
-
return ret;
104
-
}
105
-
106
-
static inline int
107
-
intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
108
-
u32 mask, u32 value, unsigned int timeout_ms,
109
-
u32 *out_value)
110
-
{
111
-
int ret;
112
-
113
-
intel_dmc_wl_get(display, reg);
114
-
115
-
ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
116
-
value, 2, timeout_ms, out_value);
117
-
118
-
intel_dmc_wl_put(display, reg);
119
-
120
-
return ret;
121
-
}
122
-
123
-
static inline int
124
-
intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
125
-
u32 mask, u32 value, unsigned int timeout_ms,
126
-
u32 *out_value)
127
-
{
128
-
return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
129
-
value, 2, timeout_ms, out_value);
130
-
}
131
-
132
-
static inline int
133
-
intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
134
-
u32 mask, u32 value, unsigned int timeout_us,
135
-
u32 *out_value)
136
-
{
137
-
return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
138
-
value, timeout_us, 0, out_value);
139
-
}
140
-
141
-
static inline int
142
-
intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
143
-
u32 mask, unsigned int timeout_us)
144
-
{
145
-
return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
146
-
}
147
-
148
-
static inline int
149
-
intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
150
-
u32 mask, unsigned int timeout_us)
151
-
{
152
-
return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);
153
-
}
154
-
155
-
static inline int
156
-
intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
157
-
u32 mask, unsigned int timeout_ms)
158
-
{
159
-
return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);
160
-
}
161
-
162
-
static inline int
163
-
intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
164
-
u32 mask, unsigned int timeout_ms)
165
-
{
166
-
return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
167
-
}
105
+
int intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
106
+
u32 mask, u32 value, unsigned int timeout_us,
107
+
u32 *out_value);
108
+
int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
109
+
u32 mask, u32 value, unsigned int timeout_ms,
110
+
u32 *out_value);
111
+
int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
112
+
u32 mask, u32 value, unsigned int timeout_ms,
113
+
u32 *out_value);
114
+
int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
115
+
u32 mask, u32 value, unsigned int timeout_us,
116
+
u32 *out_value);
117
+
int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
118
+
u32 mask, unsigned int timeout_us);
119
+
int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
120
+
u32 mask, unsigned int timeout_us);
121
+
int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
122
+
u32 mask, unsigned int timeout_ms);
123
+
int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
124
+
u32 mask, unsigned int timeout_ms);
168
125
169
126
/*
170
127
* Unlocked mmio-accessors, think carefully before using these.
+2
-33
drivers/gpu/drm/i915/display/intel_display.c
+2
-33
drivers/gpu/drm/i915/display/intel_display.c
···
5063
5063
!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
5064
5064
}
5065
5065
5066
-
static void
5067
-
pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
5068
-
const struct intel_crtc *crtc,
5069
-
const char *name,
5070
-
const struct intel_lt_phy_pll_state *a,
5071
-
const struct intel_lt_phy_pll_state *b)
5072
-
{
5073
-
struct intel_display *display = to_intel_display(crtc);
5074
-
char *chipname = "LTPHY";
5075
-
5076
-
pipe_config_mismatch(p, fastset, crtc, name, chipname);
5077
-
5078
-
drm_printf(p, "expected:\n");
5079
-
intel_lt_phy_dump_hw_state(display, a);
5080
-
drm_printf(p, "found:\n");
5081
-
intel_lt_phy_dump_hw_state(display, b);
5082
-
}
5083
-
5084
5066
bool
5085
5067
intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5086
5068
const struct intel_crtc_state *pipe_config,
···
5173
5191
pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5174
5192
¤t_config->name, \
5175
5193
&pipe_config->name); \
5176
-
ret = false; \
5177
-
} \
5178
-
} while (0)
5179
-
5180
-
#define PIPE_CONF_CHECK_PLL_LT(name) do { \
5181
-
if (!intel_lt_phy_pll_compare_hw_state(¤t_config->name, \
5182
-
&pipe_config->name)) { \
5183
-
pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5184
-
¤t_config->name, \
5185
-
&pipe_config->name); \
5186
5194
ret = false; \
5187
5195
} \
5188
5196
} while (0)
···
5402
5430
/* FIXME convert everything over the dpll_mgr */
5403
5431
if (display->dpll.mgr || HAS_GMCH(display))
5404
5432
PIPE_CONF_CHECK_PLL(dpll_hw_state);
5405
-
5406
-
/* FIXME convert MTL+ platforms over to dpll_mgr */
5407
-
if (HAS_LT_PHY(display))
5408
-
PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
5409
5433
5410
5434
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5411
5435
PIPE_CONF_CHECK_X(dsi_pll.div);
···
7864
7896
7865
7897
bool assert_port_valid(struct intel_display *display, enum port port)
7866
7898
{
7867
-
return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
7899
+
return !drm_WARN(display->drm,
7900
+
!(port >= 0 && DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
7868
7901
"Platform does not support port %c\n", port_name(port));
7869
7902
}
7870
7903
+25
-3
drivers/gpu/drm/i915/display/intel_display_device.c
+25
-3
drivers/gpu/drm/i915/display/intel_display_device.c
···
1654
1654
bitmap_or(dst->bitmap, dst->bitmap, src->bitmap, display_platforms_num_bits());
1655
1655
}
1656
1656
1657
+
#define __STEP_NAME(name) [STEP_##name] = #name,
1658
+
1659
+
static void initialize_step(struct intel_display *display, enum intel_step step)
1660
+
{
1661
+
static const char step_names[][3] = {
1662
+
STEP_NAME_LIST(__STEP_NAME)
1663
+
};
1664
+
1665
+
DISPLAY_RUNTIME_INFO(display)->step = step;
1666
+
1667
+
/* Step name will remain an empty string if not applicable */
1668
+
if (step >= 0 && step < ARRAY_SIZE(step_names))
1669
+
strscpy(DISPLAY_RUNTIME_INFO(display)->step_name, step_names[step]);
1670
+
}
1671
+
1672
+
#undef __STEP_NAME
1673
+
1674
+
static const char *step_name(const struct intel_display_runtime_info *runtime)
1675
+
{
1676
+
return strlen(runtime->step_name) ? runtime->step_name : "N/A";
1677
+
}
1678
+
1657
1679
struct intel_display *intel_display_device_probe(struct pci_dev *pdev,
1658
1680
const struct intel_display_parent_interface *parent)
1659
1681
{
···
1753
1731
subdesc ? &subdesc->step_info : NULL);
1754
1732
}
1755
1733
1756
-
DISPLAY_RUNTIME_INFO(display)->step = step;
1734
+
initialize_step(display, step);
1757
1735
1758
1736
drm_info(display->drm, "Found %s%s%s (device ID %04x) %s display version %u.%02u stepping %s\n",
1759
1737
desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "",
1760
1738
pdev->device, display->platform.dgfx ? "discrete" : "integrated",
1761
1739
DISPLAY_RUNTIME_INFO(display)->ip.ver,
1762
1740
DISPLAY_RUNTIME_INFO(display)->ip.rel,
1763
-
step != STEP_NONE ? intel_step_name(step) : "N/A");
1741
+
step_name(DISPLAY_RUNTIME_INFO(display)));
1764
1742
1765
1743
return display;
1766
1744
···
1976
1954
drm_printf(p, "display version: %u\n",
1977
1955
runtime->ip.ver);
1978
1956
1979
-
drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step));
1957
+
drm_printf(p, "display stepping: %s\n", step_name(runtime));
1980
1958
1981
1959
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
1982
1960
DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
+1
drivers/gpu/drm/i915/display/intel_display_device.h
+1
drivers/gpu/drm/i915/display/intel_display_device.h
+1
-2
drivers/gpu/drm/i915/display/intel_display_types.h
+1
-2
drivers/gpu/drm/i915/display/intel_display_types.h
···
835
835
836
836
struct skl_wm_level {
837
837
u16 min_ddb_alloc;
838
+
u16 min_ddb_alloc_uv; /* for pre-icl */
838
839
u16 blocks;
839
840
u8 lines;
840
841
bool enable;
···
846
845
847
846
struct skl_plane_wm {
848
847
struct skl_wm_level wm[8];
849
-
struct skl_wm_level uv_wm[8];
850
848
struct skl_wm_level trans_wm;
851
849
struct {
852
850
struct skl_wm_level wm0;
853
851
struct skl_wm_level trans_wm;
854
852
} sagv;
855
-
bool is_planar;
856
853
};
857
854
858
855
struct skl_pipe_wm {
+8
-11
drivers/gpu/drm/i915/display/intel_dmc.c
+8
-11
drivers/gpu/drm/i915/display/intel_dmc.c
···
39
39
#include "intel_dmc.h"
40
40
#include "intel_dmc_regs.h"
41
41
#include "intel_flipq.h"
42
-
#include "intel_step.h"
43
42
44
43
/**
45
44
* DOC: DMC Firmware Support
···
417
418
return has_dmc_id_fw(display, DMC_FW_MAIN);
418
419
}
419
420
420
-
static const struct stepping_info *
421
-
intel_get_stepping_info(struct intel_display *display,
422
-
struct stepping_info *si)
421
+
static void initialize_stepping_info(struct intel_display *display, struct stepping_info *si)
423
422
{
424
-
const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display));
423
+
const char *step_name = DISPLAY_RUNTIME_INFO(display)->step_name;
425
424
426
-
si->stepping = step_name[0];
427
-
si->substepping = step_name[1];
428
-
return si;
425
+
si->stepping = step_name[0] ?: '*';
426
+
si->substepping = step_name[1] ?: '*';
429
427
}
430
428
431
429
static void gen9_set_dc_state_debugmask(struct intel_display *display)
···
1270
1274
struct intel_css_header *css_header;
1271
1275
struct intel_package_header *package_header;
1272
1276
struct intel_dmc_header_base *dmc_header;
1273
-
struct stepping_info display_info = { '*', '*'};
1274
-
const struct stepping_info *si = intel_get_stepping_info(display, &display_info);
1277
+
struct stepping_info si = {};
1275
1278
enum intel_dmc_id dmc_id;
1276
1279
u32 readcount = 0;
1277
1280
u32 r, offset;
1278
1281
1279
1282
if (!fw)
1280
1283
return -EINVAL;
1284
+
1285
+
initialize_stepping_info(display, &si);
1281
1286
1282
1287
/* Extract CSS Header information */
1283
1288
css_header = (struct intel_css_header *)fw->data;
···
1290
1293
1291
1294
/* Extract Package Header information */
1292
1295
package_header = (struct intel_package_header *)&fw->data[readcount];
1293
-
r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
1296
+
r = parse_dmc_fw_package(dmc, package_header, &si, fw->size - readcount);
1294
1297
if (!r)
1295
1298
return -EINVAL;
1296
1299
+31
-1
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+31
-1
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
···
610
610
}
611
611
612
612
static bool
613
+
check_if_vesa_backlight_possible(struct intel_dp *intel_dp)
614
+
{
615
+
int ret;
616
+
u8 bit_min, bit_max;
617
+
618
+
if (!(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP))
619
+
return true;
620
+
621
+
ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &bit_min);
622
+
if (ret < 0)
623
+
return false;
624
+
625
+
bit_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
626
+
if (bit_min < 1)
627
+
return false;
628
+
629
+
ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &bit_max);
630
+
if (ret < 0)
631
+
return false;
632
+
633
+
bit_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
634
+
if (bit_max < bit_min)
635
+
return false;
636
+
637
+
return true;
638
+
}
639
+
640
+
static bool
613
641
intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
614
642
{
615
643
struct intel_display *display = to_intel_display(connector);
···
653
625
return true;
654
626
}
655
627
656
-
if (drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
628
+
if (drm_edp_backlight_supported(intel_dp->edp_dpcd) &&
629
+
check_if_vesa_backlight_possible(intel_dp)) {
657
630
drm_dbg_kms(display->drm,
658
631
"[CONNECTOR:%d:%s] AUX Backlight Control Supported!\n",
659
632
connector->base.base.id, connector->base.name);
660
633
return true;
661
634
}
635
+
662
636
return false;
663
637
}
664
638
+2
-24
drivers/gpu/drm/i915/display/intel_dpll.c
+2
-24
drivers/gpu/drm/i915/display/intel_dpll.c
···
1212
1212
return 0;
1213
1213
}
1214
1214
1215
-
static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
1216
-
struct intel_crtc *crtc)
1217
-
{
1218
-
struct intel_crtc_state *crtc_state =
1219
-
intel_atomic_get_new_crtc_state(state, crtc);
1220
-
struct intel_encoder *encoder =
1221
-
intel_get_crtc_new_encoder(state, crtc_state);
1222
-
struct intel_display *display = to_intel_display(encoder);
1223
-
int ret;
1224
-
1225
-
ret = intel_lt_phy_pll_calc_state(crtc_state, encoder);
1226
-
if (ret)
1227
-
return ret;
1228
-
1229
-
/* TODO: Do the readback via intel_compute_shared_dplls() */
1230
-
crtc_state->port_clock =
1231
-
intel_lt_phy_calc_port_clock(display, &crtc_state->dpll_hw_state.ltpll);
1232
-
1233
-
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1234
-
1235
-
return 0;
1236
-
}
1237
-
1238
1215
static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
1239
1216
{
1240
1217
struct intel_display *display = to_intel_display(crtc_state);
···
1672
1695
}
1673
1696
1674
1697
static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
1675
-
.crtc_compute_clock = xe3plpd_crtc_compute_clock,
1698
+
.crtc_compute_clock = hsw_crtc_compute_clock,
1699
+
.crtc_get_dpll = hsw_crtc_get_dpll,
1676
1700
};
1677
1701
1678
1702
static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
+181
-5
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+181
-5
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
4571
4571
.compare_hw_state = mtl_compare_hw_state,
4572
4572
};
4573
4573
4574
+
static bool xe3plpd_pll_get_hw_state(struct intel_display *display,
4575
+
struct intel_dpll *pll,
4576
+
struct intel_dpll_hw_state *dpll_hw_state)
4577
+
{
4578
+
struct intel_encoder *encoder = get_intel_encoder(display, pll);
4579
+
4580
+
if (!encoder)
4581
+
return false;
4582
+
4583
+
return intel_lt_phy_pll_readout_hw_state(encoder, &dpll_hw_state->ltpll);
4584
+
}
4585
+
4586
+
static int xe3plpd_pll_get_freq(struct intel_display *display,
4587
+
const struct intel_dpll *pll,
4588
+
const struct intel_dpll_hw_state *dpll_hw_state)
4589
+
{
4590
+
struct intel_encoder *encoder = get_intel_encoder(display, pll);
4591
+
4592
+
if (drm_WARN_ON(display->drm, !encoder))
4593
+
return -EINVAL;
4594
+
4595
+
return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
4596
+
}
4597
+
4598
+
static void xe3plpd_pll_enable(struct intel_display *display,
4599
+
struct intel_dpll *pll,
4600
+
const struct intel_dpll_hw_state *dpll_hw_state)
4601
+
{
4602
+
struct intel_encoder *encoder = get_intel_encoder(display, pll);
4603
+
4604
+
if (drm_WARN_ON(display->drm, !encoder))
4605
+
return;
4606
+
4607
+
intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state);
4608
+
}
4609
+
4610
+
static void xe3plpd_pll_disable(struct intel_display *display,
4611
+
struct intel_dpll *pll)
4612
+
{
4613
+
struct intel_encoder *encoder = get_intel_encoder(display, pll);
4614
+
4615
+
if (drm_WARN_ON(display->drm, !encoder))
4616
+
return;
4617
+
4618
+
intel_xe3plpd_pll_disable(encoder);
4619
+
}
4620
+
4621
+
static const struct intel_dpll_funcs xe3plpd_tbt_pll_funcs = {
4622
+
.enable = mtl_tbt_pll_enable,
4623
+
.disable = mtl_tbt_pll_disable,
4624
+
.get_hw_state = intel_lt_phy_tbt_pll_readout_hw_state,
4625
+
.get_freq = mtl_tbt_pll_get_freq,
4626
+
};
4627
+
4628
+
static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
4629
+
.enable = xe3plpd_pll_enable,
4630
+
.disable = xe3plpd_pll_disable,
4631
+
.get_hw_state = xe3plpd_pll_get_hw_state,
4632
+
.get_freq = xe3plpd_pll_get_freq,
4633
+
};
4634
+
4635
+
static const struct dpll_info xe3plpd_plls[] = {
4636
+
{ .name = "DPLL 0", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4637
+
{ .name = "DPLL 1", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4638
+
{ .name = "TBT PLL", .funcs = &xe3plpd_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4639
+
.is_alt_port_dpll = true, .always_on = true },
4640
+
{ .name = "TC PLL 1", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4641
+
{ .name = "TC PLL 2", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4642
+
{ .name = "TC PLL 3", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4643
+
{ .name = "TC PLL 4", .funcs = &xe3plpd_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4644
+
{}
4645
+
};
4646
+
4647
+
static int xe3plpd_compute_non_tc_phy_dpll(struct intel_atomic_state *state,
4648
+
struct intel_crtc *crtc,
4649
+
struct intel_encoder *encoder)
4650
+
{
4651
+
struct intel_display *display = to_intel_display(encoder);
4652
+
struct intel_crtc_state *crtc_state =
4653
+
intel_atomic_get_new_crtc_state(state, crtc);
4654
+
struct icl_port_dpll *port_dpll =
4655
+
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
4656
+
int ret;
4657
+
4658
+
ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
4659
+
if (ret)
4660
+
return ret;
4661
+
4662
+
/* this is mainly for the fastset check */
4663
+
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
4664
+
4665
+
crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, &port_dpll->hw_state.ltpll);
4666
+
4667
+
return 0;
4668
+
}
4669
+
4670
+
static int xe3plpd_compute_tc_phy_dplls(struct intel_atomic_state *state,
4671
+
struct intel_crtc *crtc,
4672
+
struct intel_encoder *encoder)
4673
+
{
4674
+
struct intel_display *display = to_intel_display(encoder);
4675
+
struct intel_crtc_state *crtc_state =
4676
+
intel_atomic_get_new_crtc_state(state, crtc);
4677
+
const struct intel_crtc_state *old_crtc_state =
4678
+
intel_atomic_get_old_crtc_state(state, crtc);
4679
+
struct icl_port_dpll *port_dpll;
4680
+
int ret;
4681
+
4682
+
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
4683
+
intel_lt_phy_tbt_pll_calc_state(&port_dpll->hw_state);
4684
+
4685
+
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
4686
+
ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
4687
+
if (ret)
4688
+
return ret;
4689
+
4690
+
/* this is mainly for the fastset check */
4691
+
if (old_crtc_state->intel_dpll &&
4692
+
old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
4693
+
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
4694
+
else
4695
+
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
4696
+
4697
+
crtc_state->port_clock = intel_lt_phy_calc_port_clock(display, &port_dpll->hw_state.ltpll);
4698
+
4699
+
return 0;
4700
+
}
4701
+
4702
+
static int xe3plpd_compute_dplls(struct intel_atomic_state *state,
4703
+
struct intel_crtc *crtc,
4704
+
struct intel_encoder *encoder)
4705
+
{
4706
+
if (intel_encoder_is_tc(encoder))
4707
+
return xe3plpd_compute_tc_phy_dplls(state, crtc, encoder);
4708
+
else
4709
+
return xe3plpd_compute_non_tc_phy_dpll(state, crtc, encoder);
4710
+
}
4711
+
4712
+
static void xe3plpd_dump_hw_state(struct drm_printer *p,
4713
+
const struct intel_dpll_hw_state *dpll_hw_state)
4714
+
{
4715
+
intel_lt_phy_dump_hw_state(p, &dpll_hw_state->ltpll);
4716
+
}
4717
+
4718
+
static bool xe3plpd_compare_hw_state(const struct intel_dpll_hw_state *_a,
4719
+
const struct intel_dpll_hw_state *_b)
4720
+
{
4721
+
const struct intel_lt_phy_pll_state *a = &_a->ltpll;
4722
+
const struct intel_lt_phy_pll_state *b = &_b->ltpll;
4723
+
4724
+
return intel_lt_phy_pll_compare_hw_state(a, b);
4725
+
}
4726
+
4727
+
static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
4728
+
.dpll_info = xe3plpd_plls,
4729
+
.compute_dplls = xe3plpd_compute_dplls,
4730
+
.get_dplls = mtl_get_dplls,
4731
+
.put_dplls = icl_put_dplls,
4732
+
.update_active_dpll = icl_update_active_dpll,
4733
+
.update_ref_clks = icl_update_dpll_ref_clks,
4734
+
.dump_hw_state = xe3plpd_dump_hw_state,
4735
+
.compare_hw_state = xe3plpd_compare_hw_state,
4736
+
};
4737
+
4574
4738
/**
4575
4739
* intel_dpll_init - Initialize DPLLs
4576
4740
* @display: intel_display device
···
4749
4585
4750
4586
mutex_init(&display->dpll.lock);
4751
4587
4752
-
if (DISPLAY_VER(display) >= 35 || display->platform.dg2)
4753
-
/* No shared DPLLs on NVL or DG2; port PLLs are part of the PHY */
4588
+
if (display->platform.dg2)
4589
+
/* No shared DPLLs on DG2; port PLLs are part of the PHY */
4754
4590
dpll_mgr = NULL;
4591
+
else if (DISPLAY_VER(display) >= 35)
4592
+
dpll_mgr = &xe3plpd_pll_mgr;
4755
4593
else if (DISPLAY_VER(display) >= 14)
4756
4594
dpll_mgr = &mtl_pll_mgr;
4757
4595
else if (display->platform.alderlake_p)
···
5076
4910
const struct intel_crtc_state *new_crtc_state)
5077
4911
{
5078
4912
struct intel_dpll_hw_state dpll_hw_state = {};
4913
+
bool pll_mismatch = false;
5079
4914
u8 pipe_mask;
5080
4915
bool active;
5081
4916
···
5118
4951
"%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
5119
4952
pll->info->name, pipe_mask, pll->state.pipe_mask);
5120
4953
5121
-
if (INTEL_DISPLAY_STATE_WARN(display,
5122
-
pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
5123
-
sizeof(dpll_hw_state)),
4954
+
if (pll->on) {
4955
+
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
4956
+
4957
+
if (HAS_LT_PHY(display))
4958
+
pll_mismatch = !dpll_mgr->compare_hw_state(&pll->state.hw_state,
4959
+
&dpll_hw_state);
4960
+
else
4961
+
pll_mismatch = memcmp(&pll->state.hw_state, &dpll_hw_state,
4962
+
sizeof(dpll_hw_state));
4963
+
}
4964
+
4965
+
if (INTEL_DISPLAY_STATE_WARN(display, pll_mismatch,
5124
4966
"%s: pll hw state mismatch\n",
5125
4967
pll->info->name)) {
5126
4968
struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
+1
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+1
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+4
-3
drivers/gpu/drm/i915/display/intel_dsi.h
+4
-3
drivers/gpu/drm/i915/display/intel_dsi.h
···
80
80
/* NON_BURST_SYNC_PULSE, NON_BURST_SYNC_EVENTS, or BURST_MODE */
81
81
int video_mode;
82
82
83
-
/* eot for MIPI_EOT_DISABLE register */
84
-
u8 eotp_pkt;
85
-
u8 clock_stop;
83
+
bool lp_clock_during_lpm;
84
+
bool blanking_pkt;
85
+
bool eot_pkt;
86
+
bool clock_stop;
86
87
87
88
u8 escape_clk_div;
88
89
u8 dual_link;
+8
-4
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+8
-4
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
···
718
718
"burst" : "<unknown>");
719
719
drm_printf(&p, "Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
720
720
drm_printf(&p, "Reset timer %d\n", intel_dsi->rst_timer_val);
721
-
drm_printf(&p, "Eot %s\n", str_enabled_disabled(intel_dsi->eotp_pkt));
722
-
drm_printf(&p, "Clockstop %s\n", str_enabled_disabled(!intel_dsi->clock_stop));
721
+
drm_printf(&p, "LP clock during LPM %s\n", str_enabled_disabled(intel_dsi->lp_clock_during_lpm));
722
+
drm_printf(&p, "Blanking packets during BLLP %s\n", str_enabled_disabled(intel_dsi->blanking_pkt));
723
+
drm_printf(&p, "EoT packet %s\n", str_enabled_disabled(intel_dsi->eot_pkt));
724
+
drm_printf(&p, "Clock stop during BLLP %s\n", str_enabled_disabled(intel_dsi->clock_stop));
723
725
drm_printf(&p, "Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
724
726
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
725
727
drm_printf(&p, "Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
···
772
770
773
771
drm_dbg_kms(display->drm, "\n");
774
772
775
-
intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
776
-
intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
773
+
intel_dsi->lp_clock_during_lpm = mipi_config->lp_clock_during_lpm;
774
+
intel_dsi->blanking_pkt = mipi_config->blanking_packets_during_bllp;
775
+
intel_dsi->eot_pkt = !mipi_config->eot_pkt_disabled;
776
+
intel_dsi->clock_stop = mipi_config->enable_clk_stop;
777
777
intel_dsi->lane_count = mipi_config->lane_cnt + 1;
778
778
intel_dsi->pixel_format =
779
779
vbt_to_dsi_pixel_format(mipi_config->videomode_color_format);
+1
-1
drivers/gpu/drm/i915/display/intel_gmbus.c
+1
-1
drivers/gpu/drm/i915/display/intel_gmbus.c
···
694
694
goto clear_err;
695
695
}
696
696
697
-
/* Generate a STOP condition on the bus. Note that gmbus can't generata
697
+
/* Generate a STOP condition on the bus. Note that gmbus can't generate
698
698
* a STOP on the very first cycle. To simplify the code we
699
699
* unconditionally generate the STOP condition with an additional gmbus
700
700
* cycle. */
+107
-86
drivers/gpu/drm/i915/display/intel_lt_phy.c
+107
-86
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
11
11
#include "intel_ddi_buf_trans.h"
12
12
#include "intel_de.h"
13
13
#include "intel_display.h"
14
+
#include "intel_display_regs.h"
14
15
#include "intel_display_types.h"
15
16
#include "intel_display_utils.h"
16
17
#include "intel_dpll.h"
···
33
32
INTEL_LT_PHY_LANE0)
34
33
#define MODE_DP 3
35
34
#define MODE_HDMI_20 4
35
+
#define MODE_HDMI_FRL 5
36
36
#define Q32_TO_INT(x) ((x) >> 32)
37
37
#define Q32_TO_FRAC(x) ((x) & 0xFFFFFFFF)
38
38
#define DCO_MIN_FREQ_MHZ 11850
···
1178
1176
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
1179
1177
}
1180
1178
1179
+
static bool intel_lt_phy_is_hdmi(const struct intel_lt_phy_pll_state *ltpll)
1180
+
{
1181
+
u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, ltpll->config[0]);
1182
+
1183
+
if (mode == MODE_HDMI_20 || mode == MODE_HDMI_FRL)
1184
+
return true;
1185
+
1186
+
return false;
1187
+
}
1188
+
1189
+
static bool intel_lt_phy_is_dp(const struct intel_lt_phy_pll_state *ltpll)
1190
+
{
1191
+
u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, ltpll->config[0]);
1192
+
1193
+
if (mode == MODE_DP)
1194
+
return true;
1195
+
1196
+
return false;
1197
+
}
1198
+
1181
1199
static void
1182
1200
intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
1183
-
const struct intel_crtc_state *crtc_state,
1201
+
const struct intel_lt_phy_pll_state *ltpll,
1202
+
int port_clock,
1184
1203
bool lane_reversal)
1185
1204
{
1186
1205
struct intel_display *display = to_intel_display(encoder);
···
1218
1195
* but since the register bits still remain the same we use
1219
1196
* the same definition
1220
1197
*/
1221
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1222
-
intel_hdmi_is_frl(crtc_state->port_clock))
1198
+
if (intel_lt_phy_is_hdmi(ltpll) && intel_hdmi_is_frl(port_clock))
1223
1199
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
1224
1200
else
1225
1201
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
1226
1202
1227
1203
/* DP2.0 10G and 20G rates enable MPLLA*/
1228
-
if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
1204
+
if (port_clock == 1000000 || port_clock == 2000000)
1229
1205
val |= XELPDP_SSC_ENABLE_PLLA;
1230
1206
else
1231
-
val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
1207
+
val |= ltpll->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
1232
1208
1233
1209
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
1234
1210
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
···
1270
1248
1271
1249
static bool
1272
1250
intel_lt_phy_config_changed(struct intel_encoder *encoder,
1273
-
const struct intel_crtc_state *crtc_state)
1251
+
const struct intel_lt_phy_pll_state *ltpll,
1252
+
u32 port_clock)
1274
1253
{
1275
1254
u8 val, rate;
1276
1255
u32 clock;
···
1285
1262
* using 1.62 Gbps clock since PHY PLL defaults to that
1286
1263
* otherwise we always need to reconfigure it.
1287
1264
*/
1288
-
if (intel_crtc_has_dp_encoder(crtc_state)) {
1265
+
if (intel_lt_phy_is_dp(ltpll)) {
1289
1266
clock = intel_lt_phy_get_dp_clock(rate);
1290
-
if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock)
1267
+
if (port_clock == 1620000 && port_clock == clock)
1291
1268
return false;
1292
1269
}
1293
1270
···
1746
1723
1747
1724
int
1748
1725
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
1749
-
struct intel_encoder *encoder)
1726
+
struct intel_encoder *encoder,
1727
+
struct intel_dpll_hw_state *hw_state)
1750
1728
{
1751
1729
struct intel_display *display = to_intel_display(crtc_state);
1752
1730
const struct intel_lt_phy_pll_params *tables;
1753
1731
int i;
1732
+
1733
+
memset(hw_state, 0, sizeof(*hw_state));
1754
1734
1755
1735
tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
1756
1736
if (!tables)
···
1764
1738
1765
1739
drm_WARN_ON(display->drm, !intel_dpll_clock_matches(clock, tables[i].clock_rate));
1766
1740
if (intel_dpll_clock_matches(crtc_state->port_clock, clock)) {
1767
-
crtc_state->dpll_hw_state.ltpll = *tables[i].state;
1741
+
hw_state->ltpll = *tables[i].state;
1768
1742
if (intel_crtc_has_dp_encoder(crtc_state)) {
1769
1743
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1770
-
crtc_state->dpll_hw_state.ltpll.config[2] = 1;
1744
+
hw_state->ltpll.config[2] = 1;
1771
1745
}
1772
-
crtc_state->dpll_hw_state.ltpll.ssc_enabled =
1746
+
hw_state->ltpll.ssc_enabled =
1773
1747
intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
1748
+
hw_state->ltpll.lane_count = crtc_state->lane_count;
1774
1749
return 0;
1775
1750
}
1776
1751
}
1777
1752
1778
1753
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1779
-
return intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll,
1754
+
hw_state->ltpll.lane_count = crtc_state->lane_count;
1755
+
return intel_lt_phy_calculate_hdmi_state(&hw_state->ltpll,
1780
1756
crtc_state->port_clock);
1781
1757
}
1782
1758
1783
1759
return -EINVAL;
1784
1760
}
1785
1761
1762
+
void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state)
1763
+
{
1764
+
memset(hw_state, 0, sizeof(*hw_state));
1765
+
1766
+
hw_state->ltpll.tbt_mode = true;
1767
+
}
1768
+
1786
1769
static void
1787
1770
intel_lt_phy_program_pll(struct intel_encoder *encoder,
1788
-
const struct intel_crtc_state *crtc_state)
1771
+
const struct intel_lt_phy_pll_state *ltpll)
1789
1772
{
1790
1773
u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
1791
1774
int i, j, k;
1792
1775
1793
1776
intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG,
1794
-
crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED);
1777
+
ltpll->config[0], MB_WRITE_COMMITTED);
1795
1778
intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,
1796
-
crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED);
1779
+
ltpll->config[1], MB_WRITE_COMMITTED);
1797
1780
intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG,
1798
-
crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED);
1781
+
ltpll->config[2], MB_WRITE_COMMITTED);
1799
1782
1800
1783
for (i = 0; i <= 12; i++) {
1801
1784
intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),
1802
-
crtc_state->dpll_hw_state.ltpll.addr_msb[i],
1785
+
ltpll->addr_msb[i],
1803
1786
MB_WRITE_COMMITTED);
1804
1787
intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),
1805
-
crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
1788
+
ltpll->addr_lsb[i],
1806
1789
MB_WRITE_COMMITTED);
1807
1790
1808
1791
for (j = 3, k = 0; j >= 0; j--, k++)
1809
1792
intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
1810
1793
LT_PHY_VDR_X_DATAY(i, j),
1811
-
crtc_state->dpll_hw_state.ltpll.data[i][k],
1794
+
ltpll->data[i][k],
1812
1795
MB_WRITE_COMMITTED);
1813
1796
}
1814
1797
}
1815
1798
1816
1799
static void
1817
1800
intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
1818
-
const struct intel_crtc_state *crtc_state)
1801
+
const struct intel_lt_phy_pll_state *ltpll)
1819
1802
{
1820
1803
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1821
1804
bool lane_reversal = dig_port->lane_reversal;
1822
-
u8 lane_count = crtc_state->lane_count;
1805
+
u8 lane_count = ltpll->lane_count;
1823
1806
bool is_dp_alt =
1824
1807
intel_tc_port_in_dp_alt_mode(dig_port);
1825
1808
enum intel_tc_pin_assignment tc_pin =
···
1909
1874
}
1910
1875
1911
1876
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
1912
-
const struct intel_crtc_state *crtc_state)
1877
+
struct intel_dpll *pll,
1878
+
const struct intel_dpll_hw_state *dpll_hw_state)
1913
1879
{
1914
1880
struct intel_display *display = to_intel_display(encoder);
1881
+
int port_clock = intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll);
1915
1882
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1916
1883
bool lane_reversal = dig_port->lane_reversal;
1917
1884
u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
···
1929
1892
wakeref = intel_lt_phy_transaction_begin(encoder);
1930
1893
1931
1894
/* 1. Enable MacCLK at default 162 MHz frequency. */
1932
-
intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
1895
+
intel_lt_phy_lane_reset(encoder, dpll_hw_state->ltpll.lane_count);
1933
1896
1934
1897
/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
1935
-
intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
1898
+
intel_lt_phy_program_port_clock_ctl(encoder, &dpll_hw_state->ltpll,
1899
+
port_clock, lane_reversal);
1936
1900
1937
1901
/* 3. Change owned PHY lanes power to Ready state. */
1938
1902
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
···
1943
1905
* 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
1944
1906
* encoded rate and encoded mode.
1945
1907
*/
1946
-
if (intel_lt_phy_config_changed(encoder, crtc_state)) {
1908
+
if (intel_lt_phy_config_changed(encoder, &dpll_hw_state->ltpll, port_clock)) {
1947
1909
/*
1948
1910
* 5. Program the PHY internal PLL registers over PHY message bus for the desired
1949
1911
* frequency and protocol type
1950
1912
*/
1951
-
intel_lt_phy_program_pll(encoder, crtc_state);
1913
+
intel_lt_phy_program_pll(encoder, &dpll_hw_state->ltpll);
1952
1914
1953
1915
/* 6. Use the P2P transaction flow */
1954
1916
/*
···
1980
1942
* Change. We handle this step in bxt_set_cdclk().
1981
1943
*/
1982
1944
/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
1983
-
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
1984
-
crtc_state->port_clock);
1945
+
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
1985
1946
1986
1947
/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
1987
1948
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
···
2027
1990
lane_phy_pulse_status,
2028
1991
lane_phy_pulse_status);
2029
1992
} else {
2030
-
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
1993
+
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
2031
1994
}
2032
1995
2033
1996
/*
···
2038
2001
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
2039
2002
XELPDP_P0_STATE_ACTIVE);
2040
2003
2041
-
intel_lt_phy_enable_disable_tx(encoder, crtc_state);
2004
+
intel_lt_phy_enable_disable_tx(encoder, &dpll_hw_state->ltpll);
2042
2005
intel_lt_phy_transaction_end(encoder, wakeref);
2043
2006
}
2044
2007
···
2173
2136
intel_lt_phy_transaction_end(encoder, wakeref);
2174
2137
}
2175
2138
2176
-
void intel_lt_phy_dump_hw_state(struct intel_display *display,
2139
+
void intel_lt_phy_dump_hw_state(struct drm_printer *p,
2177
2140
const struct intel_lt_phy_pll_state *hw_state)
2178
2141
{
2179
2142
int i, j;
2180
2143
2181
-
drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n");
2144
+
drm_printf(p, "lt_phy_pll_hw_state: lane count: %d, ssc enabled: %d, tbt mode: %d\n",
2145
+
hw_state->lane_count, hw_state->ssc_enabled, hw_state->tbt_mode);
2146
+
2182
2147
for (i = 0; i < 3; i++) {
2183
-
drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
2184
-
i, hw_state->config[i]);
2148
+
drm_printf(p, "config[%d] = 0x%.4x,\n",
2149
+
i, hw_state->config[i]);
2185
2150
}
2186
2151
2187
2152
for (i = 0; i <= 12; i++)
2188
2153
for (j = 3; j >= 0; j--)
2189
-
drm_dbg_kms(display->drm, "vdr_data[%d][%d] = 0x%.4x,\n",
2190
-
i, j, hw_state->data[i][j]);
2154
+
drm_printf(p, "vdr_data[%d][%d] = 0x%.4x,\n",
2155
+
i, j, hw_state->data[i][j]);
2191
2156
}
2192
2157
2193
2158
bool
···
2213
2174
return false;
2214
2175
}
2215
2176
2216
-
void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
2217
-
const struct intel_crtc_state *crtc_state,
2177
+
static bool intel_lt_phy_pll_is_enabled(struct intel_encoder *encoder)
2178
+
{
2179
+
struct intel_display *display = to_intel_display(encoder);
2180
+
2181
+
return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
2182
+
XELPDP_LANE_PCLK_PLL_ACK(0);
2183
+
}
2184
+
2185
+
bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
2186
+
struct intel_dpll *pll,
2187
+
struct intel_dpll_hw_state *hw_state)
2188
+
{
2189
+
memset(hw_state, 0, sizeof(*hw_state));
2190
+
2191
+
hw_state->ltpll.tbt_mode = true;
2192
+
2193
+
return true;
2194
+
}
2195
+
2196
+
bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
2218
2197
struct intel_lt_phy_pll_state *pll_state)
2219
2198
{
2220
2199
u8 owned_lane_mask;
···
2240
2183
struct ref_tracker *wakeref;
2241
2184
int i, j, k;
2242
2185
2186
+
if (!intel_lt_phy_pll_is_enabled(encoder))
2187
+
return false;
2188
+
2243
2189
pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
2244
2190
if (pll_state->tbt_mode)
2245
-
return;
2191
+
return false;
2246
2192
2247
2193
owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
2248
2194
lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;
2249
2195
wakeref = intel_lt_phy_transaction_begin(encoder);
2250
2196
2197
+
pll_state->lane_count = intel_readout_lane_count(encoder, INTEL_LT_PHY_LANE0,
2198
+
INTEL_LT_PHY_LANE1);
2251
2199
pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG);
2252
2200
pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);
2253
2201
pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG);
···
2265
2203
}
2266
2204
2267
2205
intel_lt_phy_transaction_end(encoder, wakeref);
2268
-
}
2269
2206
2270
-
void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
2271
-
struct intel_crtc *crtc)
2272
-
{
2273
-
struct intel_display *display = to_intel_display(state);
2274
-
struct intel_digital_port *dig_port;
2275
-
const struct intel_crtc_state *new_crtc_state =
2276
-
intel_atomic_get_new_crtc_state(state, crtc);
2277
-
struct intel_encoder *encoder;
2278
-
struct intel_lt_phy_pll_state pll_hw_state = {};
2279
-
const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll;
2280
-
2281
-
if (DISPLAY_VER(display) < 35)
2282
-
return;
2283
-
2284
-
if (!new_crtc_state->hw.active)
2285
-
return;
2286
-
2287
-
/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
2288
-
if (!intel_crtc_needs_modeset(new_crtc_state) &&
2289
-
!intel_crtc_needs_fastset(new_crtc_state))
2290
-
return;
2291
-
2292
-
encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
2293
-
intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state);
2294
-
2295
-
dig_port = enc_to_dig_port(encoder);
2296
-
if (intel_tc_port_in_tbt_alt_mode(dig_port))
2297
-
return;
2298
-
2299
-
INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] != pll_sw_state->config[0],
2300
-
"[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 0: (expected 0x%04x, found 0x%04x)",
2301
-
crtc->base.base.id, crtc->base.name,
2302
-
pll_sw_state->config[0], pll_hw_state.config[0]);
2303
-
INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] != pll_sw_state->config[2],
2304
-
"[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 2: (expected 0x%04x, found 0x%04x)",
2305
-
crtc->base.base.id, crtc->base.name,
2306
-
pll_sw_state->config[2], pll_hw_state.config[2]);
2207
+
return true;
2307
2208
}
2308
2209
2309
2210
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
2310
-
const struct intel_crtc_state *crtc_state)
2211
+
struct intel_dpll *pll,
2212
+
const struct intel_dpll_hw_state *dpll_hw_state)
2311
2213
{
2312
-
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2313
-
2314
-
if (intel_tc_port_in_tbt_alt_mode(dig_port))
2315
-
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
2316
-
else
2317
-
intel_lt_phy_pll_enable(encoder, crtc_state);
2214
+
intel_lt_phy_pll_enable(encoder, pll, dpll_hw_state);
2318
2215
}
2319
2216
2320
2217
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
···
2315
2294
drm_printf(&p, "PLL state %s (%s):\n",
2316
2295
pll_state_name,
2317
2296
is_precomputed_state ? "precomputed" : "computed");
2318
-
intel_lt_phy_dump_hw_state(display, pll_state);
2297
+
intel_lt_phy_dump_hw_state(&p, pll_state);
2319
2298
}
2320
2299
2321
2300
static void intel_lt_phy_pll_verify_params(struct intel_display *display,
+15
-8
drivers/gpu/drm/i915/display/intel_lt_phy.h
+15
-8
drivers/gpu/drm/i915/display/intel_lt_phy.h
···
8
8
9
9
#include <linux/types.h>
10
10
11
+
struct drm_printer;
11
12
struct intel_atomic_state;
12
13
struct intel_display;
14
+
struct intel_dpll;
15
+
struct intel_dpll_hw_state;
13
16
struct intel_encoder;
14
17
struct intel_crtc_state;
15
18
struct intel_crtc;
16
19
struct intel_lt_phy_pll_state;
17
20
18
21
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
19
-
const struct intel_crtc_state *crtc_state);
22
+
struct intel_dpll *pll,
23
+
const struct intel_dpll_hw_state *dpll_hw_state);
20
24
void intel_lt_phy_pll_disable(struct intel_encoder *encoder);
21
25
int
22
26
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
23
-
struct intel_encoder *encoder);
27
+
struct intel_encoder *encoder,
28
+
struct intel_dpll_hw_state *hw_state);
29
+
void intel_lt_phy_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state);
24
30
int intel_lt_phy_calc_port_clock(struct intel_display *display,
25
31
const struct intel_lt_phy_pll_state *lt_state);
26
32
void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
27
33
const struct intel_crtc_state *crtc_state);
28
-
void intel_lt_phy_dump_hw_state(struct intel_display *display,
34
+
void intel_lt_phy_dump_hw_state(struct drm_printer *p,
29
35
const struct intel_lt_phy_pll_state *hw_state);
30
36
bool
31
37
intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
32
38
const struct intel_lt_phy_pll_state *b);
33
-
void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
34
-
const struct intel_crtc_state *crtc_state,
39
+
bool intel_lt_phy_tbt_pll_readout_hw_state(struct intel_display *display,
40
+
struct intel_dpll *pll,
41
+
struct intel_dpll_hw_state *hw_state);
42
+
bool intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
35
43
struct intel_lt_phy_pll_state *pll_state);
36
-
void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
37
-
struct intel_crtc *crtc);
38
44
int
39
45
intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
40
46
u32 frequency_khz);
41
47
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
42
-
const struct intel_crtc_state *crtc_state);
48
+
struct intel_dpll *pll,
49
+
const struct intel_dpll_hw_state *dpll_hw_state);
43
50
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
44
51
void intel_lt_phy_verify_plls(struct intel_display *display);
45
52
-1
drivers/gpu/drm/i915/display/intel_modeset_verify.c
-1
drivers/gpu/drm/i915/display/intel_modeset_verify.c
+93
drivers/gpu/drm/i915/display/intel_pch.c
+93
drivers/gpu/drm/i915/display/intel_pch.c
···
5
5
6
6
#include <drm/drm_print.h>
7
7
8
+
#include "intel_de.h"
9
+
#include "intel_display.h"
10
+
#include "intel_display_regs.h"
8
11
#include "intel_display_core.h"
9
12
#include "intel_display_utils.h"
10
13
#include "intel_pch.h"
···
214
211
return PCH_ADP;
215
212
default:
216
213
return PCH_NONE;
214
+
}
215
+
}
216
+
217
+
static void intel_pch_ibx_init_clock_gating(struct intel_display *display)
218
+
{
219
+
/*
220
+
* On Ibex Peak and Cougar Point, we need to disable clock
221
+
* gating for the panel power sequencer or it will fail to
222
+
* start up when no ports are active.
223
+
*/
224
+
intel_de_write(display, SOUTH_DSPCLK_GATE_D,
225
+
PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
226
+
}
227
+
228
+
static void intel_pch_cpt_init_clock_gating(struct intel_display *display)
229
+
{
230
+
enum pipe pipe;
231
+
u32 val;
232
+
233
+
/*
234
+
* On Ibex Peak and Cougar Point, we need to disable clock
235
+
* gating for the panel power sequencer or it will fail to
236
+
* start up when no ports are active.
237
+
*/
238
+
intel_de_write(display, SOUTH_DSPCLK_GATE_D,
239
+
PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
240
+
PCH_DPLUNIT_CLOCK_GATE_DISABLE |
241
+
PCH_CPUNIT_CLOCK_GATE_DISABLE);
242
+
intel_de_rmw(display, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
243
+
244
+
/* The below fixes the weird display corruption, a few pixels shifted
245
+
* downward, on (only) LVDS of some HP laptops with IVY.
246
+
*/
247
+
for_each_pipe(display, pipe) {
248
+
val = intel_de_read(display, TRANS_CHICKEN2(pipe));
249
+
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
250
+
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
251
+
if (display->vbt.fdi_rx_polarity_inverted)
252
+
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
253
+
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
254
+
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
255
+
intel_de_write(display, TRANS_CHICKEN2(pipe), val);
256
+
}
257
+
258
+
/* WADP0ClockGatingDisable */
259
+
for_each_pipe(display, pipe)
260
+
intel_de_write(display, TRANS_CHICKEN1(pipe),
261
+
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
262
+
}
263
+
264
+
static void intel_pch_lpt_init_clock_gating(struct intel_display *display)
265
+
{
266
+
/*
267
+
* TODO: this bit should only be enabled when really needed, then
268
+
* disabled when not needed anymore in order to save power.
269
+
*/
270
+
if (HAS_PCH_LPT_LP(display))
271
+
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
272
+
PCH_LP_PARTITION_LEVEL_DISABLE);
273
+
274
+
/* WADPOClockGatingDisable:hsw */
275
+
intel_de_rmw(display, TRANS_CHICKEN1(PIPE_A), 0,
276
+
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
277
+
}
278
+
279
+
static void intel_pch_cnp_init_clock_gating(struct intel_display *display)
280
+
{
281
+
/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
282
+
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
283
+
CNP_PWM_CGE_GATING_DISABLE);
284
+
}
285
+
286
+
void intel_pch_init_clock_gating(struct intel_display *display)
287
+
{
288
+
switch (INTEL_PCH_TYPE(display)) {
289
+
case PCH_IBX:
290
+
intel_pch_ibx_init_clock_gating(display);
291
+
break;
292
+
case PCH_CPT:
293
+
intel_pch_cpt_init_clock_gating(display);
294
+
break;
295
+
case PCH_LPT_H:
296
+
case PCH_LPT_LP:
297
+
intel_pch_lpt_init_clock_gating(display);
298
+
break;
299
+
case PCH_CNP:
300
+
intel_pch_cnp_init_clock_gating(display);
301
+
break;
302
+
default:
303
+
break;
217
304
}
218
305
}
219
306
+1
drivers/gpu/drm/i915/display/intel_pch.h
+1
drivers/gpu/drm/i915/display/intel_pch.h
+23
-37
drivers/gpu/drm/i915/display/intel_plane.c
+23
-37
drivers/gpu/drm/i915/display/intel_plane.c
···
437
437
}
438
438
439
439
static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,
440
-
struct intel_plane_state *plane_state);
440
+
struct intel_plane_state *plane_state)
441
+
{
442
+
struct intel_display *display = to_intel_display(plane_state);
443
+
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
444
+
445
+
if (!plane_state->planar_linked_plane)
446
+
return;
447
+
448
+
plane_state->planar_linked_plane = NULL;
449
+
450
+
if (!plane_state->is_y_plane)
451
+
return;
452
+
453
+
drm_WARN_ON(display->drm, plane_state->uapi.visible);
454
+
455
+
plane_state->is_y_plane = false;
456
+
457
+
crtc_state->enabled_planes &= ~BIT(plane->id);
458
+
crtc_state->active_planes &= ~BIT(plane->id);
459
+
crtc_state->update_planes |= BIT(plane->id);
460
+
crtc_state->data_rate[plane->id] = 0;
461
+
crtc_state->rel_data_rate[plane->id] = 0;
462
+
}
441
463
442
464
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
443
465
struct intel_plane_state *plane_state)
···
1534
1512
icl_link_nv12_planes(uv_plane_state, y_plane_state);
1535
1513
}
1536
1514
1537
-
static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,
1538
-
struct intel_plane_state *plane_state)
1539
-
{
1540
-
struct intel_display *display = to_intel_display(plane_state);
1541
-
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1542
-
1543
-
if (!plane_state->planar_linked_plane)
1544
-
return;
1545
-
1546
-
plane_state->planar_linked_plane = NULL;
1547
-
1548
-
if (!plane_state->is_y_plane)
1549
-
return;
1550
-
1551
-
drm_WARN_ON(display->drm, plane_state->uapi.visible);
1552
-
1553
-
plane_state->is_y_plane = false;
1554
-
1555
-
crtc_state->enabled_planes &= ~BIT(plane->id);
1556
-
crtc_state->active_planes &= ~BIT(plane->id);
1557
-
crtc_state->update_planes |= BIT(plane->id);
1558
-
crtc_state->data_rate[plane->id] = 0;
1559
-
crtc_state->rel_data_rate[plane->id] = 0;
1560
-
}
1561
-
1562
1515
static int icl_check_nv12_planes(struct intel_atomic_state *state,
1563
1516
struct intel_crtc *crtc)
1564
1517
{
···
1546
1549
1547
1550
if (DISPLAY_VER(display) < 11)
1548
1551
return 0;
1549
-
1550
-
/*
1551
-
* Destroy all old plane links and make the Y plane invisible
1552
-
* in the crtc_state->active_planes mask.
1553
-
*/
1554
-
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1555
-
if (plane->pipe != crtc->pipe)
1556
-
continue;
1557
-
1558
-
unlink_nv12_plane(crtc_state, plane_state);
1559
-
}
1560
1552
1561
1553
if (!crtc_state->nv12_planes)
1562
1554
return 0;
+8
drivers/gpu/drm/i915/display/intel_psr.c
+8
drivers/gpu/drm/i915/display/intel_psr.c
···
49
49
#include "intel_hdmi.h"
50
50
#include "intel_psr.h"
51
51
#include "intel_psr_regs.h"
52
+
#include "intel_quirks.h"
52
53
#include "intel_snps_phy.h"
53
54
#include "intel_step.h"
54
55
#include "intel_vblank.h"
···
609
608
/* TODO: Enable Panel Replay on MST once it's properly implemented. */
610
609
if (intel_dp->mst_detect == DRM_DP_MST)
611
610
return;
611
+
612
+
if (intel_dp_is_edp(intel_dp) &&
613
+
intel_has_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY)) {
614
+
drm_dbg_kms(display->drm,
615
+
"Panel Replay support not currently available for this setup\n");
616
+
return;
617
+
}
612
618
613
619
ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
614
620
&connector->dp.panel_replay_caps.dpcd,
+22
-3
drivers/gpu/drm/i915/display/intel_quirks.c
+22
-3
drivers/gpu/drm/i915/display/intel_quirks.c
···
86
86
drm_info(display->drm, "Applying eDP Limit rate to HBR2 quirk\n");
87
87
}
88
88
89
+
static void quirk_disable_edp_panel_replay(struct intel_dp *intel_dp)
90
+
{
91
+
struct intel_display *display = to_intel_display(intel_dp);
92
+
93
+
intel_set_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY);
94
+
drm_info(display->drm, "Applying disable Panel Replay quirk\n");
95
+
}
96
+
89
97
struct intel_quirk {
90
98
int device;
91
99
int subsystem_vendor;
···
115
107
{ (first), (second), (third), (fourth), (fifth), (sixth) }
116
108
117
109
#define SINK_DEVICE_ID_ANY SINK_DEVICE_ID(0, 0, 0, 0, 0, 0)
110
+
111
+
#define DEVICE_ID_ANY 0
118
112
119
113
/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
120
114
struct intel_dmi_quirk {
···
261
251
.sink_oui = SINK_OUI(0x38, 0xec, 0x11),
262
252
.hook = quirk_fw_sync_len,
263
253
},
264
-
254
+
/* Dell XPS 14 DA14260 */
255
+
{
256
+
.device = DEVICE_ID_ANY,
257
+
.subsystem_vendor = 0x1028,
258
+
.subsystem_device = 0x0db9,
259
+
.sink_oui = SINK_OUI(0x00, 0x22, 0xb9),
260
+
.hook = quirk_disable_edp_panel_replay,
261
+
},
265
262
};
266
263
267
264
void intel_init_quirks(struct intel_display *display)
···
279
262
for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
280
263
struct intel_quirk *q = &intel_quirks[i];
281
264
282
-
if (d->device == q->device &&
265
+
if ((d->device == q->device ||
266
+
q->device == DEVICE_ID_ANY) &&
283
267
(d->subsystem_vendor == q->subsystem_vendor ||
284
268
q->subsystem_vendor == PCI_ANY_ID) &&
285
269
(d->subsystem_device == q->subsystem_device ||
···
303
285
for (i = 0; i < ARRAY_SIZE(intel_dpcd_quirks); i++) {
304
286
const struct intel_dpcd_quirk *q = &intel_dpcd_quirks[i];
305
287
306
-
if (d->device == q->device &&
288
+
if ((d->device == q->device ||
289
+
q->device == DEVICE_ID_ANY) &&
307
290
(d->subsystem_vendor == q->subsystem_vendor ||
308
291
q->subsystem_vendor == PCI_ANY_ID) &&
309
292
(d->subsystem_device == q->subsystem_device ||
+1
drivers/gpu/drm/i915/display/intel_quirks.h
+1
drivers/gpu/drm/i915/display/intel_quirks.h
+105
-57
drivers/gpu/drm/i915/display/skl_watermark.c
+105
-57
drivers/gpu/drm/i915/display/skl_watermark.c
···
63
63
struct skl_wm_params {
64
64
bool x_tiled, y_tiled;
65
65
bool rc_surface;
66
-
bool is_planar;
67
66
u32 width;
68
67
u8 cpp;
69
68
u32 plane_pixel_rate;
···
1356
1357
}
1357
1358
1358
1359
static void
1359
-
skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
1360
-
const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
1360
+
skl_check_wm_level_nv12(struct skl_wm_level *wm,
1361
+
const struct skl_ddb_entry *ddb_y,
1362
+
const struct skl_ddb_entry *ddb)
1361
1363
{
1362
1364
if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||
1363
-
uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) {
1365
+
wm->min_ddb_alloc_uv > skl_ddb_entry_size(ddb))
1364
1366
memset(wm, 0, sizeof(*wm));
1365
-
memset(uv_wm, 0, sizeof(*uv_wm));
1366
-
}
1367
1367
}
1368
1368
1369
1369
static bool skl_need_wm_copy_wa(struct intel_display *display, int level,
···
1389
1391
};
1390
1392
1391
1393
static void
1392
-
skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
1393
-
struct skl_ddb_entry *ddb,
1394
-
const struct skl_wm_level *wm,
1395
-
u64 data_rate)
1394
+
_skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
1395
+
u16 min_ddb_alloc,
1396
+
struct skl_ddb_entry *ddb, u64 data_rate)
1396
1397
{
1397
1398
u16 size, extra = 0;
1398
1399
···
1408
1411
* to avoid skl_ddb_add_affected_planes() adding them to
1409
1412
* the state when other planes change their allocations.
1410
1413
*/
1411
-
size = wm->min_ddb_alloc + extra;
1414
+
size = min_ddb_alloc + extra;
1412
1415
if (size)
1413
1416
iter->start = skl_ddb_entry_init(ddb, iter->start,
1414
1417
iter->start + size);
1418
+
}
1419
+
1420
+
static void
1421
+
skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
1422
+
const struct skl_wm_level *wm,
1423
+
struct skl_ddb_entry *ddb, u64 data_rate)
1424
+
{
1425
+
_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc, ddb, data_rate);
1426
+
}
1427
+
1428
+
static void
1429
+
skl_allocate_plane_ddb_nv12(struct skl_plane_ddb_iter *iter,
1430
+
const struct skl_wm_level *wm,
1431
+
struct skl_ddb_entry *ddb_y, u64 data_rate_y,
1432
+
struct skl_ddb_entry *ddb, u64 data_rate)
1433
+
{
1434
+
_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc, ddb_y, data_rate_y);
1435
+
_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc_uv, ddb, data_rate);
1415
1436
}
1416
1437
1417
1438
static int
···
1497
1482
}
1498
1483
1499
1484
blocks += wm->wm[level].min_ddb_alloc;
1500
-
blocks += wm->uv_wm[level].min_ddb_alloc;
1485
+
blocks += wm->wm[level].min_ddb_alloc_uv;
1501
1486
}
1502
1487
1503
1488
if (blocks <= iter.size) {
···
1538
1523
continue;
1539
1524
1540
1525
if (DISPLAY_VER(display) < 11 &&
1541
-
crtc_state->nv12_planes & BIT(plane_id)) {
1542
-
skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level],
1543
-
crtc_state->rel_data_rate_y[plane_id]);
1544
-
skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level],
1545
-
crtc_state->rel_data_rate[plane_id]);
1546
-
} else {
1547
-
skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level],
1548
-
crtc_state->rel_data_rate[plane_id]);
1549
-
}
1526
+
crtc_state->nv12_planes & BIT(plane_id))
1527
+
skl_allocate_plane_ddb_nv12(&iter, &wm->wm[level],
1528
+
ddb_y, crtc_state->rel_data_rate_y[plane_id],
1529
+
ddb, crtc_state->rel_data_rate[plane_id]);
1530
+
else
1531
+
skl_allocate_plane_ddb(&iter, &wm->wm[level],
1532
+
ddb, crtc_state->rel_data_rate[plane_id]);
1550
1533
1551
1534
if (DISPLAY_VER(display) >= 30) {
1552
1535
*min_ddb = wm->wm[0].min_ddb_alloc;
···
1570
1557
1571
1558
if (DISPLAY_VER(display) < 11 &&
1572
1559
crtc_state->nv12_planes & BIT(plane_id))
1573
-
skl_check_nv12_wm_level(&wm->wm[level],
1574
-
&wm->uv_wm[level],
1575
-
ddb_y, ddb);
1560
+
skl_check_wm_level_nv12(&wm->wm[level], ddb_y, ddb);
1576
1561
else
1577
1562
skl_check_wm_level(&wm->wm[level], ddb);
1578
1563
···
1686
1675
wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED &&
1687
1676
intel_fb_is_tiled_modifier(modifier);
1688
1677
wp->rc_surface = intel_fb_is_ccs_modifier(modifier);
1689
-
wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
1690
1678
1691
1679
wp->width = width;
1692
-
if (color_plane == 1 && wp->is_planar)
1680
+
if (color_plane == 1 && intel_format_info_is_yuv_semiplanar(format, modifier))
1693
1681
wp->width /= 2;
1694
1682
1695
1683
wp->cpp = format->cpp[color_plane];
···
2079
2069
const struct intel_plane_state *plane_state,
2080
2070
struct intel_plane *plane)
2081
2071
{
2072
+
struct intel_display *display = to_intel_display(crtc_state);
2082
2073
struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
2074
+
struct skl_wm_level uv_wm[ARRAY_SIZE(wm->wm)] = {};
2083
2075
struct skl_wm_params wm_params;
2084
-
int ret;
2085
-
2086
-
wm->is_planar = true;
2076
+
int ret, level;
2087
2077
2088
2078
/* uv plane watermarks must also be validated for NV12/Planar */
2089
2079
ret = skl_compute_plane_wm_params(crtc_state, plane_state,
···
2091
2081
if (ret)
2092
2082
return ret;
2093
2083
2094
-
skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);
2084
+
skl_compute_wm_levels(crtc_state, plane, &wm_params, uv_wm);
2085
+
2086
+
/*
2087
+
* Only keep the min_ddb_alloc for UV as
2088
+
* the hardware needs nothing else.
2089
+
*/
2090
+
for (level = 0; level < display->wm.num_levels; level++)
2091
+
wm->wm[level].min_ddb_alloc_uv = uv_wm[level].min_ddb_alloc;
2095
2092
2096
2093
return 0;
2097
2094
}
···
2321
2304
* thing as bad via min_ddb_alloc=U16_MAX?
2322
2305
*/
2323
2306
wm->wm[level].enable = false;
2324
-
wm->uv_wm[level].enable = false;
2325
2307
}
2326
2308
}
2327
2309
···
2391
2375
int level;
2392
2376
2393
2377
for (level = 0; level < display->wm.num_levels; level++) {
2394
-
/*
2395
-
* We don't check uv_wm as the hardware doesn't actually
2396
-
* use it. It only gets used for calculating the required
2397
-
* ddb allocation.
2398
-
*/
2399
2378
if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
2400
2379
return false;
2401
2380
}
···
2601
2590
return enable ? '*' : ' ';
2602
2591
}
2603
2592
2604
-
static noinline_for_stack void
2605
-
skl_print_plane_changes(struct intel_display *display,
2606
-
struct intel_plane *plane,
2607
-
const struct skl_plane_wm *old_wm,
2608
-
const struct skl_plane_wm *new_wm)
2593
+
static void
2594
+
skl_print_plane_ddb_changes(struct intel_plane *plane,
2595
+
const struct skl_ddb_entry *old,
2596
+
const struct skl_ddb_entry *new,
2597
+
const char *ddb_name)
2609
2598
{
2599
+
struct intel_display *display = to_intel_display(plane);
2600
+
2610
2601
drm_dbg_kms(display->drm,
2611
-
"[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
2602
+
"[PLANE:%d:%s] %5s (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
2603
+
plane->base.base.id, plane->base.name, ddb_name,
2604
+
old->start, old->end, new->start, new->end,
2605
+
skl_ddb_entry_size(old), skl_ddb_entry_size(new));
2606
+
}
2607
+
2608
+
static noinline_for_stack void
2609
+
skl_print_plane_wm_changes(struct intel_plane *plane,
2610
+
const struct skl_plane_wm *old_wm,
2611
+
const struct skl_plane_wm *new_wm)
2612
+
{
2613
+
struct intel_display *display = to_intel_display(plane);
2614
+
2615
+
drm_dbg_kms(display->drm,
2616
+
"[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
2612
2617
" -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
2613
2618
plane->base.base.id, plane->base.name,
2614
2619
enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
···
2643
2616
enast(new_wm->sagv.trans_wm.enable));
2644
2617
2645
2618
drm_dbg_kms(display->drm,
2646
-
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
2619
+
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
2647
2620
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
2648
2621
plane->base.base.id, plane->base.name,
2649
2622
enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
···
2670
2643
enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
2671
2644
2672
2645
drm_dbg_kms(display->drm,
2673
-
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
2646
+
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
2674
2647
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
2675
2648
plane->base.base.id, plane->base.name,
2676
2649
old_wm->wm[0].blocks, old_wm->wm[1].blocks,
···
2689
2662
new_wm->sagv.trans_wm.blocks);
2690
2663
2691
2664
drm_dbg_kms(display->drm,
2692
-
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
2665
+
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
2693
2666
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
2694
2667
plane->base.base.id, plane->base.name,
2695
2668
old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
···
2706
2679
new_wm->trans_wm.min_ddb_alloc,
2707
2680
new_wm->sagv.wm0.min_ddb_alloc,
2708
2681
new_wm->sagv.trans_wm.min_ddb_alloc);
2682
+
2683
+
if (DISPLAY_VER(display) >= 11)
2684
+
return;
2685
+
2686
+
drm_dbg_kms(display->drm,
2687
+
"[PLANE:%d:%s] min_ddb_uv %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
2688
+
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
2689
+
plane->base.base.id, plane->base.name,
2690
+
old_wm->wm[0].min_ddb_alloc_uv, old_wm->wm[1].min_ddb_alloc_uv,
2691
+
old_wm->wm[2].min_ddb_alloc_uv, old_wm->wm[3].min_ddb_alloc_uv,
2692
+
old_wm->wm[4].min_ddb_alloc_uv, old_wm->wm[5].min_ddb_alloc_uv,
2693
+
old_wm->wm[6].min_ddb_alloc_uv, old_wm->wm[7].min_ddb_alloc_uv,
2694
+
old_wm->trans_wm.min_ddb_alloc_uv,
2695
+
old_wm->sagv.wm0.min_ddb_alloc_uv,
2696
+
old_wm->sagv.trans_wm.min_ddb_alloc_uv,
2697
+
new_wm->wm[0].min_ddb_alloc_uv, new_wm->wm[1].min_ddb_alloc_uv,
2698
+
new_wm->wm[2].min_ddb_alloc_uv, new_wm->wm[3].min_ddb_alloc_uv,
2699
+
new_wm->wm[4].min_ddb_alloc_uv, new_wm->wm[5].min_ddb_alloc_uv,
2700
+
new_wm->wm[6].min_ddb_alloc_uv, new_wm->wm[7].min_ddb_alloc_uv,
2701
+
new_wm->trans_wm.min_ddb_alloc_uv,
2702
+
new_wm->sagv.wm0.min_ddb_alloc_uv,
2703
+
new_wm->sagv.trans_wm.min_ddb_alloc_uv);
2709
2704
}
2710
2705
2711
2706
static void
···
2757
2708
old = &old_crtc_state->wm.skl.plane_ddb[plane_id];
2758
2709
new = &new_crtc_state->wm.skl.plane_ddb[plane_id];
2759
2710
2760
-
if (skl_ddb_entry_equal(old, new))
2711
+
if (!skl_ddb_entry_equal(old, new))
2712
+
skl_print_plane_ddb_changes(plane, old, new, "ddb");
2713
+
2714
+
if (DISPLAY_VER(display) >= 11)
2761
2715
continue;
2762
-
drm_dbg_kms(display->drm,
2763
-
"[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
2764
-
plane->base.base.id, plane->base.name,
2765
-
old->start, old->end, new->start, new->end,
2766
-
skl_ddb_entry_size(old), skl_ddb_entry_size(new));
2716
+
2717
+
old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
2718
+
new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
2719
+
2720
+
if (!skl_ddb_entry_equal(old, new))
2721
+
skl_print_plane_ddb_changes(plane, old, new, "ddb_y");
2767
2722
}
2768
2723
2769
2724
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
···
2780
2727
if (skl_plane_wm_equals(display, old_wm, new_wm))
2781
2728
continue;
2782
2729
2783
-
skl_print_plane_changes(display, plane, old_wm, new_wm);
2730
+
skl_print_plane_wm_changes(plane, old_wm, new_wm);
2784
2731
}
2785
2732
}
2786
2733
}
···
2793
2740
int level;
2794
2741
2795
2742
for (level = 0; level < display->wm.num_levels; level++) {
2796
-
/*
2797
-
* We don't check uv_wm as the hardware doesn't actually
2798
-
* use it. It only gets used for calculating the required
2799
-
* ddb allocation.
2800
-
*/
2801
2743
if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level),
2802
2744
skl_plane_wm_level(new_pipe_wm, plane->id, level)))
2803
2745
return false;
+1
-1
drivers/gpu/drm/i915/display/vlv_dsi.c
+1
-1
drivers/gpu/drm/i915/display/vlv_dsi.c
+8
-10
drivers/gpu/drm/i915/gvt/edid.c
+8
-10
drivers/gpu/drm/i915/gvt/edid.c
···
535
535
i2c_edid->edid_available = true;
536
536
}
537
537
}
538
-
} else if ((op & 0x1) == DP_AUX_I2C_WRITE) {
539
-
/* TODO
540
-
* We only support EDID reading from I2C_over_AUX. And
541
-
* we do not expect the index mode to be used. Right now
542
-
* the WRITE operation is ignored. It is good enough to
543
-
* support the gfx driver to do EDID access.
544
-
*/
545
-
} else {
546
-
if (drm_WARN_ON(&i915->drm, (op & 0x1) != DP_AUX_I2C_READ))
547
-
return;
538
+
} else if ((op & 0x1) == DP_AUX_I2C_READ) {
548
539
if (drm_WARN_ON(&i915->drm, msg_length != 4))
549
540
return;
550
541
if (i2c_edid->edid_available && i2c_edid->target_selected) {
···
544
553
aux_data_for_write = (val << 16);
545
554
} else
546
555
aux_data_for_write = (0xff << 16);
556
+
} else {
557
+
/* TODO
558
+
* We only support EDID reading from I2C_over_AUX. And
559
+
* we do not expect the index mode to be used. Right now
560
+
* the WRITE operation is ignored. It is good enough to
561
+
* support the gfx driver to do EDID access.
562
+
*/
547
563
}
548
564
/* write the return value in AUX_CH_DATA reg which includes:
549
565
* ACK of I2C_WRITE
+2
-1
drivers/gpu/drm/i915/i915_initial_plane.c
+2
-1
drivers/gpu/drm/i915/i915_initial_plane.c
···
115
115
* important and we should probably use that space with FBC or other
116
116
* features.
117
117
*/
118
-
if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
118
+
if (IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION) &&
119
+
IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
119
120
mem == i915->mm.stolen_region &&
120
121
!intel_fbdev_fb_prefer_stolen(&i915->drm, size)) {
121
122
drm_dbg_kms(&i915->drm, "Initial FB size exceeds half of stolen, discarding\n");
+7
-79
drivers/gpu/drm/i915/intel_clock_gating.c
+7
-79
drivers/gpu/drm/i915/intel_clock_gating.c
···
33
33
#include "display/intel_display.h"
34
34
#include "display/intel_display_core.h"
35
35
#include "display/intel_display_regs.h"
36
+
#include "display/intel_pch.h"
36
37
#include "gt/intel_engine_regs.h"
37
38
#include "gt/intel_gt.h"
38
39
#include "gt/intel_gt_mcr.h"
···
125
124
PWM1_GATING_DIS | PWM2_GATING_DIS);
126
125
}
127
126
128
-
static void ibx_init_clock_gating(struct drm_i915_private *i915)
129
-
{
130
-
/*
131
-
* On Ibex Peak and Cougar Point, we need to disable clock
132
-
* gating for the panel power sequencer or it will fail to
133
-
* start up when no ports are active.
134
-
*/
135
-
intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
136
-
}
137
-
138
127
static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
139
128
{
140
129
struct intel_display *display = dev_priv->display;
···
193
202
194
203
g4x_disable_trickle_feed(i915);
195
204
196
-
ibx_init_clock_gating(i915);
197
-
}
198
-
199
-
static void cpt_init_clock_gating(struct drm_i915_private *i915)
200
-
{
201
-
struct intel_display *display = i915->display;
202
-
enum pipe pipe;
203
-
u32 val;
204
-
205
-
/*
206
-
* On Ibex Peak and Cougar Point, we need to disable clock
207
-
* gating for the panel power sequencer or it will fail to
208
-
* start up when no ports are active.
209
-
*/
210
-
intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
211
-
PCH_DPLUNIT_CLOCK_GATE_DISABLE |
212
-
PCH_CPUNIT_CLOCK_GATE_DISABLE);
213
-
intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
214
-
/* The below fixes the weird display corruption, a few pixels shifted
215
-
* downward, on (only) LVDS of some HP laptops with IVY.
216
-
*/
217
-
for_each_pipe(display, pipe) {
218
-
val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));
219
-
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
220
-
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
221
-
if (display->vbt.fdi_rx_polarity_inverted)
222
-
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
223
-
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
224
-
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
225
-
intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);
226
-
}
227
-
/* WADP0ClockGatingDisable */
228
-
for_each_pipe(display, pipe) {
229
-
intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe),
230
-
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
231
-
}
205
+
intel_pch_init_clock_gating(i915->display);
232
206
}
233
207
234
208
static void gen6_check_mch_setup(struct drm_i915_private *i915)
···
261
305
262
306
g4x_disable_trickle_feed(i915);
263
307
264
-
cpt_init_clock_gating(i915);
308
+
intel_pch_init_clock_gating(i915->display);
265
309
266
310
gen6_check_mch_setup(i915);
267
-
}
268
-
269
-
static void lpt_init_clock_gating(struct drm_i915_private *i915)
270
-
{
271
-
struct intel_display *display = i915->display;
272
-
273
-
/*
274
-
* TODO: this bit should only be enabled when really needed, then
275
-
* disabled when not needed anymore in order to save power.
276
-
*/
277
-
if (HAS_PCH_LPT_LP(display))
278
-
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,
279
-
0, PCH_LP_PARTITION_LEVEL_DISABLE);
280
-
281
-
/* WADPOClockGatingDisable:hsw */
282
-
intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A),
283
-
0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
284
311
}
285
312
286
313
static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
···
299
360
SGSI_SIDECLK_DIS);
300
361
}
301
362
302
-
static void cnp_init_clock_gating(struct drm_i915_private *i915)
303
-
{
304
-
struct intel_display *display = i915->display;
305
-
306
-
if (!HAS_PCH_CNP(display))
307
-
return;
308
-
309
-
/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
310
-
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
311
-
}
312
-
313
363
static void cfl_init_clock_gating(struct drm_i915_private *i915)
314
364
{
315
-
cnp_init_clock_gating(i915);
365
+
intel_pch_init_clock_gating(i915->display);
316
366
gen9_init_clock_gating(i915);
317
367
318
368
/* WAC6entrylatency:cfl */
···
394
466
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1,
395
467
0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
396
468
397
-
lpt_init_clock_gating(i915);
469
+
intel_pch_init_clock_gating(i915->display);
398
470
399
471
/* WaDisableDopClockGating:bdw
400
472
*
···
428
500
/* WaSwitchSolVfFArbitrationPriority:hsw */
429
501
intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
430
502
431
-
lpt_init_clock_gating(i915);
503
+
intel_pch_init_clock_gating(i915->display);
432
504
}
433
505
434
506
static void ivb_init_clock_gating(struct drm_i915_private *i915)
···
473
545
GEN6_MBC_SNPCR_MED);
474
546
475
547
if (!HAS_PCH_NOP(display))
476
-
cpt_init_clock_gating(i915);
548
+
intel_pch_init_clock_gating(display);
477
549
478
550
gen6_check_mch_setup(i915);
479
551
}
+2
-55
drivers/gpu/drm/i915/intel_step.h
+2
-55
drivers/gpu/drm/i915/intel_step.h
···
8
8
9
9
#include <linux/types.h>
10
10
11
+
#include <drm/intel/step.h>
12
+
11
13
struct drm_i915_private;
12
14
13
15
struct intel_step_info {
···
19
17
*/
20
18
u8 graphics_step; /* Represents the compute tile on Xe_HPC */
21
19
u8 media_step;
22
-
};
23
-
24
-
#define STEP_ENUM_VAL(name) STEP_##name,
25
-
26
-
#define STEP_NAME_LIST(func) \
27
-
func(A0) \
28
-
func(A1) \
29
-
func(A2) \
30
-
func(A3) \
31
-
func(B0) \
32
-
func(B1) \
33
-
func(B2) \
34
-
func(B3) \
35
-
func(C0) \
36
-
func(C1) \
37
-
func(C2) \
38
-
func(C3) \
39
-
func(D0) \
40
-
func(D1) \
41
-
func(D2) \
42
-
func(D3) \
43
-
func(E0) \
44
-
func(E1) \
45
-
func(E2) \
46
-
func(E3) \
47
-
func(F0) \
48
-
func(F1) \
49
-
func(F2) \
50
-
func(F3) \
51
-
func(G0) \
52
-
func(G1) \
53
-
func(G2) \
54
-
func(G3) \
55
-
func(H0) \
56
-
func(H1) \
57
-
func(H2) \
58
-
func(H3) \
59
-
func(I0) \
60
-
func(I1) \
61
-
func(I2) \
62
-
func(I3) \
63
-
func(J0) \
64
-
func(J1) \
65
-
func(J2) \
66
-
func(J3)
67
-
68
-
/*
69
-
* Symbolic steppings that do not match the hardware. These are valid both as gt
70
-
* and display steppings as symbolic names.
71
-
*/
72
-
enum intel_step {
73
-
STEP_NONE = 0,
74
-
STEP_NAME_LIST(STEP_ENUM_VAL)
75
-
STEP_FUTURE,
76
-
STEP_FOREVER,
77
20
};
78
21
79
22
void intel_step_init(struct drm_i915_private *i915);
+50
-22
drivers/gpu/drm/i915/intel_uncore.c
+50
-22
drivers/gpu/drm/i915/intel_uncore.c
···
399
399
__gen6_gt_wait_for_thread_c0(uncore);
400
400
}
401
401
402
+
static void
403
+
gen6_check_for_fifo_debug(struct intel_uncore *uncore)
404
+
{
405
+
u32 fifodbg;
406
+
407
+
fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
408
+
409
+
if (unlikely(fifodbg)) {
410
+
drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
411
+
__raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
412
+
}
413
+
}
414
+
415
+
static void
416
+
fw_domains_get_normal_fifo(struct intel_uncore *uncore,
417
+
enum forcewake_domains fw_domains)
418
+
{
419
+
gen6_check_for_fifo_debug(uncore);
420
+
fw_domains_get_normal(uncore, fw_domains);
421
+
}
422
+
423
+
static void
424
+
fw_domains_get_with_thread_status_fifo(struct intel_uncore *uncore,
425
+
enum forcewake_domains fw_domains)
426
+
{
427
+
gen6_check_for_fifo_debug(uncore);
428
+
fw_domains_get_with_thread_status(uncore, fw_domains);
429
+
}
430
+
402
431
static inline u32 fifo_free_entries(struct intel_uncore *uncore)
403
432
{
404
433
u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
···
591
562
}
592
563
593
564
static bool
594
-
gen6_check_for_fifo_debug(struct intel_uncore *uncore)
595
-
{
596
-
u32 fifodbg;
597
-
598
-
fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
599
-
600
-
if (unlikely(fifodbg)) {
601
-
drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
602
-
__raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
603
-
}
604
-
605
-
return fifodbg;
606
-
}
607
-
608
-
static bool
609
565
check_for_unclaimed_mmio(struct intel_uncore *uncore)
610
566
{
611
567
bool ret = false;
···
605
591
606
592
if (intel_uncore_has_dbg_unclaimed(uncore))
607
593
ret |= vlv_check_for_unclaimed_mmio(uncore);
608
-
609
-
if (intel_uncore_has_fifo(uncore))
610
-
ret |= gen6_check_for_fifo_debug(uncore);
611
594
612
595
return ret;
613
596
}
···
621
610
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
622
611
GT_FIFO_CTL_RC6_POLICY_STALL);
623
612
}
613
+
614
+
if (intel_uncore_has_fifo(uncore))
615
+
gen6_check_for_fifo_debug(uncore);
624
616
625
617
iosf_mbi_punit_acquire();
626
618
intel_uncore_forcewake_reset(uncore);
···
2169
2155
.force_wake_get = fw_domains_get_with_thread_status
2170
2156
};
2171
2157
2158
+
static const struct intel_uncore_fw_get uncore_get_normal_fifo = {
2159
+
.force_wake_get = fw_domains_get_normal_fifo,
2160
+
};
2161
+
2162
+
static const struct intel_uncore_fw_get uncore_get_thread_status_fifo = {
2163
+
.force_wake_get = fw_domains_get_with_thread_status_fifo
2164
+
};
2165
+
2172
2166
static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
2173
2167
{
2174
2168
struct drm_i915_private *i915 = uncore->i915;
···
2240
2218
fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
2241
2219
FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
2242
2220
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
2243
-
uncore->fw_get_funcs = &uncore_get_normal;
2221
+
if (intel_uncore_has_fifo(uncore))
2222
+
uncore->fw_get_funcs = &uncore_get_normal_fifo;
2223
+
else
2224
+
uncore->fw_get_funcs = &uncore_get_normal;
2244
2225
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2245
2226
FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
2246
2227
fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
2247
2228
FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
2248
2229
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2249
-
uncore->fw_get_funcs = &uncore_get_thread_status;
2230
+
if (intel_uncore_has_fifo(uncore))
2231
+
uncore->fw_get_funcs = &uncore_get_thread_status_fifo;
2232
+
else
2233
+
uncore->fw_get_funcs = &uncore_get_thread_status;
2250
2234
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2251
2235
FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
2252
2236
} else if (IS_IVYBRIDGE(i915)) {
···
2267
2239
* (correctly) interpreted by the test below as MT
2268
2240
* forcewake being disabled.
2269
2241
*/
2270
-
uncore->fw_get_funcs = &uncore_get_thread_status;
2242
+
uncore->fw_get_funcs = &uncore_get_thread_status_fifo;
2271
2243
2272
2244
/* We need to init first for ECOBUS access and then
2273
2245
* determine later if we want to reinit, in case of MT access is
···
2298
2270
FORCEWAKE, FORCEWAKE_ACK);
2299
2271
}
2300
2272
} else if (GRAPHICS_VER(i915) == 6) {
2301
-
uncore->fw_get_funcs = &uncore_get_thread_status;
2273
+
uncore->fw_get_funcs = &uncore_get_thread_status_fifo;
2302
2274
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2303
2275
FORCEWAKE, FORCEWAKE_ACK);
2304
2276
}
-62
drivers/gpu/drm/i915/selftests/intel_uncore.c
-62
drivers/gpu/drm/i915/selftests/intel_uncore.c
···
272
272
return err;
273
273
}
274
274
275
-
static int live_forcewake_domains(void *arg)
276
-
{
277
-
#define FW_RANGE 0x40000
278
-
struct intel_gt *gt = arg;
279
-
struct intel_uncore *uncore = gt->uncore;
280
-
struct drm_i915_private *i915 = gt->i915;
281
-
struct intel_display *display = i915->display;
282
-
unsigned long *valid;
283
-
u32 offset;
284
-
int err;
285
-
286
-
if (!HAS_FPGA_DBG_UNCLAIMED(display) &&
287
-
!IS_VALLEYVIEW(i915) &&
288
-
!IS_CHERRYVIEW(i915))
289
-
return 0;
290
-
291
-
/*
292
-
* This test may lockup the machine or cause GPU hangs afterwards.
293
-
*/
294
-
if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
295
-
return 0;
296
-
297
-
valid = bitmap_zalloc(FW_RANGE, GFP_KERNEL);
298
-
if (!valid)
299
-
return -ENOMEM;
300
-
301
-
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
302
-
303
-
check_for_unclaimed_mmio(uncore);
304
-
for (offset = 0; offset < FW_RANGE; offset += 4) {
305
-
i915_reg_t reg = { offset };
306
-
307
-
intel_uncore_posting_read_fw(uncore, reg);
308
-
if (!check_for_unclaimed_mmio(uncore))
309
-
set_bit(offset, valid);
310
-
}
311
-
312
-
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
313
-
314
-
err = 0;
315
-
for_each_set_bit(offset, valid, FW_RANGE) {
316
-
i915_reg_t reg = { offset };
317
-
318
-
iosf_mbi_punit_acquire();
319
-
intel_uncore_forcewake_reset(uncore);
320
-
iosf_mbi_punit_release();
321
-
322
-
check_for_unclaimed_mmio(uncore);
323
-
324
-
intel_uncore_posting_read_fw(uncore, reg);
325
-
if (check_for_unclaimed_mmio(uncore)) {
326
-
pr_err("Unclaimed mmio read to register 0x%04x\n",
327
-
offset);
328
-
err = -EINVAL;
329
-
}
330
-
}
331
-
332
-
bitmap_free(valid);
333
-
return err;
334
-
}
335
-
336
275
static int live_fw_table(void *arg)
337
276
{
338
277
struct intel_gt *gt = arg;
···
287
348
static const struct i915_subtest tests[] = {
288
349
SUBTEST(live_fw_table),
289
350
SUBTEST(live_forcewake_ops),
290
-
SUBTEST(live_forcewake_domains),
291
351
};
292
352
293
353
return intel_gt_live_subtests(tests, to_gt(i915));
+1
drivers/gpu/drm/xe/Makefile
+1
drivers/gpu/drm/xe/Makefile
+1
-2
drivers/gpu/drm/xe/compat-i915-headers/intel_step.h
+1
-2
drivers/gpu/drm/xe/compat-i915-headers/intel_step.h
-31
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
-31
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
···
98
98
return xe_mmio_rmw32(__compat_uncore_to_mmio(uncore), reg, clear, set);
99
99
}
100
100
101
-
static inline int
102
-
__intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg,
103
-
u32 mask, u32 value, unsigned int fast_timeout_us,
104
-
unsigned int slow_timeout_ms, u32 *out_value)
105
-
{
106
-
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
107
-
bool atomic;
108
-
109
-
/*
110
-
* Replicate the behavior from i915 here, in which sleep is not
111
-
* performed if slow_timeout_ms == 0. This is necessary because
112
-
* of some paths in display code where waits are done in atomic
113
-
* context.
114
-
*/
115
-
atomic = !slow_timeout_ms && fast_timeout_us > 0;
116
-
117
-
return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
118
-
fast_timeout_us + 1000 * slow_timeout_ms,
119
-
out_value, atomic);
120
-
}
121
-
122
-
static inline int
123
-
__intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t i915_reg,
124
-
u32 mask, u32 value, unsigned int fast_timeout_us,
125
-
unsigned int slow_timeout_ms, u32 *out_value)
126
-
{
127
-
return __intel_wait_for_register(uncore, i915_reg, mask, value,
128
-
fast_timeout_us, slow_timeout_ms,
129
-
out_value);
130
-
}
131
-
132
101
static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,
133
102
i915_reg_t i915_reg)
134
103
{
+62
include/drm/intel/step.h
+62
include/drm/intel/step.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/* Copyright © 2026 Intel Corporation */
3
+
4
+
#ifndef __STEP_H__
5
+
#define __STEP_H__
6
+
7
+
#define STEP_ENUM_VAL(name) STEP_##name,
8
+
9
+
#define STEP_NAME_LIST(func) \
10
+
func(A0) \
11
+
func(A1) \
12
+
func(A2) \
13
+
func(A3) \
14
+
func(B0) \
15
+
func(B1) \
16
+
func(B2) \
17
+
func(B3) \
18
+
func(C0) \
19
+
func(C1) \
20
+
func(C2) \
21
+
func(C3) \
22
+
func(D0) \
23
+
func(D1) \
24
+
func(D2) \
25
+
func(D3) \
26
+
func(E0) \
27
+
func(E1) \
28
+
func(E2) \
29
+
func(E3) \
30
+
func(F0) \
31
+
func(F1) \
32
+
func(F2) \
33
+
func(F3) \
34
+
func(G0) \
35
+
func(G1) \
36
+
func(G2) \
37
+
func(G3) \
38
+
func(H0) \
39
+
func(H1) \
40
+
func(H2) \
41
+
func(H3) \
42
+
func(I0) \
43
+
func(I1) \
44
+
func(I2) \
45
+
func(I3) \
46
+
func(J0) \
47
+
func(J1) \
48
+
func(J2) \
49
+
func(J3)
50
+
51
+
/*
52
+
* Symbolic steppings that do not match the hardware. These are valid both as gt
53
+
* and display steppings as symbolic names.
54
+
*/
55
+
enum intel_step {
56
+
STEP_NONE = 0,
57
+
STEP_NAME_LIST(STEP_ENUM_VAL)
58
+
STEP_FUTURE,
59
+
STEP_FOREVER,
60
+
};
61
+
62
+
#endif /* __STEP_H__ */