Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: support imu for gfx11
Add support to initialize imu for gfx v11.
IMU is a new power management block for
gfx which manages gfx power.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Likun Gao
and committed by
Alex Deucher
289bcffb
18ee4ce6
+386
-1
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
···
30
30
#include "clearstate_defs.h"
31
31
#include "amdgpu_ring.h"
32
32
#include "amdgpu_rlc.h"
33
+
#include "amdgpu_imu.h"
33
34
#include "soc15.h"
34
35
#include "amdgpu_ras.h"
35
36
···
275
274
struct amdgpu_me me;
276
275
struct amdgpu_mec mec;
277
276
struct amdgpu_kiq kiq;
277
+
struct amdgpu_imu imu;
278
278
struct amdgpu_scratch scratch;
279
279
const struct firmware *me_fw; /* ME firmware */
280
280
uint32_t me_fw_version;
···
289
287
uint32_t mec_fw_version;
290
288
const struct firmware *mec2_fw; /* MEC2 firmware */
291
289
uint32_t mec2_fw_version;
290
+
const struct firmware *imu_fw; /* IMU firmware */
291
+
uint32_t imu_fw_version;
292
292
uint32_t me_feature_version;
293
293
uint32_t ce_feature_version;
294
294
uint32_t pfp_feature_version;
+51
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
+51
drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
···
1
+
/*
2
+
* Copyright 2021 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#ifndef __AMDGPU_IMU_H__
25
+
#define __AMDGPU_IMU_H__
26
+
27
+
struct amdgpu_imu_funcs {
28
+
int (*init_microcode)(struct amdgpu_device *adev);
29
+
int (*load_microcode)(struct amdgpu_device *adev);
30
+
void (*setup_imu)(struct amdgpu_device *adev);
31
+
int (*start_imu)(struct amdgpu_device *adev);
32
+
void (*program_rlc_ram)(struct amdgpu_device *adev);
33
+
};
34
+
35
+
struct imu_rlc_ram_golden {
36
+
u32 hwip;
37
+
u32 instance;
38
+
u32 segment;
39
+
u32 reg;
40
+
u32 data;
41
+
u32 addr_mask;
42
+
};
43
+
44
+
#define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \
45
+
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }
46
+
47
+
struct amdgpu_imu {
48
+
const struct amdgpu_imu_funcs *funcs;
49
+
};
50
+
51
+
#endif
+13
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+13
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
···
126
126
}
127
127
}
128
128
129
+
void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr)
130
+
{
131
+
uint16_t version_major = le16_to_cpu(hdr->header_version_major);
132
+
uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
133
+
134
+
DRM_DEBUG("IMU\n");
135
+
amdgpu_ucode_print_common_hdr(hdr);
136
+
137
+
if (version_major != 1) {
138
+
DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
139
+
}
140
+
}
141
+
129
142
void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
130
143
{
131
144
uint16_t version_major = le16_to_cpu(hdr->header_version_major);
+286
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+286
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
···
1
+
/*
2
+
* Copyright 2021 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#include <linux/firmware.h>
25
+
#include "amdgpu.h"
26
+
#include "amdgpu_imu.h"
27
+
28
+
#include "gc/gc_11_0_0_offset.h"
29
+
#include "gc/gc_11_0_0_sh_mask.h"
30
+
31
+
MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu.bin");
32
+
33
+
static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
34
+
{
35
+
char fw_name[40];
36
+
char ucode_prefix[30];
37
+
int err;
38
+
const struct imu_firmware_header_v1_0 *imu_hdr;
39
+
struct amdgpu_firmware_info *info = NULL;
40
+
41
+
DRM_DEBUG("\n");
42
+
43
+
amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
44
+
45
+
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_imu.bin", ucode_prefix);
46
+
err = request_firmware(&adev->gfx.imu_fw, fw_name, adev->dev);
47
+
if (err)
48
+
goto out;
49
+
err = amdgpu_ucode_validate(adev->gfx.imu_fw);
50
+
if (err)
51
+
goto out;
52
+
imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
53
+
adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);
54
+
//adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version);
55
+
56
+
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
57
+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I];
58
+
info->ucode_id = AMDGPU_UCODE_ID_IMU_I;
59
+
info->fw = adev->gfx.imu_fw;
60
+
adev->firmware.fw_size +=
61
+
ALIGN(le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes), PAGE_SIZE);
62
+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_D];
63
+
info->ucode_id = AMDGPU_UCODE_ID_IMU_D;
64
+
info->fw = adev->gfx.imu_fw;
65
+
adev->firmware.fw_size +=
66
+
ALIGN(le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes), PAGE_SIZE);
67
+
}
68
+
69
+
out:
70
+
if (err) {
71
+
dev_err(adev->dev,
72
+
"gfx11: Failed to load firmware \"%s\"\n",
73
+
fw_name);
74
+
release_firmware(adev->gfx.imu_fw);
75
+
}
76
+
77
+
return err;
78
+
}
79
+
80
+
static int imu_v11_0_load_microcode(struct amdgpu_device *adev)
81
+
{
82
+
const struct imu_firmware_header_v1_0 *hdr;
83
+
const __le32 *fw_data;
84
+
unsigned i, fw_size;
85
+
86
+
if (!adev->gfx.imu_fw)
87
+
return -EINVAL;
88
+
89
+
hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
90
+
//amdgpu_ucode_print_rlc_hdr(&hdr->header);
91
+
92
+
fw_data = (const __le32 *)(adev->gfx.imu_fw->data +
93
+
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
94
+
fw_size = le32_to_cpu(hdr->imu_iram_ucode_size_bytes) / 4;
95
+
96
+
WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0);
97
+
98
+
for (i = 0; i < fw_size; i++)
99
+
WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++));
100
+
101
+
WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version);
102
+
103
+
fw_data = (const __le32 *)(adev->gfx.imu_fw->data +
104
+
le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
105
+
le32_to_cpu(hdr->imu_iram_ucode_size_bytes));
106
+
fw_size = le32_to_cpu(hdr->imu_dram_ucode_size_bytes) / 4;
107
+
108
+
WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0);
109
+
110
+
for (i = 0; i < fw_size; i++)
111
+
WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++));
112
+
113
+
WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version);
114
+
115
+
return 0;
116
+
}
117
+
118
+
static void imu_v11_0_setup(struct amdgpu_device *adev)
119
+
{
120
+
int imu_reg_val;
121
+
122
+
//enable IMU debug mode
123
+
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
124
+
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
125
+
126
+
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
127
+
imu_reg_val |= 0x1;
128
+
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
129
+
130
+
//disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB
131
+
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);
132
+
imu_reg_val |= 0x10007;
133
+
WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val);
134
+
}
135
+
136
+
static int imu_v11_0_start(struct amdgpu_device *adev)
137
+
{
138
+
int imu_reg_val, i;
139
+
140
+
//Start IMU by set GFX_IMU_CORE_CTRL.CRESET = 0
141
+
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
142
+
imu_reg_val &= 0xfffffffe;
143
+
WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
144
+
145
+
for (i = 0; i < adev->usec_timeout; i++) {
146
+
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
147
+
if ((imu_reg_val & 0x1f) == 0x1f)
148
+
break;
149
+
udelay(1);
150
+
}
151
+
152
+
if (i >= adev->usec_timeout) {
153
+
dev_err(adev->dev, "init imu: IMU start timeout\n");
154
+
return -ETIMEDOUT;
155
+
}
156
+
157
+
return 0;
158
+
}
159
+
160
+
static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
161
+
{
162
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
163
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
164
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
165
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
166
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS , 0x003f3fff, 0xe0000000),
167
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
168
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
169
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
170
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000),
171
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000),
172
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC, 0x00000017, 0xe0000000),
173
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_ENABLE, 0x00000001, 0xe0000000),
174
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_CREDITS , 0x003f3fbf, 0xe0000000),
175
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE0, 0x10201000, 0xe0000000),
176
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE1, 0x00000080, 0xe0000000),
177
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE0, 0x1d041040, 0xe0000000),
178
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE1, 0x80000000, 0xe0000000),
179
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_IO_PRIORITY, 0x88888888, 0xe0000000),
180
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MAM_CTRL, 0x0000d800, 0xe0000000),
181
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ARB_FINAL, 0x000003f7, 0xe0000000),
182
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ENABLE, 0x00000001, 0xe0000000),
183
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
184
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000),
185
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0x000fffff, 0xe0000000),
186
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MISC, 0x0c48bff0, 0xe0000000),
187
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SA_UNIT_DISABLE, 0x00fffc01, 0xe0000000),
188
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_PRIM_CONFIG, 0x000fffe1, 0xe0000000),
189
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0x0fffff01, 0xe0000000),
190
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0xe0000000),
191
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0xe0000000),
192
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0xe0000000),
193
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0xe0000000),
194
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0xe0000000),
195
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x000fffff, 0xe0000000),
196
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000),
197
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0xe0000000),
198
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000),
199
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0xe0000000),
200
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x00000fff, 0xe0000000),
201
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
202
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000501, 0xe0000000),
203
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
204
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0xe0000000),
205
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
206
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0xe0000000),
207
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000),
208
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000),
209
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000001, 0xe0000000),
210
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000),
211
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000545, 0xe0000000),
212
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x13455431, 0xe0000000),
213
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_1, 0x13455431, 0xe0000000),
214
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x76027602, 0xe0000000),
215
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_3, 0x76207620, 0xe0000000),
216
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000345, 0xe0000000),
217
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCUTCL2_HARVEST_BYPASS_GROUPS, 0x0000003e, 0xe0000000),
218
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0xe0000000),
219
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x000061ff, 0xe0000000),
220
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000),
221
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0xe0000000),
222
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000),
223
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000),
224
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
225
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
226
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
227
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
228
+
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
229
+
};
230
+
231
+
void program_imu_rlc_ram(struct amdgpu_device *adev,
232
+
const struct imu_rlc_ram_golden *regs,
233
+
const u32 array_size)
234
+
{
235
+
const struct imu_rlc_ram_golden *entry;
236
+
u32 reg, data;
237
+
int i;
238
+
239
+
for (i = 0; i < array_size; ++i) {
240
+
entry = ®s[i];
241
+
reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
242
+
reg |= entry->addr_mask;
243
+
244
+
data = entry->data;
245
+
if (entry->reg == regGCMC_VM_AGP_BASE)
246
+
data = 0x00ffffff;
247
+
else if (entry->reg == regGCMC_VM_AGP_TOP)
248
+
data = 0x0;
249
+
else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE)
250
+
data = adev->gmc.vram_start >> 24;
251
+
else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP)
252
+
data = adev->gmc.vram_end >> 24;
253
+
254
+
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);
255
+
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg);
256
+
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);
257
+
}
258
+
//Indicate the latest entry
259
+
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);
260
+
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0);
261
+
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0);
262
+
}
263
+
264
+
static void imu_v11_0_program_rlc_ram(struct amdgpu_device *adev)
265
+
{
266
+
u32 reg_data;
267
+
268
+
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2);
269
+
270
+
program_imu_rlc_ram(adev,
271
+
imu_rlc_ram_golden_11,
272
+
(const u32)ARRAY_SIZE(imu_rlc_ram_golden_11));
273
+
274
+
//Indicate the contents of the RAM are valid
275
+
reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);
276
+
reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK;
277
+
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data);
278
+
}
279
+
280
+
const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = {
281
+
.init_microcode = imu_v11_0_init_microcode,
282
+
.load_microcode = imu_v11_0_load_microcode,
283
+
.setup_imu = imu_v11_0_setup,
284
+
.start_imu = imu_v11_0_start,
285
+
.program_rlc_ram = imu_v11_0_program_rlc_ram,
286
+
};
+30
drivers/gpu/drm/amd/amdgpu/imu_v11_0.h
+30
drivers/gpu/drm/amd/amdgpu/imu_v11_0.h
···
1
+
/*
2
+
* Copyright 2021 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#ifndef __IMU_V11_0_H__
25
+
#define __IMU_V11_0_H__
26
+
27
+
extern const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs;
28
+
29
+
#endif
30
+