Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-stmmac-dwmac-rk-add-gmac-support-for-rk3528'
Jonas Karlman says:
====================
net: stmmac: dwmac-rk: Add GMAC support for RK3528
The Rockchip RK3528 has two Ethernet controllers, one 100/10 MAC to be
used with the integrated PHY and a second 1000/100/10 MAC to be used
with an external Ethernet PHY.
This series add initial support for the Ethernet controllers found
in RK3528 and initial support to power up/down the integrated PHY.
v2: https://lore.kernel.org/20250309232622.1498084-1-jonas@kwiboo.se
v1: https://lore.kernel.org/20250306221402.1704196-1-jonas@kwiboo.se
====================
Link: https://patch.msgid.link/20250319214415.3086027-1-jonas@kwiboo.se
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+242
-51
+15
-1
Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
+15
-1
Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
···
24
24
- rockchip,rk3366-gmac
25
25
- rockchip,rk3368-gmac
26
26
- rockchip,rk3399-gmac
27
+
- rockchip,rk3528-gmac
27
28
- rockchip,rk3568-gmac
28
29
- rockchip,rk3576-gmac
29
30
- rockchip,rk3588-gmac
···
50
49
- rockchip,rv1108-gmac
51
50
- items:
52
51
- enum:
52
+
- rockchip,rk3528-gmac
53
53
- rockchip,rk3568-gmac
54
54
- rockchip,rk3576-gmac
55
55
- rockchip,rk3588-gmac
···
68
66
- const: eth_wake_irq
69
67
70
68
clocks:
71
-
minItems: 5
69
+
minItems: 4
72
70
maxItems: 8
73
71
74
72
clock-names:
···
141
139
else:
142
140
properties:
143
141
rockchip,php-grf: false
142
+
143
+
- if:
144
+
not:
145
+
properties:
146
+
compatible:
147
+
contains:
148
+
enum:
149
+
- rockchip,rk3528-gmac
150
+
then:
151
+
properties:
152
+
clocks:
153
+
minItems: 5
144
154
145
155
unevaluatedProperties: false
146
156
+227
-50
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+227
-50
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
···
33
33
void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
34
34
bool enable);
35
35
void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
36
+
void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv);
36
37
bool php_grf_required;
37
38
bool regs_valid;
38
39
u32 regs[];
···
92
91
#define DELAY_ENABLE(soc, tx, rx) \
93
92
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
94
93
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
94
+
95
+
#define RK_GRF_MACPHY_CON0 0xb00
96
+
#define RK_GRF_MACPHY_CON1 0xb04
97
+
#define RK_GRF_MACPHY_CON2 0xb08
98
+
#define RK_GRF_MACPHY_CON3 0xb0c
99
+
100
+
#define RK_MACPHY_ENABLE GRF_BIT(0)
101
+
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
102
+
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
103
+
#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
104
+
#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
105
+
#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
106
+
107
+
static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
108
+
{
109
+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
110
+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
111
+
112
+
regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
113
+
regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
114
+
115
+
if (priv->phy_reset) {
116
+
/* PHY needs to be disabled before trying to reset it */
117
+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
118
+
if (priv->phy_reset)
119
+
reset_control_assert(priv->phy_reset);
120
+
usleep_range(10, 20);
121
+
if (priv->phy_reset)
122
+
reset_control_deassert(priv->phy_reset);
123
+
usleep_range(10, 20);
124
+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
125
+
msleep(30);
126
+
}
127
+
}
128
+
129
+
static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
130
+
{
131
+
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
132
+
if (priv->phy_reset)
133
+
reset_control_assert(priv->phy_reset);
134
+
}
135
+
136
+
#define RK_FEPHY_SHUTDOWN GRF_BIT(1)
137
+
#define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
138
+
#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
139
+
#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9))
140
+
#define RK_FEPHY_PHY_ID GRF_BIT(11)
141
+
142
+
static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv,
143
+
unsigned int reg)
144
+
{
145
+
reset_control_assert(priv->phy_reset);
146
+
usleep_range(20, 30);
147
+
148
+
regmap_write(priv->grf, reg,
149
+
RK_FEPHY_POWERUP |
150
+
RK_FEPHY_INTERNAL_RMII_SEL |
151
+
RK_FEPHY_24M_CLK_SEL |
152
+
RK_FEPHY_PHY_ID);
153
+
usleep_range(10000, 12000);
154
+
155
+
reset_control_deassert(priv->phy_reset);
156
+
usleep_range(50000, 60000);
157
+
}
158
+
159
+
static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
160
+
unsigned int reg)
161
+
{
162
+
regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN);
163
+
}
95
164
96
165
#define PX30_GRF_GMAC_CON1 0x0904
97
166
···
395
324
{
396
325
regmap_write(priv->grf, RK3228_GRF_CON_MUX,
397
326
RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
327
+
328
+
rk_gmac_integrated_ephy_powerup(priv);
398
329
}
399
330
400
331
static const struct rk_gmac_ops rk3228_ops = {
···
404
331
.set_to_rmii = rk3228_set_to_rmii,
405
332
.set_rgmii_speed = rk3228_set_rgmii_speed,
406
333
.set_rmii_speed = rk3228_set_rmii_speed,
407
-
.integrated_phy_powerup = rk3228_integrated_phy_powerup,
334
+
.integrated_phy_powerup = rk3228_integrated_phy_powerup,
335
+
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
408
336
};
409
337
410
338
#define RK3288_GRF_SOC_CON1 0x0248
···
631
557
{
632
558
regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
633
559
RK3328_MACPHY_RMII_MODE);
560
+
561
+
rk_gmac_integrated_ephy_powerup(priv);
634
562
}
635
563
636
564
static const struct rk_gmac_ops rk3328_ops = {
···
640
564
.set_to_rmii = rk3328_set_to_rmii,
641
565
.set_rgmii_speed = rk3328_set_rgmii_speed,
642
566
.set_rmii_speed = rk3328_set_rmii_speed,
643
-
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
567
+
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
568
+
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
644
569
};
645
570
646
571
#define RK3366_GRF_SOC_CON6 0x0418
···
903
826
.set_to_rmii = rk3399_set_to_rmii,
904
827
.set_rgmii_speed = rk3399_set_rgmii_speed,
905
828
.set_rmii_speed = rk3399_set_rmii_speed,
829
+
};
830
+
831
+
#define RK3528_VO_GRF_GMAC_CON 0x0018
832
+
#define RK3528_VO_GRF_MACPHY_CON0 0x001c
833
+
#define RK3528_VO_GRF_MACPHY_CON1 0x0020
834
+
#define RK3528_VPU_GRF_GMAC_CON5 0x0018
835
+
#define RK3528_VPU_GRF_GMAC_CON6 0x001c
836
+
837
+
#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
838
+
#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
839
+
#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
840
+
#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
841
+
842
+
#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
843
+
#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
844
+
845
+
#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
846
+
#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
847
+
#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
848
+
849
+
#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
850
+
#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
851
+
852
+
#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
853
+
#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
854
+
#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
855
+
#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
856
+
857
+
#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
858
+
#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10))
859
+
#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10))
860
+
861
+
#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
862
+
#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
863
+
#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
864
+
#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
865
+
866
+
static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
867
+
int tx_delay, int rx_delay)
868
+
{
869
+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
870
+
RK3528_GMAC1_PHY_INTF_SEL_RGMII);
871
+
872
+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
873
+
DELAY_ENABLE(RK3528, tx_delay, rx_delay));
874
+
875
+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
876
+
RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
877
+
RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
878
+
}
879
+
880
+
static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
881
+
{
882
+
if (bsp_priv->id == 1)
883
+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
884
+
RK3528_GMAC1_PHY_INTF_SEL_RMII);
885
+
else
886
+
regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
887
+
RK3528_GMAC0_PHY_INTF_SEL_RMII |
888
+
RK3528_GMAC0_CLK_RMII_DIV2);
889
+
}
890
+
891
+
static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
892
+
{
893
+
struct device *dev = &bsp_priv->pdev->dev;
894
+
895
+
if (speed == 10)
896
+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
897
+
RK3528_GMAC1_CLK_RGMII_DIV50);
898
+
else if (speed == 100)
899
+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
900
+
RK3528_GMAC1_CLK_RGMII_DIV5);
901
+
else if (speed == 1000)
902
+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
903
+
RK3528_GMAC1_CLK_RGMII_DIV1);
904
+
else
905
+
dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
906
+
}
907
+
908
+
static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
909
+
{
910
+
struct device *dev = &bsp_priv->pdev->dev;
911
+
unsigned int reg, val;
912
+
913
+
if (speed == 10)
914
+
val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :
915
+
RK3528_GMAC0_CLK_RMII_DIV20;
916
+
else if (speed == 100)
917
+
val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :
918
+
RK3528_GMAC0_CLK_RMII_DIV2;
919
+
else {
920
+
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
921
+
return;
922
+
}
923
+
924
+
reg = bsp_priv->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :
925
+
RK3528_VO_GRF_GMAC_CON;
926
+
927
+
regmap_write(bsp_priv->grf, reg, val);
928
+
}
929
+
930
+
static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
931
+
bool input, bool enable)
932
+
{
933
+
unsigned int val;
934
+
935
+
if (bsp_priv->id == 1) {
936
+
val = input ? RK3528_GMAC1_CLK_SELECT_IO :
937
+
RK3528_GMAC1_CLK_SELECT_CRU;
938
+
val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
939
+
RK3528_GMAC1_CLK_RMII_GATE;
940
+
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
941
+
} else {
942
+
val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
943
+
RK3528_GMAC0_CLK_RMII_GATE;
944
+
regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val);
945
+
}
946
+
}
947
+
948
+
static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
949
+
{
950
+
rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
951
+
}
952
+
953
+
static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
954
+
{
955
+
rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
956
+
}
957
+
958
+
static const struct rk_gmac_ops rk3528_ops = {
959
+
.set_to_rgmii = rk3528_set_to_rgmii,
960
+
.set_to_rmii = rk3528_set_to_rmii,
961
+
.set_rgmii_speed = rk3528_set_rgmii_speed,
962
+
.set_rmii_speed = rk3528_set_rmii_speed,
963
+
.set_clock_selection = rk3528_set_clock_selection,
964
+
.integrated_phy_powerup = rk3528_integrated_phy_powerup,
965
+
.integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
966
+
.regs_valid = true,
967
+
.regs = {
968
+
0xffbd0000, /* gmac0 */
969
+
0xffbe0000, /* gmac1 */
970
+
0x0, /* sentinel */
971
+
},
906
972
};
907
973
908
974
#define RK3568_GRF_GMAC0_CON0 0x0380
···
1552
1332
.set_rmii_speed = rv1126_set_rmii_speed,
1553
1333
};
1554
1334
1555
-
#define RK_GRF_MACPHY_CON0 0xb00
1556
-
#define RK_GRF_MACPHY_CON1 0xb04
1557
-
#define RK_GRF_MACPHY_CON2 0xb08
1558
-
#define RK_GRF_MACPHY_CON3 0xb0c
1559
-
1560
-
#define RK_MACPHY_ENABLE GRF_BIT(0)
1561
-
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
1562
-
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
1563
-
#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
1564
-
#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
1565
-
#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
1566
-
1567
-
static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1568
-
{
1569
-
if (priv->ops->integrated_phy_powerup)
1570
-
priv->ops->integrated_phy_powerup(priv);
1571
-
1572
-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1573
-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1574
-
1575
-
regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1576
-
regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1577
-
1578
-
if (priv->phy_reset) {
1579
-
/* PHY needs to be disabled before trying to reset it */
1580
-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1581
-
if (priv->phy_reset)
1582
-
reset_control_assert(priv->phy_reset);
1583
-
usleep_range(10, 20);
1584
-
if (priv->phy_reset)
1585
-
reset_control_deassert(priv->phy_reset);
1586
-
usleep_range(10, 20);
1587
-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1588
-
msleep(30);
1589
-
}
1590
-
}
1591
-
1592
-
static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1593
-
{
1594
-
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1595
-
if (priv->phy_reset)
1596
-
reset_control_assert(priv->phy_reset);
1597
-
}
1598
-
1599
1335
static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1600
1336
{
1601
1337
struct rk_priv_data *bsp_priv = plat->bsp_priv;
···
1847
1671
1848
1672
pm_runtime_get_sync(dev);
1849
1673
1850
-
if (bsp_priv->integrated_phy)
1851
-
rk_gmac_integrated_phy_powerup(bsp_priv);
1674
+
if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup)
1675
+
bsp_priv->ops->integrated_phy_powerup(bsp_priv);
1852
1676
1853
1677
return 0;
1854
1678
}
1855
1679
1856
1680
static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1857
1681
{
1858
-
if (gmac->integrated_phy)
1859
-
rk_gmac_integrated_phy_powerdown(gmac);
1682
+
if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown)
1683
+
gmac->ops->integrated_phy_powerdown(gmac);
1860
1684
1861
1685
pm_runtime_put_sync(&gmac->pdev->dev);
1862
1686
···
1995
1819
{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1996
1820
{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1997
1821
{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1822
+
{ .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
1998
1823
{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
1999
1824
{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
2000
1825
{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },