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clk: renesas: r9a08g045: Add clock and reset support for watchdog

RZ/G3S has a watchdog module accessible by the Cortex-A core. Add clock
and reset support for it.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240122111115.2861835-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Claudiu Beznea and committed by
Geert Uytterhoeven 292d3079 4ae2c995

+3
+3
drivers/clk/renesas/r9a08g045-cpg.c
··· 193 193 DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0), 194 194 DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), 195 195 DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), 196 + DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0), 197 + DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1), 196 198 DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), 197 199 DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), 198 200 DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2), ··· 221 219 DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), 222 220 DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), 223 221 DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0), 222 + DEF_RST(R9A08G045_WDT0_PRESETN, 0x848, 0), 224 223 DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), 225 224 DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), 226 225 DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),