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phy: phy-rockchip-samsung-hdptx: Swap the definitions of LCPLL_REF and ROPLL_REF

According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097)
to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0
selects the ROPLL.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250205105157.580060-2-damon.ding@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Damon Ding and committed by
Vinod Koul 2947c806 27995020

+2 -2
+2 -2
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
··· 94 94 #define LCPLL_ALONE_MODE BIT(1) 95 95 /* CMN_REG(0097) */ 96 96 #define DIG_CLK_SEL BIT(1) 97 - #define ROPLL_REF BIT(1) 98 - #define LCPLL_REF 0 97 + #define LCPLL_REF BIT(1) 98 + #define ROPLL_REF 0 99 99 /* CMN_REG(0099) */ 100 100 #define CMN_ROPLL_ALONE_MODE BIT(2) 101 101 #define ROPLL_ALONE_MODE BIT(2)