Merge branch 'i2c/for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

+37

Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt

··· 1 + Broadcom iProc I2C controller 2 + 3 + Required properties: 4 + 5 + - compatible: 6 + Must be "brcm,iproc-i2c" 7 + 8 + - reg: 9 + Define the base and range of the I/O address space that contain the iProc 10 + I2C controller registers 11 + 12 + - interrupts: 13 + Should contain the I2C interrupt 14 + 15 + - clock-frequency: 16 + This is the I2C bus clock. Need to be either 100000 or 400000 17 + 18 + - #address-cells: 19 + Always 1 (for I2C addresses) 20 + 21 + - #size-cells: 22 + Always 0 23 + 24 + Example: 25 + i2c0: i2c@18008000 { 26 + compatible = "brcm,iproc-i2c"; 27 + reg = <0x18008000 0x100>; 28 + #address-cells = <1>; 29 + #size-cells = <0>; 30 + interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; 31 + clock-frequency = <100000>; 32 + 33 + codec: wm8750@1a { 34 + compatible = "wlf,wm8750"; 35 + reg = <0x1a>; 36 + }; 37 + };

+3

Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt

··· 16 16 Optional Properties: 17 17 18 18 - reset-gpios: Reference to the GPIO connected to the reset input. 19 + - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all 20 + children in idle state. This is necessary for example, if there are several 21 + multiplexers on the bus and the devices behind them use same I2C addresses. 19 22 20 23 21 24 Example:

+39 -3

Documentation/devicetree/bindings/i2c/i2c-ocores.txt

··· 4 4 - compatible : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst" 5 5 - reg : bus address start and address range size of device 6 6 - interrupts : interrupt number 7 - - clock-frequency : frequency of bus clock in Hz 7 + - clocks : handle to the controller clock; see the note below. 8 + Mutually exclusive with opencores,ip-clock-frequency 9 + - opencores,ip-clock-frequency: frequency of the controller clock in Hz; 10 + see the note below. Mutually exclusive with clocks 8 11 - #address-cells : should be <1> 9 12 - #size-cells : should be <0> 10 13 11 14 Optional properties: 15 + - clock-frequency : frequency of bus clock in Hz; see the note below. 16 + Defaults to 100 KHz when the property is not specified 12 17 - reg-shift : device register offsets are shifted by this value 13 18 - reg-io-width : io register width in bytes (1, 2 or 4) 14 19 - regstep : deprecated, use reg-shift above 15 20 16 - Example: 21 + Note 22 + clock-frequency property is meant to control the bus frequency for i2c bus 23 + drivers, but it was incorrectly used to specify i2c controller input clock 24 + frequency. So the following rules are set to fix this situation: 25 + - if clock-frequency is present and neither opencores,ip-clock-frequency nor 26 + clocks are, then clock-frequency specifies i2c controller clock frequency. 27 + This is to keep backwards compatibility with setups using old DTB. i2c bus 28 + frequency is fixed at 100 KHz. 29 + - if clocks is present it specifies i2c controller clock. clock-frequency 30 + property specifies i2c bus frequency. 31 + - if opencores,ip-clock-frequency is present it specifies i2c controller 32 + clock frequency. clock-frequency property specifies i2c bus frequency. 33 + 34 + Examples: 17 35 18 36 i2c0: ocores@a0000000 { 19 37 #address-cells = <1>; ··· 39 21 compatible = "opencores,i2c-ocores"; 40 22 reg = <0xa0000000 0x8>; 41 23 interrupts = <10>; 42 - clock-frequency = <20000000>; 24 + opencores,ip-clock-frequency = <20000000>; 25 + 26 + reg-shift = <0>; /* 8 bit registers */ 27 + reg-io-width = <1>; /* 8 bit read/write */ 28 + 29 + dummy@60 { 30 + compatible = "dummy"; 31 + reg = <0x60>; 32 + }; 33 + }; 34 + or 35 + i2c0: ocores@a0000000 { 36 + #address-cells = <1>; 37 + #size-cells = <0>; 38 + compatible = "opencores,i2c-ocores"; 39 + reg = <0xa0000000 0x8>; 40 + interrupts = <10>; 41 + clocks = <&osc>; 42 + clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ 43 43 44 44 reg-shift = <0>; /* 8 bit registers */ 45 45 reg-io-width = <1>; /* 8 bit read/write */

+14

Documentation/devicetree/bindings/i2c/i2c-rk3x.txt

··· 21 21 Optional properties : 22 22 23 23 - clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used. 24 + - i2c-scl-rising-time-ns : Number of nanoseconds the SCL signal takes to rise 25 + (t(r) in I2C specification). If not specified this is assumed to be 26 + the maximum the specification allows(1000 ns for Standard-mode, 27 + 300 ns for Fast-mode) which might cause slightly slower communication. 28 + - i2c-scl-falling-time-ns : Number of nanoseconds the SCL signal takes to fall 29 + (t(f) in the I2C specification). If not specified this is assumed to 30 + be the maximum the specification allows (300 ns) which might cause 31 + slightly slower communication. 32 + - i2c-sda-falling-time-ns : Number of nanoseconds the SDA signal takes to fall 33 + (t(f) in the I2C specification). If not specified we'll use the SCL 34 + value since they are the same in nearly all cases. 24 35 25 36 Example: 26 37 ··· 50 39 51 40 clock-names = "i2c"; 52 41 clocks = <&cru PCLK_I2C0>; 42 + 43 + i2c-scl-rising-time-ns = <800>; 44 + i2c-scl-falling-time-ns = <100>; 53 45 };

+2 -3

Documentation/devicetree/bindings/i2c/trivial-devices.txt

··· 61 61 gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface 62 62 infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) 63 63 infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) 64 - isl,isl12057 Intersil ISL12057 I2C RTC Chip 65 - isil,isl29028 (deprecated, use isl) 66 - isl,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor 64 + isil,isl12057 Intersil ISL12057 I2C RTC Chip 65 + isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor 67 66 maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator 68 67 maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs 69 68 maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface

+1 -1

Documentation/i2c/functionality

··· 12 12 ----------------------- 13 13 14 14 For the most up-to-date list of functionality constants, please check 15 - <linux/i2c.h>! 15 + <uapi/linux/i2c.h>! 16 16 17 17 I2C_FUNC_I2C Plain i2c-level commands (Pure SMBus 18 18 adapters typically can not do these)

+21 -1

drivers/i2c/busses/Kconfig

··· 79 79 80 80 config I2C_HIX5HD2 81 81 tristate "Hix5hd2 high-speed I2C driver" 82 - depends on ARCH_HIX5HD2 82 + depends on ARCH_HIX5HD2 || COMPILE_TEST 83 83 help 84 84 Say Y here to include support for high-speed I2C controller in the 85 85 Hisilicon based hix5hd2 SoCs. ··· 372 372 This support is also available as a module. If so, the module 373 373 will be called i2c-bcm2835. 374 374 375 + config I2C_BCM_IPROC 376 + tristate "Broadcom iProc I2C controller" 377 + depends on ARCH_BCM_IPROC || COMPILE_TEST 378 + default ARCH_BCM_IPROC 379 + help 380 + If you say yes to this option, support will be included for the 381 + Broadcom iProc I2C controller. 382 + 383 + If you don't know what to do here, say N. 384 + 375 385 config I2C_BCM_KONA 376 386 tristate "BCM Kona I2C adapter" 377 387 depends on ARCH_BCM_MOBILE ··· 474 464 475 465 This driver can also be built as a module. If so, the module 476 466 will be called i2c-designware-pci. 467 + 468 + config I2C_DESIGNWARE_BAYTRAIL 469 + bool "Intel Baytrail I2C semaphore support" 470 + depends on I2C_DESIGNWARE_PLATFORM && IOSF_MBI=y && ACPI 471 + help 472 + This driver enables managed host access to the PMIC I2C bus on select 473 + Intel BayTrail platforms using the X-Powers AXP288 PMIC. It allows 474 + the host to request uninterrupted access to the PMIC's I2C bus from 475 + the platform firmware controlling it. You should say Y if running on 476 + a BayTrail system using the AXP288. 477 477 478 478 config I2C_EFM32 479 479 tristate "EFM32 I2C controller"

+2

drivers/i2c/busses/Makefile

··· 33 33 obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o 34 34 obj-$(CONFIG_I2C_AXXIA) += i2c-axxia.o 35 35 obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o 36 + obj-$(CONFIG_I2C_BCM_IPROC) += i2c-bcm-iproc.o 36 37 obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o 37 38 obj-$(CONFIG_I2C_CADENCE) += i2c-cadence.o 38 39 obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o ··· 42 41 obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o 43 42 obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o 44 43 i2c-designware-platform-objs := i2c-designware-platdrv.o 44 + i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_BAYTRAIL) += i2c-designware-baytrail.o 45 45 obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o 46 46 i2c-designware-pci-objs := i2c-designware-pcidrv.o 47 47 obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o

+461

drivers/i2c/busses/i2c-bcm-iproc.c

··· 1 + /* 2 + * Copyright (C) 2014 Broadcom Corporation 3 + * 4 + * This program is free software; you can redistribute it and/or 5 + * modify it under the terms of the GNU General Public License as 6 + * published by the Free Software Foundation version 2. 7 + * 8 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 + * kind, whether express or implied; without even the implied warranty 10 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 + * GNU General Public License for more details. 12 + */ 13 + 14 + #include <linux/delay.h> 15 + #include <linux/i2c.h> 16 + #include <linux/interrupt.h> 17 + #include <linux/io.h> 18 + #include <linux/kernel.h> 19 + #include <linux/module.h> 20 + #include <linux/platform_device.h> 21 + #include <linux/slab.h> 22 + 23 + #define CFG_OFFSET 0x00 24 + #define CFG_RESET_SHIFT 31 25 + #define CFG_EN_SHIFT 30 26 + #define CFG_M_RETRY_CNT_SHIFT 16 27 + #define CFG_M_RETRY_CNT_MASK 0x0f 28 + 29 + #define TIM_CFG_OFFSET 0x04 30 + #define TIM_CFG_MODE_400_SHIFT 31 31 + 32 + #define M_FIFO_CTRL_OFFSET 0x0c 33 + #define M_FIFO_RX_FLUSH_SHIFT 31 34 + #define M_FIFO_TX_FLUSH_SHIFT 30 35 + #define M_FIFO_RX_CNT_SHIFT 16 36 + #define M_FIFO_RX_CNT_MASK 0x7f 37 + #define M_FIFO_RX_THLD_SHIFT 8 38 + #define M_FIFO_RX_THLD_MASK 0x3f 39 + 40 + #define M_CMD_OFFSET 0x30 41 + #define M_CMD_START_BUSY_SHIFT 31 42 + #define M_CMD_STATUS_SHIFT 25 43 + #define M_CMD_STATUS_MASK 0x07 44 + #define M_CMD_STATUS_SUCCESS 0x0 45 + #define M_CMD_STATUS_LOST_ARB 0x1 46 + #define M_CMD_STATUS_NACK_ADDR 0x2 47 + #define M_CMD_STATUS_NACK_DATA 0x3 48 + #define M_CMD_STATUS_TIMEOUT 0x4 49 + #define M_CMD_PROTOCOL_SHIFT 9 50 + #define M_CMD_PROTOCOL_MASK 0xf 51 + #define M_CMD_PROTOCOL_BLK_WR 0x7 52 + #define M_CMD_PROTOCOL_BLK_RD 0x8 53 + #define M_CMD_PEC_SHIFT 8 54 + #define M_CMD_RD_CNT_SHIFT 0 55 + #define M_CMD_RD_CNT_MASK 0xff 56 + 57 + #define IE_OFFSET 0x38 58 + #define IE_M_RX_FIFO_FULL_SHIFT 31 59 + #define IE_M_RX_THLD_SHIFT 30 60 + #define IE_M_START_BUSY_SHIFT 28 61 + 62 + #define IS_OFFSET 0x3c 63 + #define IS_M_RX_FIFO_FULL_SHIFT 31 64 + #define IS_M_RX_THLD_SHIFT 30 65 + #define IS_M_START_BUSY_SHIFT 28 66 + 67 + #define M_TX_OFFSET 0x40 68 + #define M_TX_WR_STATUS_SHIFT 31 69 + #define M_TX_DATA_SHIFT 0 70 + #define M_TX_DATA_MASK 0xff 71 + 72 + #define M_RX_OFFSET 0x44 73 + #define M_RX_STATUS_SHIFT 30 74 + #define M_RX_STATUS_MASK 0x03 75 + #define M_RX_PEC_ERR_SHIFT 29 76 + #define M_RX_DATA_SHIFT 0 77 + #define M_RX_DATA_MASK 0xff 78 + 79 + #define I2C_TIMEOUT_MESC 100 80 + #define M_TX_RX_FIFO_SIZE 64 81 + 82 + enum bus_speed_index { 83 + I2C_SPD_100K = 0, 84 + I2C_SPD_400K, 85 + }; 86 + 87 + struct bcm_iproc_i2c_dev { 88 + struct device *device; 89 + int irq; 90 + 91 + void __iomem *base; 92 + 93 + struct i2c_adapter adapter; 94 + 95 + struct completion done; 96 + int xfer_is_done; 97 + }; 98 + 99 + /* 100 + * Can be expanded in the future if more interrupt status bits are utilized 101 + */ 102 + #define ISR_MASK (1 << IS_M_START_BUSY_SHIFT) 103 + 104 + static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) 105 + { 106 + struct bcm_iproc_i2c_dev *iproc_i2c = data; 107 + u32 status = readl(iproc_i2c->base + IS_OFFSET); 108 + 109 + status &= ISR_MASK; 110 + 111 + if (!status) 112 + return IRQ_NONE; 113 + 114 + writel(status, iproc_i2c->base + IS_OFFSET); 115 + iproc_i2c->xfer_is_done = 1; 116 + complete_all(&iproc_i2c->done); 117 + 118 + return IRQ_HANDLED; 119 + } 120 + 121 + static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, 122 + struct i2c_msg *msg) 123 + { 124 + u32 val; 125 + 126 + val = readl(iproc_i2c->base + M_CMD_OFFSET); 127 + val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK; 128 + 129 + switch (val) { 130 + case M_CMD_STATUS_SUCCESS: 131 + return 0; 132 + 133 + case M_CMD_STATUS_LOST_ARB: 134 + dev_dbg(iproc_i2c->device, "lost bus arbitration\n"); 135 + return -EAGAIN; 136 + 137 + case M_CMD_STATUS_NACK_ADDR: 138 + dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr); 139 + return -ENXIO; 140 + 141 + case M_CMD_STATUS_NACK_DATA: 142 + dev_dbg(iproc_i2c->device, "NAK data\n"); 143 + return -ENXIO; 144 + 145 + case M_CMD_STATUS_TIMEOUT: 146 + dev_dbg(iproc_i2c->device, "bus timeout\n"); 147 + return -ETIMEDOUT; 148 + 149 + default: 150 + dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val); 151 + return -EIO; 152 + } 153 + } 154 + 155 + static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, 156 + struct i2c_msg *msg) 157 + { 158 + int ret, i; 159 + u8 addr; 160 + u32 val; 161 + unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MESC); 162 + 163 + /* need to reserve one byte in the FIFO for the slave address */ 164 + if (msg->len > M_TX_RX_FIFO_SIZE - 1) { 165 + dev_err(iproc_i2c->device, 166 + "only support data length up to %u bytes\n", 167 + M_TX_RX_FIFO_SIZE - 1); 168 + return -EOPNOTSUPP; 169 + } 170 + 171 + /* check if bus is busy */ 172 + if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) & 173 + BIT(M_CMD_START_BUSY_SHIFT))) { 174 + dev_warn(iproc_i2c->device, "bus is busy\n"); 175 + return -EBUSY; 176 + } 177 + 178 + /* format and load slave address into the TX FIFO */ 179 + addr = msg->addr << 1 | (msg->flags & I2C_M_RD ? 1 : 0); 180 + writel(addr, iproc_i2c->base + M_TX_OFFSET); 181 + 182 + /* for a write transaction, load data into the TX FIFO */ 183 + if (!(msg->flags & I2C_M_RD)) { 184 + for (i = 0; i < msg->len; i++) { 185 + val = msg->buf[i]; 186 + 187 + /* mark the last byte */ 188 + if (i == msg->len - 1) 189 + val |= 1 << M_TX_WR_STATUS_SHIFT; 190 + 191 + writel(val, iproc_i2c->base + M_TX_OFFSET); 192 + } 193 + } 194 + 195 + /* mark as incomplete before starting the transaction */ 196 + reinit_completion(&iproc_i2c->done); 197 + iproc_i2c->xfer_is_done = 0; 198 + 199 + /* 200 + * Enable the "start busy" interrupt, which will be triggered after the 201 + * transaction is done, i.e., the internal start_busy bit, transitions 202 + * from 1 to 0. 203 + */ 204 + writel(1 << IE_M_START_BUSY_SHIFT, iproc_i2c->base + IE_OFFSET); 205 + 206 + /* 207 + * Now we can activate the transfer. For a read operation, specify the 208 + * number of bytes to read 209 + */ 210 + val = 1 << M_CMD_START_BUSY_SHIFT; 211 + if (msg->flags & I2C_M_RD) { 212 + val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) | 213 + (msg->len << M_CMD_RD_CNT_SHIFT); 214 + } else { 215 + val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); 216 + } 217 + writel(val, iproc_i2c->base + M_CMD_OFFSET); 218 + 219 + time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left); 220 + 221 + /* disable all interrupts */ 222 + writel(0, iproc_i2c->base + IE_OFFSET); 223 + /* read it back to flush the write */ 224 + readl(iproc_i2c->base + IE_OFFSET); 225 + 226 + /* make sure the interrupt handler isn't running */ 227 + synchronize_irq(iproc_i2c->irq); 228 + 229 + if (!time_left && !iproc_i2c->xfer_is_done) { 230 + dev_err(iproc_i2c->device, "transaction timed out\n"); 231 + 232 + /* flush FIFOs */ 233 + val = (1 << M_FIFO_RX_FLUSH_SHIFT) | 234 + (1 << M_FIFO_TX_FLUSH_SHIFT); 235 + writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); 236 + return -ETIMEDOUT; 237 + } 238 + 239 + ret = bcm_iproc_i2c_check_status(iproc_i2c, msg); 240 + if (ret) { 241 + /* flush both TX/RX FIFOs */ 242 + val = (1 << M_FIFO_RX_FLUSH_SHIFT) | 243 + (1 << M_FIFO_TX_FLUSH_SHIFT); 244 + writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); 245 + return ret; 246 + } 247 + 248 + /* 249 + * For a read operation, we now need to load the data from FIFO 250 + * into the memory buffer 251 + */ 252 + if (msg->flags & I2C_M_RD) { 253 + for (i = 0; i < msg->len; i++) { 254 + msg->buf[i] = (readl(iproc_i2c->base + M_RX_OFFSET) >> 255 + M_RX_DATA_SHIFT) & M_RX_DATA_MASK; 256 + } 257 + } 258 + 259 + return 0; 260 + } 261 + 262 + static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, 263 + struct i2c_msg msgs[], int num) 264 + { 265 + struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter); 266 + int ret, i; 267 + 268 + /* go through all messages */ 269 + for (i = 0; i < num; i++) { 270 + ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]); 271 + if (ret) { 272 + dev_dbg(iproc_i2c->device, "xfer failed\n"); 273 + return ret; 274 + } 275 + } 276 + 277 + return num; 278 + } 279 + 280 + static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) 281 + { 282 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 283 + } 284 + 285 + static const struct i2c_algorithm bcm_iproc_algo = { 286 + .master_xfer = bcm_iproc_i2c_xfer, 287 + .functionality = bcm_iproc_i2c_functionality, 288 + }; 289 + 290 + static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) 291 + { 292 + unsigned int bus_speed; 293 + u32 val; 294 + int ret = of_property_read_u32(iproc_i2c->device->of_node, 295 + "clock-frequency", &bus_speed); 296 + if (ret < 0) { 297 + dev_info(iproc_i2c->device, 298 + "unable to interpret clock-frequency DT property\n"); 299 + bus_speed = 100000; 300 + } 301 + 302 + if (bus_speed < 100000) { 303 + dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n", 304 + bus_speed); 305 + dev_err(iproc_i2c->device, 306 + "valid speeds are 100khz and 400khz\n"); 307 + return -EINVAL; 308 + } else if (bus_speed < 400000) { 309 + bus_speed = 100000; 310 + } else { 311 + bus_speed = 400000; 312 + } 313 + 314 + val = readl(iproc_i2c->base + TIM_CFG_OFFSET); 315 + val &= ~(1 << TIM_CFG_MODE_400_SHIFT); 316 + val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; 317 + writel(val, iproc_i2c->base + TIM_CFG_OFFSET); 318 + 319 + dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed); 320 + 321 + return 0; 322 + } 323 + 324 + static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) 325 + { 326 + u32 val; 327 + 328 + /* put controller in reset */ 329 + val = readl(iproc_i2c->base + CFG_OFFSET); 330 + val |= 1 << CFG_RESET_SHIFT; 331 + val &= ~(1 << CFG_EN_SHIFT); 332 + writel(val, iproc_i2c->base + CFG_OFFSET); 333 + 334 + /* wait 100 usec per spec */ 335 + udelay(100); 336 + 337 + /* bring controller out of reset */ 338 + val &= ~(1 << CFG_RESET_SHIFT); 339 + writel(val, iproc_i2c->base + CFG_OFFSET); 340 + 341 + /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ 342 + val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT); 343 + writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); 344 + 345 + /* disable all interrupts */ 346 + writel(0, iproc_i2c->base + IE_OFFSET); 347 + 348 + /* clear all pending interrupts */ 349 + writel(0xffffffff, iproc_i2c->base + IS_OFFSET); 350 + 351 + return 0; 352 + } 353 + 354 + static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, 355 + bool enable) 356 + { 357 + u32 val; 358 + 359 + val = readl(iproc_i2c->base + CFG_OFFSET); 360 + if (enable) 361 + val |= BIT(CFG_EN_SHIFT); 362 + else 363 + val &= ~BIT(CFG_EN_SHIFT); 364 + writel(val, iproc_i2c->base + CFG_OFFSET); 365 + } 366 + 367 + static int bcm_iproc_i2c_probe(struct platform_device *pdev) 368 + { 369 + int irq, ret = 0; 370 + struct bcm_iproc_i2c_dev *iproc_i2c; 371 + struct i2c_adapter *adap; 372 + struct resource *res; 373 + 374 + iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c), 375 + GFP_KERNEL); 376 + if (!iproc_i2c) 377 + return -ENOMEM; 378 + 379 + platform_set_drvdata(pdev, iproc_i2c); 380 + iproc_i2c->device = &pdev->dev; 381 + init_completion(&iproc_i2c->done); 382 + 383 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 384 + iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res); 385 + if (IS_ERR(iproc_i2c->base)) 386 + return PTR_ERR(iproc_i2c->base); 387 + 388 + ret = bcm_iproc_i2c_init(iproc_i2c); 389 + if (ret) 390 + return ret; 391 + 392 + ret = bcm_iproc_i2c_cfg_speed(iproc_i2c); 393 + if (ret) 394 + return ret; 395 + 396 + irq = platform_get_irq(pdev, 0); 397 + if (irq <= 0) { 398 + dev_err(iproc_i2c->device, "no irq resource\n"); 399 + return irq; 400 + } 401 + iproc_i2c->irq = irq; 402 + 403 + ret = devm_request_irq(iproc_i2c->device, irq, bcm_iproc_i2c_isr, 0, 404 + pdev->name, iproc_i2c); 405 + if (ret < 0) { 406 + dev_err(iproc_i2c->device, "unable to request irq %i\n", irq); 407 + return ret; 408 + } 409 + 410 + bcm_iproc_i2c_enable_disable(iproc_i2c, true); 411 + 412 + adap = &iproc_i2c->adapter; 413 + i2c_set_adapdata(adap, iproc_i2c); 414 + strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name)); 415 + adap->algo = &bcm_iproc_algo; 416 + adap->dev.parent = &pdev->dev; 417 + adap->dev.of_node = pdev->dev.of_node; 418 + 419 + ret = i2c_add_adapter(adap); 420 + if (ret) { 421 + dev_err(iproc_i2c->device, "failed to add adapter\n"); 422 + return ret; 423 + } 424 + 425 + return 0; 426 + } 427 + 428 + static int bcm_iproc_i2c_remove(struct platform_device *pdev) 429 + { 430 + struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); 431 + 432 + /* make sure there's no pending interrupt when we remove the adapter */ 433 + writel(0, iproc_i2c->base + IE_OFFSET); 434 + readl(iproc_i2c->base + IE_OFFSET); 435 + synchronize_irq(iproc_i2c->irq); 436 + 437 + i2c_del_adapter(&iproc_i2c->adapter); 438 + bcm_iproc_i2c_enable_disable(iproc_i2c, false); 439 + 440 + return 0; 441 + } 442 + 443 + static const struct of_device_id bcm_iproc_i2c_of_match[] = { 444 + { .compatible = "brcm,iproc-i2c" }, 445 + { /* sentinel */ } 446 + }; 447 + MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match); 448 + 449 + static struct platform_driver bcm_iproc_i2c_driver = { 450 + .driver = { 451 + .name = "bcm-iproc-i2c", 452 + .of_match_table = bcm_iproc_i2c_of_match, 453 + }, 454 + .probe = bcm_iproc_i2c_probe, 455 + .remove = bcm_iproc_i2c_remove, 456 + }; 457 + module_platform_driver(bcm_iproc_i2c_driver); 458 + 459 + MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); 460 + MODULE_DESCRIPTION("Broadcom iProc I2C Driver"); 461 + MODULE_LICENSE("GPL v2");

+116 -73

drivers/i2c/busses/i2c-cadence.c

··· 128 128 * @suspended: Flag holding the device's PM status 129 129 * @send_count: Number of bytes still expected to send 130 130 * @recv_count: Number of bytes still expected to receive 131 + * @curr_recv_count: Number of bytes to be received in current transfer 131 132 * @irq: IRQ number 132 133 * @input_clk: Input clock to I2C controller 133 134 * @i2c_clk: Maximum I2C clock speed ··· 147 146 u8 suspended; 148 147 unsigned int send_count; 149 148 unsigned int recv_count; 149 + unsigned int curr_recv_count; 150 150 int irq; 151 151 unsigned long input_clk; 152 152 unsigned int i2c_clk; ··· 184 182 */ 185 183 static irqreturn_t cdns_i2c_isr(int irq, void *ptr) 186 184 { 187 - unsigned int isr_status, avail_bytes; 188 - unsigned int bytes_to_recv, bytes_to_send; 185 + unsigned int isr_status, avail_bytes, updatetx; 186 + unsigned int bytes_to_send; 189 187 struct cdns_i2c *id = ptr; 190 188 /* Signal completion only after everything is updated */ 191 189 int done_flag = 0; 192 190 irqreturn_t status = IRQ_NONE; 193 191 194 192 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 193 + cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 195 194 196 195 /* Handling nack and arbitration lost interrupt */ 197 196 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { ··· 200 197 status = IRQ_HANDLED; 201 198 } 202 199 203 - /* Handling Data interrupt */ 204 - if ((isr_status & CDNS_I2C_IXR_DATA) && 205 - (id->recv_count >= CDNS_I2C_DATA_INTR_DEPTH)) { 206 - /* Always read data interrupt threshold bytes */ 207 - bytes_to_recv = CDNS_I2C_DATA_INTR_DEPTH; 208 - id->recv_count -= CDNS_I2C_DATA_INTR_DEPTH; 209 - avail_bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 200 + /* 201 + * Check if transfer size register needs to be updated again for a 202 + * large data receive operation. 203 + */ 204 + updatetx = 0; 205 + if (id->recv_count > id->curr_recv_count) 206 + updatetx = 1; 210 207 211 - /* 212 - * if the tranfer size register value is zero, then 213 - * check for the remaining bytes and update the 214 - * transfer size register. 215 - */ 216 - if (!avail_bytes) { 217 - if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) 218 - cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 219 - CDNS_I2C_XFER_SIZE_OFFSET); 220 - else 221 - cdns_i2c_writereg(id->recv_count, 222 - CDNS_I2C_XFER_SIZE_OFFSET); 223 - } 208 + /* When receiving, handle data interrupt and completion interrupt */ 209 + if (id->p_recv_buf && 210 + ((isr_status & CDNS_I2C_IXR_COMP) || 211 + (isr_status & CDNS_I2C_IXR_DATA))) { 212 + /* Read data if receive data valid is set */ 213 + while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & 214 + CDNS_I2C_SR_RXDV) { 215 + /* 216 + * Clear hold bit that was set for FIFO control if 217 + * RX data left is less than FIFO depth, unless 218 + * repeated start is selected. 219 + */ 220 + if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) && 221 + !id->bus_hold_flag) 222 + cdns_i2c_clear_bus_hold(id); 224 223 225 - /* Process the data received */ 226 - while (bytes_to_recv--) 227 224 *(id->p_recv_buf)++ = 228 225 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 226 + id->recv_count--; 227 + id->curr_recv_count--; 229 228 230 - if (!id->bus_hold_flag && 231 - (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) 232 - cdns_i2c_clear_bus_hold(id); 229 + if (updatetx && 230 + (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)) 231 + break; 232 + } 233 + 234 + /* 235 + * The controller sends NACK to the slave when transfer size 236 + * register reaches zero without considering the HOLD bit. 237 + * This workaround is implemented for large data transfers to 238 + * maintain transfer size non-zero while performing a large 239 + * receive operation. 240 + */ 241 + if (updatetx && 242 + (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)) { 243 + /* wait while fifo is full */ 244 + while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != 245 + (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH)) 246 + ; 247 + 248 + /* 249 + * Check number of bytes to be received against maximum 250 + * transfer size and update register accordingly. 251 + */ 252 + if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) > 253 + CDNS_I2C_TRANSFER_SIZE) { 254 + cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 255 + CDNS_I2C_XFER_SIZE_OFFSET); 256 + id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE + 257 + CDNS_I2C_FIFO_DEPTH; 258 + } else { 259 + cdns_i2c_writereg(id->recv_count - 260 + CDNS_I2C_FIFO_DEPTH, 261 + CDNS_I2C_XFER_SIZE_OFFSET); 262 + id->curr_recv_count = id->recv_count; 263 + } 264 + } 265 + 266 + /* Clear hold (if not repeated start) and signal completion */ 267 + if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) { 268 + if (!id->bus_hold_flag) 269 + cdns_i2c_clear_bus_hold(id); 270 + done_flag = 1; 271 + } 233 272 234 273 status = IRQ_HANDLED; 235 274 } 236 275 237 - /* Handling Transfer Complete interrupt */ 238 - if (isr_status & CDNS_I2C_IXR_COMP) { 239 - if (!id->p_recv_buf) { 240 - /* 241 - * If the device is sending data If there is further 242 - * data to be sent. Calculate the available space 243 - * in FIFO and fill the FIFO with that many bytes. 244 - */ 245 - if (id->send_count) { 246 - avail_bytes = CDNS_I2C_FIFO_DEPTH - 247 - cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 248 - if (id->send_count > avail_bytes) 249 - bytes_to_send = avail_bytes; 250 - else 251 - bytes_to_send = id->send_count; 276 + /* When sending, handle transfer complete interrupt */ 277 + if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) { 278 + /* 279 + * If there is more data to be sent, calculate the 280 + * space available in FIFO and fill with that many bytes. 281 + */ 282 + if (id->send_count) { 283 + avail_bytes = CDNS_I2C_FIFO_DEPTH - 284 + cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 285 + if (id->send_count > avail_bytes) 286 + bytes_to_send = avail_bytes; 287 + else 288 + bytes_to_send = id->send_count; 252 289 253 - while (bytes_to_send--) { 254 - cdns_i2c_writereg( 255 - (*(id->p_send_buf)++), 256 - CDNS_I2C_DATA_OFFSET); 257 - id->send_count--; 258 - } 259 - } else { 260 - /* 261 - * Signal the completion of transaction and 262 - * clear the hold bus bit if there are no 263 - * further messages to be processed. 264 - */ 265 - done_flag = 1; 290 + while (bytes_to_send--) { 291 + cdns_i2c_writereg( 292 + (*(id->p_send_buf)++), 293 + CDNS_I2C_DATA_OFFSET); 294 + id->send_count--; 266 295 } 267 - if (!id->send_count && !id->bus_hold_flag) 268 - cdns_i2c_clear_bus_hold(id); 269 296 } else { 270 - if (!id->bus_hold_flag) 271 - cdns_i2c_clear_bus_hold(id); 272 297 /* 273 - * If the device is receiving data, then signal 274 - * the completion of transaction and read the data 275 - * present in the FIFO. Signal the completion of 276 - * transaction. 298 + * Signal the completion of transaction and 299 + * clear the hold bus bit if there are no 300 + * further messages to be processed. 277 301 */ 278 - while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & 279 - CDNS_I2C_SR_RXDV) { 280 - *(id->p_recv_buf)++ = 281 - cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 282 - id->recv_count--; 283 - } 284 302 done_flag = 1; 285 303 } 304 + if (!id->send_count && !id->bus_hold_flag) 305 + cdns_i2c_clear_bus_hold(id); 286 306 287 307 status = IRQ_HANDLED; 288 308 } ··· 314 288 id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; 315 289 if (id->err_status) 316 290 status = IRQ_HANDLED; 317 - 318 - cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 319 291 320 292 if (done_flag) 321 293 complete(&id->xfer_done); ··· 340 316 if (id->p_msg->flags & I2C_M_RECV_LEN) 341 317 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1; 342 318 319 + id->curr_recv_count = id->recv_count; 320 + 343 321 /* 344 322 * Check for the message size against FIFO depth and set the 345 323 * 'hold bus' bit if it is greater than FIFO depth. ··· 361 335 * receive if it is less than transfer size and transfer size if 362 336 * it is more. Enable the interrupts. 363 337 */ 364 - if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) 338 + if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 365 339 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 366 340 CDNS_I2C_XFER_SIZE_OFFSET); 367 - else 341 + id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 342 + } else { 368 343 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); 344 + } 345 + 369 346 /* Clear the bus hold flag if bytes to receive is less than FIFO size */ 370 347 if (!id->bus_hold_flag && 371 348 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && ··· 545 516 * processed with a repeated start. 546 517 */ 547 518 if (num > 1) { 519 + /* 520 + * This controller does not give completion interrupt after a 521 + * master receive message if HOLD bit is set (repeated start), 522 + * resulting in SW timeout. Hence, if a receive message is 523 + * followed by any other message, an error is returned 524 + * indicating that this sequence is not supported. 525 + */ 526 + for (count = 0; count < num - 1; count++) { 527 + if (msgs[count].flags & I2C_M_RD) { 528 + dev_warn(adap->dev.parent, 529 + "Can't do repeated start after a receive message\n"); 530 + return -EOPNOTSUPP; 531 + } 532 + } 548 533 id->bus_hold_flag = 1; 549 534 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 550 535 reg |= CDNS_I2C_CR_HOLD;

+160

drivers/i2c/busses/i2c-designware-baytrail.c

··· 1 + /* 2 + * Intel BayTrail PMIC I2C bus semaphore implementaion 3 + * Copyright (c) 2014, Intel Corporation. 4 + * 5 + * This program is free software; you can redistribute it and/or modify it 6 + * under the terms and conditions of the GNU General Public License, 7 + * version 2, as published by the Free Software Foundation. 8 + * 9 + * This program is distributed in the hope it will be useful, but WITHOUT 10 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 + * more details. 13 + */ 14 + #include <linux/module.h> 15 + #include <linux/delay.h> 16 + #include <linux/device.h> 17 + #include <linux/acpi.h> 18 + #include <linux/i2c.h> 19 + #include <linux/interrupt.h> 20 + #include <asm/iosf_mbi.h> 21 + #include "i2c-designware-core.h" 22 + 23 + #define SEMAPHORE_TIMEOUT 100 24 + #define PUNIT_SEMAPHORE 0x7 25 + 26 + static unsigned long acquired; 27 + 28 + static int get_sem(struct device *dev, u32 *sem) 29 + { 30 + u32 reg_val; 31 + int ret; 32 + 33 + ret = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ, PUNIT_SEMAPHORE, 34 + &reg_val); 35 + if (ret) { 36 + dev_err(dev, "iosf failed to read punit semaphore\n"); 37 + return ret; 38 + } 39 + 40 + *sem = reg_val & 0x1; 41 + 42 + return 0; 43 + } 44 + 45 + static void reset_semaphore(struct device *dev) 46 + { 47 + u32 data; 48 + 49 + if (iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ, 50 + PUNIT_SEMAPHORE, &data)) { 51 + dev_err(dev, "iosf failed to reset punit semaphore during read\n"); 52 + return; 53 + } 54 + 55 + data = data & 0xfffffffe; 56 + if (iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE, 57 + PUNIT_SEMAPHORE, data)) 58 + dev_err(dev, "iosf failed to reset punit semaphore during write\n"); 59 + } 60 + 61 + int baytrail_i2c_acquire(struct dw_i2c_dev *dev) 62 + { 63 + u32 sem = 0; 64 + int ret; 65 + unsigned long start, end; 66 + 67 + if (!dev || !dev->dev) 68 + return -ENODEV; 69 + 70 + if (!dev->acquire_lock) 71 + return 0; 72 + 73 + /* host driver writes 0x2 to side band semaphore register */ 74 + ret = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE, 75 + PUNIT_SEMAPHORE, 0x2); 76 + if (ret) { 77 + dev_err(dev->dev, "iosf punit semaphore request failed\n"); 78 + return ret; 79 + } 80 + 81 + /* host driver waits for bit 0 to be set in semaphore register */ 82 + start = jiffies; 83 + end = start + msecs_to_jiffies(SEMAPHORE_TIMEOUT); 84 + while (!time_after(jiffies, end)) { 85 + ret = get_sem(dev->dev, &sem); 86 + if (!ret && sem) { 87 + acquired = jiffies; 88 + dev_dbg(dev->dev, "punit semaphore acquired after %ums\n", 89 + jiffies_to_msecs(jiffies - start)); 90 + return 0; 91 + } 92 + 93 + usleep_range(1000, 2000); 94 + } 95 + 96 + dev_err(dev->dev, "punit semaphore timed out, resetting\n"); 97 + reset_semaphore(dev->dev); 98 + 99 + ret = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ, 100 + PUNIT_SEMAPHORE, &sem); 101 + if (!ret) 102 + dev_err(dev->dev, "iosf failed to read punit semaphore\n"); 103 + else 104 + dev_err(dev->dev, "PUNIT SEM: %d\n", sem); 105 + 106 + WARN_ON(1); 107 + 108 + return -ETIMEDOUT; 109 + } 110 + EXPORT_SYMBOL(baytrail_i2c_acquire); 111 + 112 + void baytrail_i2c_release(struct dw_i2c_dev *dev) 113 + { 114 + if (!dev || !dev->dev) 115 + return; 116 + 117 + if (!dev->acquire_lock) 118 + return; 119 + 120 + reset_semaphore(dev->dev); 121 + dev_dbg(dev->dev, "punit semaphore held for %ums\n", 122 + jiffies_to_msecs(jiffies - acquired)); 123 + } 124 + EXPORT_SYMBOL(baytrail_i2c_release); 125 + 126 + int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev) 127 + { 128 + acpi_status status; 129 + unsigned long long shared_host = 0; 130 + acpi_handle handle; 131 + 132 + if (!dev || !dev->dev) 133 + return 0; 134 + 135 + handle = ACPI_HANDLE(dev->dev); 136 + if (!handle) 137 + return 0; 138 + 139 + status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); 140 + 141 + if (ACPI_FAILURE(status)) 142 + return 0; 143 + 144 + if (shared_host) { 145 + dev_info(dev->dev, "I2C bus managed by PUNIT\n"); 146 + dev->acquire_lock = baytrail_i2c_acquire; 147 + dev->release_lock = baytrail_i2c_release; 148 + dev->pm_runtime_disabled = true; 149 + } 150 + 151 + if (!iosf_mbi_available()) 152 + return -EPROBE_DEFER; 153 + 154 + return 0; 155 + } 156 + EXPORT_SYMBOL(i2c_dw_eval_lock_support); 157 + 158 + MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>"); 159 + MODULE_DESCRIPTION("Baytrail I2C Semaphore driver"); 160 + MODULE_LICENSE("GPL v2");

+54 -29

drivers/i2c/busses/i2c-designware-core.c

··· 170 170 u32 value; 171 171 172 172 if (dev->accessor_flags & ACCESS_16BIT) 173 - value = readw(dev->base + offset) | 174 - (readw(dev->base + offset + 2) << 16); 173 + value = readw_relaxed(dev->base + offset) | 174 + (readw_relaxed(dev->base + offset + 2) << 16); 175 175 else 176 - value = readl(dev->base + offset); 176 + value = readl_relaxed(dev->base + offset); 177 177 178 178 if (dev->accessor_flags & ACCESS_SWAP) 179 179 return swab32(value); ··· 187 187 b = swab32(b); 188 188 189 189 if (dev->accessor_flags & ACCESS_16BIT) { 190 - writew((u16)b, dev->base + offset); 191 - writew((u16)(b >> 16), dev->base + offset + 2); 190 + writew_relaxed((u16)b, dev->base + offset); 191 + writew_relaxed((u16)(b >> 16), dev->base + offset + 2); 192 192 } else { 193 - writel(b, dev->base + offset); 193 + writel_relaxed(b, dev->base + offset); 194 194 } 195 195 } 196 196 ··· 285 285 u32 hcnt, lcnt; 286 286 u32 reg; 287 287 u32 sda_falling_time, scl_falling_time; 288 + int ret; 289 + 290 + if (dev->acquire_lock) { 291 + ret = dev->acquire_lock(dev); 292 + if (ret) { 293 + dev_err(dev->dev, "couldn't acquire bus ownership\n"); 294 + return ret; 295 + } 296 + } 288 297 289 298 input_clock_khz = dev->get_clk_rate_khz(dev); 290 299 ··· 307 298 } else if (reg != DW_IC_COMP_TYPE_VALUE) { 308 299 dev_err(dev->dev, "Unknown Synopsys component type: " 309 300 "0x%08x\n", reg); 301 + if (dev->release_lock) 302 + dev->release_lock(dev); 310 303 return -ENODEV; 311 304 } 312 305 ··· 320 309 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */ 321 310 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */ 322 311 323 - /* Standard-mode */ 324 - hcnt = i2c_dw_scl_hcnt(input_clock_khz, 325 - 4000, /* tHD;STA = tHIGH = 4.0 us */ 326 - sda_falling_time, 327 - 0, /* 0: DW default, 1: Ideal */ 328 - 0); /* No offset */ 329 - lcnt = i2c_dw_scl_lcnt(input_clock_khz, 330 - 4700, /* tLOW = 4.7 us */ 331 - scl_falling_time, 332 - 0); /* No offset */ 333 - 334 - /* Allow platforms to specify the ideal HCNT and LCNT values */ 312 + /* Set SCL timing parameters for standard-mode */ 335 313 if (dev->ss_hcnt && dev->ss_lcnt) { 336 314 hcnt = dev->ss_hcnt; 337 315 lcnt = dev->ss_lcnt; 316 + } else { 317 + hcnt = i2c_dw_scl_hcnt(input_clock_khz, 318 + 4000, /* tHD;STA = tHIGH = 4.0 us */ 319 + sda_falling_time, 320 + 0, /* 0: DW default, 1: Ideal */ 321 + 0); /* No offset */ 322 + lcnt = i2c_dw_scl_lcnt(input_clock_khz, 323 + 4700, /* tLOW = 4.7 us */ 324 + scl_falling_time, 325 + 0); /* No offset */ 338 326 } 339 327 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); 340 328 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); 341 329 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); 342 330 343 - /* Fast-mode */ 344 - hcnt = i2c_dw_scl_hcnt(input_clock_khz, 345 - 600, /* tHD;STA = tHIGH = 0.6 us */ 346 - sda_falling_time, 347 - 0, /* 0: DW default, 1: Ideal */ 348 - 0); /* No offset */ 349 - lcnt = i2c_dw_scl_lcnt(input_clock_khz, 350 - 1300, /* tLOW = 1.3 us */ 351 - scl_falling_time, 352 - 0); /* No offset */ 353 - 331 + /* Set SCL timing parameters for fast-mode */ 354 332 if (dev->fs_hcnt && dev->fs_lcnt) { 355 333 hcnt = dev->fs_hcnt; 356 334 lcnt = dev->fs_lcnt; 335 + } else { 336 + hcnt = i2c_dw_scl_hcnt(input_clock_khz, 337 + 600, /* tHD;STA = tHIGH = 0.6 us */ 338 + sda_falling_time, 339 + 0, /* 0: DW default, 1: Ideal */ 340 + 0); /* No offset */ 341 + lcnt = i2c_dw_scl_lcnt(input_clock_khz, 342 + 1300, /* tLOW = 1.3 us */ 343 + scl_falling_time, 344 + 0); /* No offset */ 357 345 } 358 346 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); 359 347 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); ··· 374 364 375 365 /* configure the i2c master */ 376 366 dw_writel(dev, dev->master_cfg , DW_IC_CON); 367 + 368 + if (dev->release_lock) 369 + dev->release_lock(dev); 377 370 return 0; 378 371 } 379 372 EXPORT_SYMBOL_GPL(i2c_dw_init); ··· 640 627 dev->abort_source = 0; 641 628 dev->rx_outstanding = 0; 642 629 630 + if (dev->acquire_lock) { 631 + ret = dev->acquire_lock(dev); 632 + if (ret) { 633 + dev_err(dev->dev, "couldn't acquire bus ownership\n"); 634 + goto done_nolock; 635 + } 636 + } 637 + 643 638 ret = i2c_dw_wait_bus_not_busy(dev); 644 639 if (ret < 0) 645 640 goto done; ··· 693 672 ret = -EIO; 694 673 695 674 done: 675 + if (dev->release_lock) 676 + dev->release_lock(dev); 677 + 678 + done_nolock: 696 679 pm_runtime_mark_last_busy(dev->dev); 697 680 pm_runtime_put_autosuspend(dev->dev); 698 681 mutex_unlock(&dev->lock);

+12

drivers/i2c/busses/i2c-designware-core.h

··· 61 61 * @ss_lcnt: standard speed LCNT value 62 62 * @fs_hcnt: fast speed HCNT value 63 63 * @fs_lcnt: fast speed LCNT value 64 + * @acquire_lock: function to acquire a hardware lock on the bus 65 + * @release_lock: function to release a hardware lock on the bus 66 + * @pm_runtime_disabled: true if pm runtime is disabled 64 67 * 65 68 * HCNT and LCNT parameters can be used if the platform knows more accurate 66 69 * values than the one computed based only on the input clock frequency. ··· 104 101 u16 ss_lcnt; 105 102 u16 fs_hcnt; 106 103 u16 fs_lcnt; 104 + int (*acquire_lock)(struct dw_i2c_dev *dev); 105 + void (*release_lock)(struct dw_i2c_dev *dev); 106 + bool pm_runtime_disabled; 107 107 }; 108 108 109 109 #define ACCESS_SWAP 0x00000001 ··· 125 119 extern void i2c_dw_clear_int(struct dw_i2c_dev *dev); 126 120 extern void i2c_dw_disable_int(struct dw_i2c_dev *dev); 127 121 extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev); 122 + 123 + #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) 124 + extern int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev); 125 + #else 126 + static inline int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev) { return 0; } 127 + #endif

+5 -36

drivers/i2c/busses/i2c-designware-pcidrv.c

··· 6 6 * Copyright (C) 2006 Texas Instruments. 7 7 * Copyright (C) 2007 MontaVista Software Inc. 8 8 * Copyright (C) 2009 Provigent Ltd. 9 - * Copyright (C) 2011 Intel corporation. 9 + * Copyright (C) 2011, 2015 Intel Corporation. 10 10 * 11 11 * ---------------------------------------------------------------------------- 12 12 * ··· 40 40 #define DRIVER_NAME "i2c-designware-pci" 41 41 42 42 enum dw_pci_ctl_id_t { 43 - moorestown_0, 44 - moorestown_1, 45 - moorestown_2, 46 - 47 43 medfield_0, 48 44 medfield_1, 49 45 medfield_2, ··· 97 101 .sda_hold = 0x9, 98 102 }; 99 103 100 - static struct dw_pci_controller dw_pci_controllers[] = { 101 - [moorestown_0] = { 102 - .bus_num = 0, 103 - .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 104 - .tx_fifo_depth = 32, 105 - .rx_fifo_depth = 32, 106 - .clk_khz = 25000, 107 - }, 108 - [moorestown_1] = { 109 - .bus_num = 1, 110 - .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 111 - .tx_fifo_depth = 32, 112 - .rx_fifo_depth = 32, 113 - .clk_khz = 25000, 114 - }, 115 - [moorestown_2] = { 116 - .bus_num = 2, 117 - .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 118 - .tx_fifo_depth = 32, 119 - .rx_fifo_depth = 32, 120 - .clk_khz = 25000, 121 - }, 104 + static struct dw_pci_controller dw_pci_controllers[] = { 122 105 [medfield_0] = { 123 106 .bus_num = 0, 124 107 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, ··· 145 170 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 146 171 .tx_fifo_depth = 32, 147 172 .rx_fifo_depth = 32, 148 - .clk_khz = 100000, 149 173 .functionality = I2C_FUNC_10BIT_ADDR, 150 174 .scl_sda_cfg = &byt_config, 151 175 }, ··· 153 179 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 154 180 .tx_fifo_depth = 32, 155 181 .rx_fifo_depth = 32, 156 - .clk_khz = 100000, 157 182 .functionality = I2C_FUNC_10BIT_ADDR, 158 183 .scl_sda_cfg = &hsw_config, 159 184 }, ··· 232 259 dev->functionality = controller->functionality | 233 260 DW_DEFAULT_FUNCTIONALITY; 234 261 235 - dev->master_cfg = controller->bus_cfg; 262 + dev->master_cfg = controller->bus_cfg; 236 263 if (controller->scl_sda_cfg) { 237 264 cfg = controller->scl_sda_cfg; 238 265 dev->ss_hcnt = cfg->ss_hcnt; ··· 298 325 MODULE_ALIAS("i2c_designware-pci"); 299 326 300 327 static const struct pci_device_id i2_designware_pci_ids[] = { 301 - /* Moorestown */ 302 - { PCI_VDEVICE(INTEL, 0x0802), moorestown_0 }, 303 - { PCI_VDEVICE(INTEL, 0x0803), moorestown_1 }, 304 - { PCI_VDEVICE(INTEL, 0x0804), moorestown_2 }, 305 328 /* Medfield */ 306 - { PCI_VDEVICE(INTEL, 0x0817), medfield_3,}, 329 + { PCI_VDEVICE(INTEL, 0x0817), medfield_3 }, 307 330 { PCI_VDEVICE(INTEL, 0x0818), medfield_4 }, 308 331 { PCI_VDEVICE(INTEL, 0x0819), medfield_5 }, 309 332 { PCI_VDEVICE(INTEL, 0x082C), medfield_0 }, ··· 317 348 { PCI_VDEVICE(INTEL, 0x9c61), haswell }, 318 349 { PCI_VDEVICE(INTEL, 0x9c62), haswell }, 319 350 /* Braswell / Cherrytrail */ 320 - { PCI_VDEVICE(INTEL, 0x22C1), baytrail,}, 351 + { PCI_VDEVICE(INTEL, 0x22C1), baytrail }, 321 352 { PCI_VDEVICE(INTEL, 0x22C2), baytrail }, 322 353 { PCI_VDEVICE(INTEL, 0x22C3), baytrail }, 323 354 { PCI_VDEVICE(INTEL, 0x22C4), baytrail },

+15 -5

drivers/i2c/busses/i2c-designware-platdrv.c

··· 195 195 clk_freq = pdata->i2c_scl_freq; 196 196 } 197 197 198 + r = i2c_dw_eval_lock_support(dev); 199 + if (r) 200 + return r; 201 + 198 202 dev->functionality = 199 203 I2C_FUNC_I2C | 200 204 I2C_FUNC_10BIT_ADDR | ··· 261 257 return r; 262 258 } 263 259 264 - pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); 265 - pm_runtime_use_autosuspend(&pdev->dev); 266 - pm_runtime_set_active(&pdev->dev); 267 - pm_runtime_enable(&pdev->dev); 260 + if (dev->pm_runtime_disabled) { 261 + pm_runtime_forbid(&pdev->dev); 262 + } else { 263 + pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); 264 + pm_runtime_use_autosuspend(&pdev->dev); 265 + pm_runtime_set_active(&pdev->dev); 266 + pm_runtime_enable(&pdev->dev); 267 + } 268 268 269 269 return 0; 270 270 } ··· 318 310 struct dw_i2c_dev *i_dev = platform_get_drvdata(pdev); 319 311 320 312 clk_prepare_enable(i_dev->clk); 321 - i2c_dw_init(i_dev); 313 + 314 + if (!i_dev->pm_runtime_disabled) 315 + i2c_dw_init(i_dev); 322 316 323 317 return 0; 324 318 }

+17 -16

drivers/i2c/busses/i2c-imx.c

··· 201 201 void __iomem *base; 202 202 wait_queue_head_t queue; 203 203 unsigned long i2csr; 204 - unsigned int disable_delay; 204 + unsigned int disable_delay; 205 205 int stopped; 206 206 unsigned int ifdr; /* IMX_I2C_IFDR */ 207 207 unsigned int cur_clk; ··· 295 295 dma->chan_tx = dma_request_slave_channel(dev, "tx"); 296 296 if (!dma->chan_tx) { 297 297 dev_dbg(dev, "can't request DMA tx channel\n"); 298 - ret = -ENODEV; 299 298 goto fail_al; 300 299 } 301 300 ··· 312 313 dma->chan_rx = dma_request_slave_channel(dev, "rx"); 313 314 if (!dma->chan_rx) { 314 315 dev_dbg(dev, "can't request DMA rx channel\n"); 315 - ret = -ENODEV; 316 316 goto fail_tx; 317 317 } 318 318 ··· 479 481 i2c_clk_rate = clk_get_rate(i2c_imx->clk); 480 482 if (i2c_imx->cur_clk == i2c_clk_rate) 481 483 return; 482 - else 483 - i2c_imx->cur_clk = i2c_clk_rate; 484 + 485 + i2c_imx->cur_clk = i2c_clk_rate; 484 486 485 487 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 486 488 if (div < i2c_clk_div[0].div) ··· 488 490 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 489 491 i = i2c_imx->hwdata->ndivs - 1; 490 492 else 491 - for (i = 0; i2c_clk_div[i].div < div; i++); 493 + for (i = 0; i2c_clk_div[i].div < div; i++) 494 + ; 492 495 493 496 /* Store divider value */ 494 497 i2c_imx->ifdr = i2c_clk_div[i].val; ··· 627 628 result = wait_for_completion_timeout( 628 629 &i2c_imx->dma->cmd_complete, 629 630 msecs_to_jiffies(DMA_TIMEOUT)); 630 - if (result <= 0) { 631 + if (result == 0) { 631 632 dmaengine_terminate_all(dma->chan_using); 632 - return result ?: -ETIMEDOUT; 633 + return -ETIMEDOUT; 633 634 } 634 635 635 636 /* Waiting for transfer complete. */ ··· 685 686 result = wait_for_completion_timeout( 686 687 &i2c_imx->dma->cmd_complete, 687 688 msecs_to_jiffies(DMA_TIMEOUT)); 688 - if (result <= 0) { 689 + if (result == 0) { 689 690 dmaengine_terminate_all(dma->chan_using); 690 - return result ?: -ETIMEDOUT; 691 + return -ETIMEDOUT; 691 692 } 692 693 693 694 /* waiting for transfer complete. */ ··· 821 822 /* read data */ 822 823 for (i = 0; i < msgs->len; i++) { 823 824 u8 len = 0; 825 + 824 826 result = i2c_imx_trx_complete(i2c_imx); 825 827 if (result) 826 828 return result; ··· 917 917 /* write/read data */ 918 918 #ifdef CONFIG_I2C_DEBUG_BUS 919 919 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 920 - dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " 921 - "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, 920 + dev_dbg(&i2c_imx->adapter.dev, 921 + "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 922 + __func__, 922 923 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 923 924 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 924 925 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 925 926 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 926 927 dev_dbg(&i2c_imx->adapter.dev, 927 - "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " 928 - "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, 928 + "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 929 + __func__, 929 930 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 930 931 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 931 932 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), ··· 1005 1004 i2c_imx->adapter.owner = THIS_MODULE; 1006 1005 i2c_imx->adapter.algo = &i2c_imx_algo; 1007 1006 i2c_imx->adapter.dev.parent = &pdev->dev; 1008 - i2c_imx->adapter.nr = pdev->id; 1007 + i2c_imx->adapter.nr = pdev->id; 1009 1008 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1010 1009 i2c_imx->base = base; 1011 1010 ··· 1064 1063 i2c_imx->adapter.name); 1065 1064 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1066 1065 1067 - /* Init DMA config if support*/ 1066 + /* Init DMA config if supported */ 1068 1067 i2c_imx_dma_request(i2c_imx, phy_addr); 1069 1068 1070 1069 return 0; /* Return OK */

+79 -12

drivers/i2c/busses/i2c-ocores.c

··· 12 12 * kind, whether express or implied. 13 13 */ 14 14 15 + #include <linux/clk.h> 15 16 #include <linux/err.h> 16 17 #include <linux/kernel.h> 17 18 #include <linux/module.h> ··· 36 35 int pos; 37 36 int nmsgs; 38 37 int state; /* see STATE_ */ 39 - int clock_khz; 38 + struct clk *clk; 39 + int ip_clock_khz; 40 + int bus_clock_khz; 40 41 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); 41 42 u8 (*getreg)(struct ocores_i2c *i2c, int reg); 42 43 }; ··· 218 215 return -ETIMEDOUT; 219 216 } 220 217 221 - static void ocores_init(struct ocores_i2c *i2c) 218 + static int ocores_init(struct device *dev, struct ocores_i2c *i2c) 222 219 { 223 220 int prescale; 221 + int diff; 224 222 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 225 223 226 224 /* make sure the device is disabled */ 227 225 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 228 226 229 - prescale = (i2c->clock_khz / (5*100)) - 1; 227 + prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1; 228 + prescale = clamp(prescale, 0, 0xffff); 229 + 230 + diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz; 231 + if (abs(diff) > i2c->bus_clock_khz / 10) { 232 + dev_err(dev, 233 + "Unsupported clock settings: core: %d KHz, bus: %d KHz\n", 234 + i2c->ip_clock_khz, i2c->bus_clock_khz); 235 + return -EINVAL; 236 + } 237 + 230 238 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); 231 239 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); 232 240 233 241 /* Init the device */ 234 242 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 235 243 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN); 244 + 245 + return 0; 236 246 } 237 247 238 248 ··· 320 304 struct device_node *np = pdev->dev.of_node; 321 305 const struct of_device_id *match; 322 306 u32 val; 307 + u32 clock_frequency; 308 + bool clock_frequency_present; 323 309 324 310 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { 325 311 /* no 'reg-shift', check for deprecated 'regstep' */ ··· 337 319 } 338 320 } 339 321 340 - if (of_property_read_u32(np, "clock-frequency", &val)) { 341 - dev_err(&pdev->dev, 342 - "Missing required parameter 'clock-frequency'\n"); 343 - return -ENODEV; 322 + clock_frequency_present = !of_property_read_u32(np, "clock-frequency", 323 + &clock_frequency); 324 + i2c->bus_clock_khz = 100; 325 + 326 + i2c->clk = devm_clk_get(&pdev->dev, NULL); 327 + 328 + if (!IS_ERR(i2c->clk)) { 329 + int ret = clk_prepare_enable(i2c->clk); 330 + 331 + if (ret) { 332 + dev_err(&pdev->dev, 333 + "clk_prepare_enable failed: %d\n", ret); 334 + return ret; 335 + } 336 + i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000; 337 + if (clock_frequency_present) 338 + i2c->bus_clock_khz = clock_frequency / 1000; 344 339 } 345 - i2c->clock_khz = val / 1000; 340 + 341 + if (i2c->ip_clock_khz == 0) { 342 + if (of_property_read_u32(np, "opencores,ip-clock-frequency", 343 + &val)) { 344 + if (!clock_frequency_present) { 345 + dev_err(&pdev->dev, 346 + "Missing required parameter 'opencores,ip-clock-frequency'\n"); 347 + return -ENODEV; 348 + } 349 + i2c->ip_clock_khz = clock_frequency / 1000; 350 + dev_warn(&pdev->dev, 351 + "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n"); 352 + } else { 353 + i2c->ip_clock_khz = val / 1000; 354 + if (clock_frequency_present) 355 + i2c->bus_clock_khz = clock_frequency / 1000; 356 + } 357 + } 346 358 347 359 of_property_read_u32(pdev->dev.of_node, "reg-io-width", 348 360 &i2c->reg_io_width); ··· 416 368 if (pdata) { 417 369 i2c->reg_shift = pdata->reg_shift; 418 370 i2c->reg_io_width = pdata->reg_io_width; 419 - i2c->clock_khz = pdata->clock_khz; 371 + i2c->ip_clock_khz = pdata->clock_khz; 372 + i2c->bus_clock_khz = 100; 420 373 } else { 421 374 ret = ocores_i2c_of_probe(pdev, i2c); 422 375 if (ret) ··· 451 402 } 452 403 } 453 404 454 - ocores_init(i2c); 405 + ret = ocores_init(&pdev->dev, i2c); 406 + if (ret) 407 + return ret; 455 408 456 409 init_waitqueue_head(&i2c->wait); 457 410 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0, ··· 497 446 /* remove adapter & data */ 498 447 i2c_del_adapter(&i2c->adap); 499 448 449 + if (!IS_ERR(i2c->clk)) 450 + clk_disable_unprepare(i2c->clk); 451 + 500 452 return 0; 501 453 } 502 454 ··· 512 458 /* make sure the device is disabled */ 513 459 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 514 460 461 + if (!IS_ERR(i2c->clk)) 462 + clk_disable_unprepare(i2c->clk); 515 463 return 0; 516 464 } 517 465 ··· 521 465 { 522 466 struct ocores_i2c *i2c = dev_get_drvdata(dev); 523 467 524 - ocores_init(i2c); 468 + if (!IS_ERR(i2c->clk)) { 469 + unsigned long rate; 470 + int ret = clk_prepare_enable(i2c->clk); 525 471 526 - return 0; 472 + if (ret) { 473 + dev_err(dev, 474 + "clk_prepare_enable failed: %d\n", ret); 475 + return ret; 476 + } 477 + rate = clk_get_rate(i2c->clk) / 1000; 478 + if (rate) 479 + i2c->ip_clock_khz = rate; 480 + } 481 + return ocores_init(dev, i2c); 527 482 } 528 483 529 484 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);

-7

drivers/i2c/busses/i2c-pmcmsp.c

··· 148 148 return ((clock->filter & 0xf) << 12) | (clock->clock & 0x03ff); 149 149 } 150 150 151 - static inline void pmcmsptwi_reg_to_clock( 152 - u32 reg, struct pmcmsptwi_clock *clock) 153 - { 154 - clock->filter = (reg >> 12) & 0xf; 155 - clock->clock = reg & 0x03ff; 156 - } 157 - 158 151 static inline u32 pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg *cfg) 159 152 { 160 153 return ((cfg->arbf & 0xf) << 12) |

+75 -24

drivers/i2c/busses/i2c-rk3x.c

··· 102 102 103 103 /* Settings */ 104 104 unsigned int scl_frequency; 105 + unsigned int scl_rise_ns; 106 + unsigned int scl_fall_ns; 107 + unsigned int sda_fall_ns; 105 108 106 109 /* Synchronization & notification */ 107 110 spinlock_t lock; ··· 438 435 * 439 436 * @clk_rate: I2C input clock rate 440 437 * @scl_rate: Desired SCL rate 438 + * @scl_rise_ns: How many ns it takes for SCL to rise. 439 + * @scl_fall_ns: How many ns it takes for SCL to fall. 440 + * @sda_fall_ns: How many ns it takes for SDA to fall. 441 441 * @div_low: Divider output for low 442 442 * @div_high: Divider output for high 443 443 * ··· 449 443 * too high, we silently use the highest possible rate. 450 444 */ 451 445 static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate, 446 + unsigned long scl_rise_ns, 447 + unsigned long scl_fall_ns, 448 + unsigned long sda_fall_ns, 452 449 unsigned long *div_low, unsigned long *div_high) 453 450 { 454 - unsigned long min_low_ns, min_high_ns; 455 - unsigned long max_data_hold_ns; 451 + unsigned long spec_min_low_ns, spec_min_high_ns; 452 + unsigned long spec_setup_start, spec_max_data_hold_ns; 456 453 unsigned long data_hold_buffer_ns; 454 + 455 + unsigned long min_low_ns, min_high_ns; 457 456 unsigned long max_low_ns, min_total_ns; 458 457 459 458 unsigned long clk_rate_khz, scl_rate_khz; ··· 480 469 scl_rate = 1000; 481 470 482 471 /* 483 - * min_low_ns: The minimum number of ns we need to hold low 484 - * to meet i2c spec 485 - * min_high_ns: The minimum number of ns we need to hold high 486 - * to meet i2c spec 487 - * max_low_ns: The maximum number of ns we can hold low 488 - * to meet i2c spec 472 + * min_low_ns: The minimum number of ns we need to hold low to 473 + * meet I2C specification, should include fall time. 474 + * min_high_ns: The minimum number of ns we need to hold high to 475 + * meet I2C specification, should include rise time. 476 + * max_low_ns: The maximum number of ns we can hold low to meet 477 + * I2C specification. 489 478 * 490 - * Note: max_low_ns should be (max data hold time * 2 - buffer) 479 + * Note: max_low_ns should be (maximum data hold time * 2 - buffer) 491 480 * This is because the i2c host on Rockchip holds the data line 492 481 * for half the low time. 493 482 */ 494 483 if (scl_rate <= 100000) { 495 - min_low_ns = 4700; 496 - min_high_ns = 4000; 497 - max_data_hold_ns = 3450; 484 + /* Standard-mode */ 485 + spec_min_low_ns = 4700; 486 + spec_setup_start = 4700; 487 + spec_min_high_ns = 4000; 488 + spec_max_data_hold_ns = 3450; 498 489 data_hold_buffer_ns = 50; 499 490 } else { 500 - min_low_ns = 1300; 501 - min_high_ns = 600; 502 - max_data_hold_ns = 900; 491 + /* Fast-mode */ 492 + spec_min_low_ns = 1300; 493 + spec_setup_start = 600; 494 + spec_min_high_ns = 600; 495 + spec_max_data_hold_ns = 900; 503 496 data_hold_buffer_ns = 50; 504 497 } 505 - max_low_ns = max_data_hold_ns * 2 - data_hold_buffer_ns; 498 + min_high_ns = scl_rise_ns + spec_min_high_ns; 499 + 500 + /* 501 + * Timings for repeated start: 502 + * - controller appears to drop SDA at .875x (7/8) programmed clk high. 503 + * - controller appears to keep SCL high for 2x programmed clk high. 504 + * 505 + * We need to account for those rules in picking our "high" time so 506 + * we meet tSU;STA and tHD;STA times. 507 + */ 508 + min_high_ns = max(min_high_ns, 509 + DIV_ROUND_UP((scl_rise_ns + spec_setup_start) * 1000, 875)); 510 + min_high_ns = max(min_high_ns, 511 + DIV_ROUND_UP((scl_rise_ns + spec_setup_start + 512 + sda_fall_ns + spec_min_high_ns), 2)); 513 + 514 + min_low_ns = scl_fall_ns + spec_min_low_ns; 515 + max_low_ns = spec_max_data_hold_ns * 2 - data_hold_buffer_ns; 506 516 min_total_ns = min_low_ns + min_high_ns; 507 517 508 518 /* Adjust to avoid overflow */ ··· 542 510 min_div_for_hold = (min_low_div + min_high_div); 543 511 544 512 /* 545 - * This is the maximum divider so we don't go over the max. 546 - * We don't round up here (we round down) since this is a max. 513 + * This is the maximum divider so we don't go over the maximum. 514 + * We don't round up here (we round down) since this is a maximum. 547 515 */ 548 516 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000); 549 517 ··· 576 544 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 577 545 scl_rate_khz * 8 * min_total_ns); 578 546 579 - /* Don't allow it to go over the max */ 547 + /* Don't allow it to go over the maximum */ 580 548 if (ideal_low_div > max_low_div) 581 549 ideal_low_div = max_low_div; 582 550 ··· 620 588 u64 t_low_ns, t_high_ns; 621 589 int ret; 622 590 623 - ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, &div_low, 624 - &div_high); 625 - 591 + ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, i2c->scl_rise_ns, 592 + i2c->scl_fall_ns, i2c->sda_fall_ns, 593 + &div_low, &div_high); 626 594 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", i2c->scl_frequency); 627 595 628 596 clk_enable(i2c->clk); ··· 665 633 switch (event) { 666 634 case PRE_RATE_CHANGE: 667 635 if (rk3x_i2c_calc_divs(ndata->new_rate, i2c->scl_frequency, 668 - &div_low, &div_high) != 0) { 636 + i2c->scl_rise_ns, i2c->scl_fall_ns, 637 + i2c->sda_fall_ns, 638 + &div_low, &div_high) != 0) 669 639 return NOTIFY_STOP; 670 - } 671 640 672 641 /* scale up */ 673 642 if (ndata->new_rate > ndata->old_rate) ··· 891 858 DEFAULT_SCL_RATE); 892 859 i2c->scl_frequency = DEFAULT_SCL_RATE; 893 860 } 861 + 862 + /* 863 + * Read rise and fall time from device tree. If not available use 864 + * the default maximum timing from the specification. 865 + */ 866 + if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-rising-time-ns", 867 + &i2c->scl_rise_ns)) { 868 + if (i2c->scl_frequency <= 100000) 869 + i2c->scl_rise_ns = 1000; 870 + else 871 + i2c->scl_rise_ns = 300; 872 + } 873 + if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-falling-time-ns", 874 + &i2c->scl_fall_ns)) 875 + i2c->scl_fall_ns = 300; 876 + if (of_property_read_u32(pdev->dev.of_node, "i2c-sda-falling-time-ns", 877 + &i2c->scl_fall_ns)) 878 + i2c->sda_fall_ns = i2c->scl_fall_ns; 894 879 895 880 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); 896 881 i2c->adap.owner = THIS_MODULE;

+2

drivers/i2c/busses/i2c-tegra.c

··· 286 286 if (rx_fifo_avail > 0 && buf_remaining > 0) { 287 287 BUG_ON(buf_remaining > 3); 288 288 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 289 + val = cpu_to_le32(val); 289 290 memcpy(buf, &val, buf_remaining); 290 291 buf_remaining = 0; 291 292 rx_fifo_avail--; ··· 345 344 if (tx_fifo_avail > 0 && buf_remaining > 0) { 346 345 BUG_ON(buf_remaining > 3); 347 346 memcpy(&val, buf, buf_remaining); 347 + val = le32_to_cpu(val); 348 348 349 349 /* Again update before writing to FIFO to make sure isr sees. */ 350 350 i2c_dev->msg_buf_remaining = 0;

+14 -148

drivers/i2c/i2c-core.c

··· 102 102 struct acpi_resource_i2c_serialbus *sb; 103 103 104 104 sb = &ares->data.i2c_serial_bus; 105 - if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) { 105 + if (!info->addr && sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) { 106 106 info->addr = sb->slave_address; 107 107 if (sb->access_mode == ACPI_I2C_10BIT_MODE) 108 108 info->flags |= I2C_CLIENT_TEN; ··· 698 698 driver->shutdown(client); 699 699 } 700 700 701 - #ifdef CONFIG_PM_SLEEP 702 - static int i2c_legacy_suspend(struct device *dev, pm_message_t mesg) 703 - { 704 - struct i2c_client *client = i2c_verify_client(dev); 705 - struct i2c_driver *driver; 706 - 707 - if (!client || !dev->driver) 708 - return 0; 709 - driver = to_i2c_driver(dev->driver); 710 - if (!driver->suspend) 711 - return 0; 712 - return driver->suspend(client, mesg); 713 - } 714 - 715 - static int i2c_legacy_resume(struct device *dev) 716 - { 717 - struct i2c_client *client = i2c_verify_client(dev); 718 - struct i2c_driver *driver; 719 - 720 - if (!client || !dev->driver) 721 - return 0; 722 - driver = to_i2c_driver(dev->driver); 723 - if (!driver->resume) 724 - return 0; 725 - return driver->resume(client); 726 - } 727 - 728 - static int i2c_device_pm_suspend(struct device *dev) 729 - { 730 - const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 731 - 732 - if (pm) 733 - return pm_generic_suspend(dev); 734 - else 735 - return i2c_legacy_suspend(dev, PMSG_SUSPEND); 736 - } 737 - 738 - static int i2c_device_pm_resume(struct device *dev) 739 - { 740 - const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 741 - 742 - if (pm) 743 - return pm_generic_resume(dev); 744 - else 745 - return i2c_legacy_resume(dev); 746 - } 747 - 748 - static int i2c_device_pm_freeze(struct device *dev) 749 - { 750 - const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 751 - 752 - if (pm) 753 - return pm_generic_freeze(dev); 754 - else 755 - return i2c_legacy_suspend(dev, PMSG_FREEZE); 756 - } 757 - 758 - static int i2c_device_pm_thaw(struct device *dev) 759 - { 760 - const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 761 - 762 - if (pm) 763 - return pm_generic_thaw(dev); 764 - else 765 - return i2c_legacy_resume(dev); 766 - } 767 - 768 - static int i2c_device_pm_poweroff(struct device *dev) 769 - { 770 - const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 771 - 772 - if (pm) 773 - return pm_generic_poweroff(dev); 774 - else 775 - return i2c_legacy_suspend(dev, PMSG_HIBERNATE); 776 - } 777 - 778 - static int i2c_device_pm_restore(struct device *dev) 779 - { 780 - const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 781 - 782 - if (pm) 783 - return pm_generic_restore(dev); 784 - else 785 - return i2c_legacy_resume(dev); 786 - } 787 - #else /* !CONFIG_PM_SLEEP */ 788 - #define i2c_device_pm_suspend NULL 789 - #define i2c_device_pm_resume NULL 790 - #define i2c_device_pm_freeze NULL 791 - #define i2c_device_pm_thaw NULL 792 - #define i2c_device_pm_poweroff NULL 793 - #define i2c_device_pm_restore NULL 794 - #endif /* !CONFIG_PM_SLEEP */ 795 - 796 701 static void i2c_client_dev_release(struct device *dev) 797 702 { 798 703 kfree(to_i2c_client(dev)); ··· 709 804 return sprintf(buf, "%s\n", dev->type == &i2c_client_type ? 710 805 to_i2c_client(dev)->name : to_i2c_adapter(dev)->name); 711 806 } 807 + static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); 712 808 713 809 static ssize_t 714 810 show_modalias(struct device *dev, struct device_attribute *attr, char *buf) ··· 723 817 724 818 return sprintf(buf, "%s%s\n", I2C_MODULE_PREFIX, client->name); 725 819 } 726 - 727 - static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); 728 820 static DEVICE_ATTR(modalias, S_IRUGO, show_modalias, NULL); 729 821 730 822 static struct attribute *i2c_dev_attrs[] = { ··· 731 827 &dev_attr_modalias.attr, 732 828 NULL 733 829 }; 734 - 735 - static struct attribute_group i2c_dev_attr_group = { 736 - .attrs = i2c_dev_attrs, 737 - }; 738 - 739 - static const struct attribute_group *i2c_dev_attr_groups[] = { 740 - &i2c_dev_attr_group, 741 - NULL 742 - }; 743 - 744 - static const struct dev_pm_ops i2c_device_pm_ops = { 745 - .suspend = i2c_device_pm_suspend, 746 - .resume = i2c_device_pm_resume, 747 - .freeze = i2c_device_pm_freeze, 748 - .thaw = i2c_device_pm_thaw, 749 - .poweroff = i2c_device_pm_poweroff, 750 - .restore = i2c_device_pm_restore, 751 - SET_RUNTIME_PM_OPS( 752 - pm_generic_runtime_suspend, 753 - pm_generic_runtime_resume, 754 - NULL 755 - ) 756 - }; 830 + ATTRIBUTE_GROUPS(i2c_dev); 757 831 758 832 struct bus_type i2c_bus_type = { 759 833 .name = "i2c", ··· 739 857 .probe = i2c_device_probe, 740 858 .remove = i2c_device_remove, 741 859 .shutdown = i2c_device_shutdown, 742 - .pm = &i2c_device_pm_ops, 743 860 }; 744 861 EXPORT_SYMBOL_GPL(i2c_bus_type); 745 862 746 863 static struct device_type i2c_client_type = { 747 - .groups = i2c_dev_attr_groups, 864 + .groups = i2c_dev_groups, 748 865 .uevent = i2c_device_uevent, 749 866 .release = i2c_client_dev_release, 750 867 }; ··· 1142 1261 1143 1262 return count; 1144 1263 } 1264 + static DEVICE_ATTR(new_device, S_IWUSR, NULL, i2c_sysfs_new_device); 1145 1265 1146 1266 /* 1147 1267 * And of course let the users delete the devices they instantiated, if ··· 1197 1315 "delete_device"); 1198 1316 return res; 1199 1317 } 1200 - 1201 - static DEVICE_ATTR(new_device, S_IWUSR, NULL, i2c_sysfs_new_device); 1202 1318 static DEVICE_ATTR_IGNORE_LOCKDEP(delete_device, S_IWUSR, NULL, 1203 1319 i2c_sysfs_delete_device); 1204 1320 ··· 1206 1326 &dev_attr_delete_device.attr, 1207 1327 NULL 1208 1328 }; 1209 - 1210 - static struct attribute_group i2c_adapter_attr_group = { 1211 - .attrs = i2c_adapter_attrs, 1212 - }; 1213 - 1214 - static const struct attribute_group *i2c_adapter_attr_groups[] = { 1215 - &i2c_adapter_attr_group, 1216 - NULL 1217 - }; 1329 + ATTRIBUTE_GROUPS(i2c_adapter); 1218 1330 1219 1331 struct device_type i2c_adapter_type = { 1220 - .groups = i2c_adapter_attr_groups, 1332 + .groups = i2c_adapter_groups, 1221 1333 .release = i2c_adapter_dev_release, 1222 1334 }; 1223 1335 EXPORT_SYMBOL_GPL(i2c_adapter_type); ··· 1290 1418 1291 1419 if (of_get_property(node, "wakeup-source", NULL)) 1292 1420 info.flags |= I2C_CLIENT_WAKE; 1293 - 1294 - request_module("%s%s", I2C_MODULE_PREFIX, info.type); 1295 1421 1296 1422 result = i2c_new_device(adap, &info); 1297 1423 if (result == NULL) { ··· 1666 1796 /* device name is gone after device_unregister */ 1667 1797 dev_dbg(&adap->dev, "adapter [%s] unregistered\n", adap->name); 1668 1798 1669 - /* clean up the sysfs representation */ 1799 + /* wait until all references to the device are gone 1800 + * 1801 + * FIXME: This is old code and should ideally be replaced by an 1802 + * alternative which results in decoupling the lifetime of the struct 1803 + * device from the i2c_adapter, like spi or netdev do. Any solution 1804 + * should be throughly tested with DEBUG_KOBJECT_RELEASE enabled! 1805 + */ 1670 1806 init_completion(&adap->dev_released); 1671 1807 device_unregister(&adap->dev); 1672 - 1673 - /* wait for sysfs to drop all references */ 1674 1808 wait_for_completion(&adap->dev_released); 1675 1809 1676 1810 /* free bus id */ ··· 1732 1858 res = driver_register(&driver->driver); 1733 1859 if (res) 1734 1860 return res; 1735 - 1736 - /* Drivers should switch to dev_pm_ops instead. */ 1737 - if (driver->suspend) 1738 - pr_warn("i2c-core: driver [%s] using legacy suspend method\n", 1739 - driver->driver.name); 1740 - if (driver->resume) 1741 - pr_warn("i2c-core: driver [%s] using legacy resume method\n", 1742 - driver->driver.name); 1743 1861 1744 1862 pr_debug("i2c-core: driver [%s] registered\n", driver->driver.name); 1745 1863

+10 -1

drivers/i2c/muxes/i2c-mux-pca954x.c

··· 41 41 #include <linux/i2c-mux.h> 42 42 #include <linux/i2c/pca954x.h> 43 43 #include <linux/module.h> 44 + #include <linux/of.h> 44 45 #include <linux/pm.h> 45 46 #include <linux/slab.h> 46 47 ··· 187 186 { 188 187 struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent); 189 188 struct pca954x_platform_data *pdata = dev_get_platdata(&client->dev); 189 + struct device_node *of_node = client->dev.of_node; 190 + bool idle_disconnect_dt; 190 191 struct gpio_desc *gpio; 191 192 int num, force, class; 192 193 struct pca954x *data; ··· 220 217 data->type = id->driver_data; 221 218 data->last_chan = 0; /* force the first selection */ 222 219 220 + idle_disconnect_dt = of_node && 221 + of_property_read_bool(of_node, "i2c-mux-idle-disconnect"); 222 + 223 223 /* Now create an adapter for each channel */ 224 224 for (num = 0; num < chips[data->type].nchans; num++) { 225 + bool idle_disconnect_pd = false; 226 + 225 227 force = 0; /* dynamic adap number */ 226 228 class = 0; /* no class by default */ 227 229 if (pdata) { ··· 237 229 } else 238 230 /* discard unconfigured channels */ 239 231 break; 232 + idle_disconnect_pd = pdata->modes[num].deselect_on_exit; 240 233 } 241 234 242 235 data->virt_adaps[num] = 243 236 i2c_add_mux_adapter(adap, &client->dev, client, 244 237 force, num, class, pca954x_select_chan, 245 - (pdata && pdata->modes[num].deselect_on_exit) 238 + (idle_disconnect_pd || idle_disconnect_dt) 246 239 ? pca954x_deselect_mux : NULL); 247 240 248 241 if (data->virt_adaps[num] == NULL) {

-4

include/linux/i2c.h

··· 130 130 * @probe: Callback for device binding 131 131 * @remove: Callback for device unbinding 132 132 * @shutdown: Callback for device shutdown 133 - * @suspend: Callback for device suspend 134 - * @resume: Callback for device resume 135 133 * @alert: Alert callback, for example for the SMBus alert protocol 136 134 * @command: Callback for bus-wide signaling (optional) 137 135 * @driver: Device driver model driver ··· 172 174 173 175 /* driver model interfaces that don't relate to enumeration */ 174 176 void (*shutdown)(struct i2c_client *); 175 - int (*suspend)(struct i2c_client *, pm_message_t mesg); 176 - int (*resume)(struct i2c_client *); 177 177 178 178 /* Alert callback, for example for the SMBus alert protocol. 179 179 * The format and meaning of the data value depends on the protocol.

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