Add support for CS42L43B codec to CS42L43 driver

+3

Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml

··· 16 16 DAC for headphone output, two integrated Class D amplifiers for 17 17 loudspeakers, and two ADCs for wired headset microphone input or 18 18 stereo line input. PDM inputs are provided for digital microphones. 19 + CS42L43B variant adds dedicated PDM interface, SoundWire Clock Gearing 20 + support and more decimators to ISRCs. 19 21 20 22 allOf: 21 23 - $ref: dai-common.yaml# ··· 26 24 compatible: 27 25 enum: 28 26 - cirrus,cs42l43 27 + - cirrus,cs42l43b 29 28 30 29 reg: 31 30 maxItems: 1

+5 -2

drivers/mfd/cs42l43-i2c.c

··· 47 47 cs42l43->irq = i2c->irq; 48 48 /* A device on an I2C is always attached by definition. */ 49 49 cs42l43->attached = true; 50 + cs42l43->variant_id = (long)device_get_match_data(cs42l43->dev); 50 51 51 52 cs42l43->regmap = devm_regmap_init_i2c(i2c, &cs42l43_i2c_regmap); 52 53 if (IS_ERR(cs42l43->regmap)) ··· 59 58 60 59 #if IS_ENABLED(CONFIG_OF) 61 60 static const struct of_device_id cs42l43_of_match[] = { 62 - { .compatible = "cirrus,cs42l43", }, 61 + { .compatible = "cirrus,cs42l43", .data = (void *)CS42L43_DEVID_VAL }, 62 + { .compatible = "cirrus,cs42l43b", .data = (void *)CS42L43B_DEVID_VAL }, 63 63 {} 64 64 }; 65 65 MODULE_DEVICE_TABLE(of, cs42l43_of_match); ··· 68 66 69 67 #if IS_ENABLED(CONFIG_ACPI) 70 68 static const struct acpi_device_id cs42l43_acpi_match[] = { 71 - { "CSC4243", 0 }, 69 + { "CSC4243", CS42L43_DEVID_VAL }, 70 + { "CSC2A3B", CS42L43B_DEVID_VAL }, 72 71 {} 73 72 }; 74 73 MODULE_DEVICE_TABLE(acpi, cs42l43_acpi_match);

+3 -1

drivers/mfd/cs42l43-sdw.c

··· 178 178 179 179 cs42l43->dev = dev; 180 180 cs42l43->sdw = sdw; 181 + cs42l43->variant_id = (long)id->driver_data; 181 182 182 183 cs42l43->regmap = devm_regmap_init_sdw(sdw, &cs42l43_sdw_regmap); 183 184 if (IS_ERR(cs42l43->regmap)) ··· 189 188 } 190 189 191 190 static const struct sdw_device_id cs42l43_sdw_id[] = { 192 - SDW_SLAVE_ENTRY(0x01FA, 0x4243, 0), 191 + SDW_SLAVE_ENTRY(0x01FA, 0x4243, (void *) CS42L43_DEVID_VAL), 192 + SDW_SLAVE_ENTRY(0x01FA, 0x2A3B, (void *) CS42L43B_DEVID_VAL), 193 193 {} 194 194 }; 195 195 MODULE_DEVICE_TABLE(sdw, cs42l43_sdw_id);

+80 -13

drivers/mfd/cs42l43.c

··· 115 115 { CS42L43_DECIM_HPF_WNF_CTRL2, 0x00000001 }, 116 116 { CS42L43_DECIM_HPF_WNF_CTRL3, 0x00000001 }, 117 117 { CS42L43_DECIM_HPF_WNF_CTRL4, 0x00000001 }, 118 + { CS42L43B_DECIM_HPF_WNF_CTRL5, 0x00000001 }, 119 + { CS42L43B_DECIM_HPF_WNF_CTRL6, 0x00000001 }, 118 120 { CS42L43_DMIC_PDM_CTRL, 0x00000000 }, 119 121 { CS42L43_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 }, 120 122 { CS42L43_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 }, 123 + { CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 }, 124 + { CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 }, 125 + { CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 0x20122012 }, 121 126 { CS42L43_INTP_VOLUME_CTRL1, 0x00000180 }, 122 127 { CS42L43_INTP_VOLUME_CTRL2, 0x00000180 }, 123 128 { CS42L43_AMP1_2_VOL_RAMP, 0x00000022 }, ··· 160 155 { CS42L43_SWIRE_DP2_CH2_INPUT, 0x00000000 }, 161 156 { CS42L43_SWIRE_DP3_CH1_INPUT, 0x00000000 }, 162 157 { CS42L43_SWIRE_DP3_CH2_INPUT, 0x00000000 }, 158 + { CS42L43B_SWIRE_DP3_CH3_INPUT, 0x00000000 }, 159 + { CS42L43B_SWIRE_DP3_CH4_INPUT, 0x00000000 }, 163 160 { CS42L43_SWIRE_DP4_CH1_INPUT, 0x00000000 }, 164 161 { CS42L43_SWIRE_DP4_CH2_INPUT, 0x00000000 }, 162 + { CS42L43B_SWIRE_DP4_CH3_INPUT, 0x00000000 }, 163 + { CS42L43B_SWIRE_DP4_CH4_INPUT, 0x00000000 }, 165 164 { CS42L43_ASRC_INT1_INPUT1, 0x00000000 }, 166 165 { CS42L43_ASRC_INT2_INPUT1, 0x00000000 }, 167 166 { CS42L43_ASRC_INT3_INPUT1, 0x00000000 }, ··· 178 169 { CS42L43_ISRC1INT2_INPUT1, 0x00000000 }, 179 170 { CS42L43_ISRC1DEC1_INPUT1, 0x00000000 }, 180 171 { CS42L43_ISRC1DEC2_INPUT1, 0x00000000 }, 172 + { CS42L43B_ISRC1DEC3_INPUT1, 0x00000000 }, 173 + { CS42L43B_ISRC1DEC4_INPUT1, 0x00000000 }, 181 174 { CS42L43_ISRC2INT1_INPUT1, 0x00000000 }, 182 175 { CS42L43_ISRC2INT2_INPUT1, 0x00000000 }, 183 176 { CS42L43_ISRC2DEC1_INPUT1, 0x00000000 }, 184 177 { CS42L43_ISRC2DEC2_INPUT1, 0x00000000 }, 178 + { CS42L43B_ISRC2DEC3_INPUT1, 0x00000000 }, 179 + { CS42L43B_ISRC2DEC4_INPUT1, 0x00000000 }, 185 180 { CS42L43_EQ1MIX_INPUT1, 0x00800000 }, 186 181 { CS42L43_EQ1MIX_INPUT2, 0x00800000 }, 187 182 { CS42L43_EQ1MIX_INPUT3, 0x00800000 }, ··· 282 269 283 270 bool cs42l43_readable_register(struct device *dev, unsigned int reg) 284 271 { 272 + struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 273 + 285 274 switch (reg) { 286 275 case CS42L43_DEVID: 287 276 case CS42L43_REVID: ··· 307 292 case CS42L43_ADC_B_CTRL1 ... CS42L43_ADC_B_CTRL2: 308 293 case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4: 309 294 case CS42L43_DMIC_PDM_CTRL: 310 - case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4: 311 295 case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2: 312 296 case CS42L43_AMP1_2_VOL_RAMP: 313 297 case CS42L43_ASP_CTRL: ··· 401 387 case CS42L43_BOOT_CONTROL: 402 388 case CS42L43_BLOCK_EN: 403 389 case CS42L43_SHUTTER_CONTROL: 404 - case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX: 405 - return true; 390 + case CS42L43B_MCU_SW_REV ... CS42L43B_MCU_RAM_MAX: 391 + return true; // registers present on all variants 392 + case CS42L43_MCU_SW_REV ... CS42L43B_MCU_SW_REV - 1: 393 + case CS42L43B_MCU_RAM_MAX + 1 ... CS42L43_MCU_RAM_MAX: 394 + case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4: 395 + return cs42l43->variant_id == CS42L43_DEVID_VAL; // regs only in CS42L43 variant 396 + case CS42L43B_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43B_DECIM_HPF_WNF_CTRL6: 397 + case CS42L43B_SWIRE_DP3_CH3_INPUT ... CS42L43B_SWIRE_DP4_CH4_INPUT: 398 + case CS42L43B_ISRC1DEC3_INPUT1 ... CS42L43B_ISRC2DEC4_INPUT1: 399 + return cs42l43->variant_id == CS42L43B_DEVID_VAL; // regs only in CS42L43B variant 406 400 default: 407 401 return false; 408 402 } ··· 619 597 static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow) 620 598 { 621 599 unsigned int need_reg = CS42L43_NEED_CONFIGS; 600 + unsigned int boot_reg; 622 601 unsigned int val; 623 602 int ret; 624 603 625 - if (shadow) 626 - need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS; 604 + switch (cs42l43->variant_id) { 605 + case CS42L43_DEVID_VAL: 606 + if (shadow) 607 + need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS; 608 + boot_reg = CS42L43_BOOT_STATUS; 609 + break; 610 + case CS42L43B_DEVID_VAL: 611 + need_reg = CS42L43B_NEED_CONFIGS; 612 + boot_reg = CS42L43B_BOOT_STATUS; 613 + break; 614 + default: 615 + return -EINVAL; 616 + } 627 617 628 618 regmap_write(cs42l43->regmap, need_reg, 0); 629 619 630 - ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_BOOT_STATUS, 620 + ret = regmap_read_poll_timeout(cs42l43->regmap, boot_reg, 631 621 val, (val == CS42L43_MCU_BOOT_STAGE3), 632 622 CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US); 633 623 if (ret) { ··· 678 644 */ 679 645 static int cs42l43_mcu_disable(struct cs42l43 *cs42l43) 680 646 { 681 - unsigned int val; 647 + unsigned int val, cfg_reg, ctrl_reg; 682 648 int ret; 683 649 684 - regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG, 685 - CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL); 686 - regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION, 687 - CS42L43_FW_MM_CTRL_MCU_SEL_MASK); 650 + switch (cs42l43->variant_id) { 651 + case CS42L43_DEVID_VAL: 652 + cfg_reg = CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG; 653 + ctrl_reg = CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION; 654 + break; 655 + case CS42L43B_DEVID_VAL: 656 + cfg_reg = CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG; 657 + ctrl_reg = CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION; 658 + break; 659 + default: 660 + return -EINVAL; 661 + } 662 + 663 + regmap_write(cs42l43->regmap, cfg_reg, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL); 664 + regmap_write(cs42l43->regmap, ctrl_reg, CS42L43_FW_MM_CTRL_MCU_SEL_MASK); 665 + 688 666 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK); 689 667 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0); 690 668 ··· 786 740 { 787 741 unsigned int mcu_rev, bios_rev, boot_status, secure_cfg; 788 742 bool patched, shadow; 743 + int boot_status_reg, mcu_sw_rev_reg; 789 744 int ret; 745 + 746 + switch (cs42l43->variant_id) { 747 + case CS42L43_DEVID_VAL: 748 + boot_status_reg = CS42L43_BOOT_STATUS; 749 + mcu_sw_rev_reg = CS42L43_MCU_SW_REV; 750 + break; 751 + case CS42L43B_DEVID_VAL: 752 + boot_status_reg = CS42L43B_BOOT_STATUS; 753 + mcu_sw_rev_reg = CS42L43B_MCU_SW_REV; 754 + break; 755 + default: 756 + return -EINVAL; 757 + } 790 758 791 759 /* Clear any stale software interrupt bits. */ 792 760 regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev); 793 761 794 - ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_STATUS, &boot_status); 762 + ret = regmap_read(cs42l43->regmap, boot_status_reg, &boot_status); 795 763 if (ret) { 796 764 dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret); 797 765 return ret; 798 766 } 799 767 800 - ret = regmap_read(cs42l43->regmap, CS42L43_MCU_SW_REV, &mcu_rev); 768 + ret = regmap_read(cs42l43->regmap, mcu_sw_rev_reg, &mcu_rev); 801 769 if (ret) { 802 770 dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret); 803 771 return ret; ··· 978 918 979 919 switch (devid) { 980 920 case CS42L43_DEVID_VAL: 921 + case CS42L43B_DEVID_VAL: 922 + if (devid != cs42l43->variant_id) { 923 + dev_err(cs42l43->dev, 924 + "Device ID (0x%06x) does not match variant ID (0x%06lx)\n", 925 + devid, cs42l43->variant_id); 926 + goto err; 927 + } 981 928 break; 982 929 default: 983 930 dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid);

+1 -1

drivers/mfd/cs42l43.h

··· 9 9 #ifndef CS42L43_CORE_INT_H 10 10 #define CS42L43_CORE_INT_H 11 11 12 - #define CS42L43_N_DEFAULTS 176 12 + #define CS42L43_N_DEFAULTS 189 13 13 14 14 struct dev_pm_ops; 15 15 struct device;

+76

include/linux/mfd/cs42l43-regs.h

··· 1181 1181 /* CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG */ 1182 1182 #define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL 0xF05AA50F 1183 1183 1184 + /* CS42L43B VARIANT REGISTERS */ 1185 + #define CS42L43B_DEVID_VAL 0x0042A43B 1186 + 1187 + #define CS42L43B_DECIM_VOL_CTRL_CH1_CH2 0x00008280 1188 + #define CS42L43B_DECIM_VOL_CTRL_CH3_CH4 0x00008284 1189 + 1190 + #define CS42L43B_DECIM_VOL_CTRL_CH5_CH6 0x00008290 1191 + #define CS42L43B_DECIM_VOL_CTRL_UPDATE 0x0000829C 1192 + 1193 + #define CS42L43B_DECIM_HPF_WNF_CTRL5 0x000082A0 1194 + #define CS42L43B_DECIM_HPF_WNF_CTRL6 0x000082A4 1195 + 1196 + #define CS42L43B_SWIRE_DP3_CH3_INPUT 0x0000C320 1197 + #define CS42L43B_SWIRE_DP3_CH4_INPUT 0x0000C330 1198 + #define CS42L43B_SWIRE_DP4_CH3_INPUT 0x0000C340 1199 + #define CS42L43B_SWIRE_DP4_CH4_INPUT 0x0000C350 1200 + 1201 + #define CS42L43B_ISRC1DEC3_INPUT1 0x0000C780 1202 + #define CS42L43B_ISRC1DEC4_INPUT1 0x0000C790 1203 + #define CS42L43B_ISRC2DEC3_INPUT1 0x0000C7A0 1204 + #define CS42L43B_ISRC2DEC4_INPUT1 0x0000C7B0 1205 + 1206 + #define CS42L43B_FW_MISSION_CTRL_NEED_CONFIGS 0x00117E00 1207 + #define CS42L43B_FW_MISSION_CTRL_HAVE_CONFIGS 0x00117E04 1208 + #define CS42L43B_FW_MISSION_CTRL_PATCH_START_ADDR_REG 0x00117E08 1209 + #define CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION 0x00117E0C 1210 + #define CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG 0x00117E10 1211 + 1212 + #define CS42L43B_MCU_SW_REV 0x00117314 1213 + #define CS42L43B_PATCH_START_ADDR 0x00117318 1214 + #define CS42L43B_CONFIG_SELECTION 0x0011731C 1215 + #define CS42L43B_NEED_CONFIGS 0x00117320 1216 + #define CS42L43B_BOOT_STATUS 0x00117330 1217 + 1218 + #define CS42L43B_FW_MISSION_CTRL_NEED_CONFIGS 0x00117E00 1219 + #define CS42L43B_FW_MISSION_CTRL_HAVE_CONFIGS 0x00117E04 1220 + #define CS42L43B_FW_MISSION_CTRL_PATCH_START_ADDR_REG 0x00117E08 1221 + #define CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION 0x00117E0C 1222 + #define CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG 0x00117E10 1223 + 1224 + #define CS42L43B_MCU_RAM_MAX 0x00117FFF 1225 + 1226 + /* CS42L43B_DECIM_DECIM_VOL_CTRL_CH5_CH6 */ 1227 + #define CS42L43B_DECIM6_MUTE_MASK 0x80000000 1228 + #define CS42L43B_DECIM6_MUTE_SHIFT 31 1229 + #define CS42L43B_DECIM6_VOL_MASK 0x3FC00000 1230 + #define CS42L43B_DECIM6_VOL_SHIFT 22 1231 + #define CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_MASK 0x00380000 1232 + #define CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_SHIFT 19 1233 + #define CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_MASK 0x00070000 1234 + #define CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_SHIFT 16 1235 + #define CS42L43B_DECIM5_MUTE_MASK 0x00008000 1236 + #define CS42L43B_DECIM5_MUTE_SHIFT 15 1237 + #define CS42L43B_DECIM5_VOL_MASK 0x00003FC0 1238 + #define CS42L43B_DECIM5_VOL_SHIFT 6 1239 + #define CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_MASK 0x00000038 1240 + #define CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_SHIFT 3 1241 + #define CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_MASK 0x00000007 1242 + #define CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_SHIFT 0 1243 + 1244 + /* CS42L43B_DECIM_VOL_CTRL_UPDATE */ 1245 + #define CS42L43B_DECIM6_PATH1_VOL_TRIG_MASK 0x00000800 1246 + #define CS42L43B_DECIM6_PATH1_VOL_TRIG_SHIFT 11 1247 + #define CS42L43B_DECIM5_PATH1_VOL_TRIG_MASK 0x00000100 1248 + #define CS42L43B_DECIM5_PATH1_VOL_TRIG_SHIFT 8 1249 + #define CS42L43B_DECIM4_VOL_UPDATE_MASK 0x00000020 1250 + #define CS42L43B_DECIM4_VOL_UPDATE_SHIFT 5 1251 + 1252 + /* CS42L43_ISRC1_CTRL..CS42L43_ISRC2_CTRL */ 1253 + #define CS42L43B_ISRC_DEC4_EN_MASK 0x00000008 1254 + #define CS42L43B_ISRC_DEC4_EN_SHIFT 3 1255 + #define CS42L43B_ISRC_DEC4_EN_WIDTH 1 1256 + #define CS42L43B_ISRC_DEC3_EN_MASK 0x00000004 1257 + #define CS42L43B_ISRC_DEC3_EN_SHIFT 2 1258 + #define CS42L43B_ISRC_DEC3_EN_WIDTH 1 1259 + 1184 1260 #endif /* CS42L43_CORE_REGS_H */

+1

include/linux/mfd/cs42l43.h

··· 98 98 bool sdw_pll_active; 99 99 bool attached; 100 100 bool hw_lock; 101 + long variant_id; 101 102 }; 102 103 103 104 #endif /* CS42L43_CORE_EXT_H */

+623 -133

sound/soc/codecs/cs42l43.c

··· 45 45 static const struct snd_kcontrol_new cs42l43_##name##_mux = \ 46 46 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum) 47 47 48 + #define CS42L43B_DECL_MUX(name, reg) \ 49 + static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \ 50 + 0, CS42L43_MIXER_SRC_MASK, \ 51 + cs42l43b_mixer_texts, cs42l43b_mixer_values); \ 52 + static const struct snd_kcontrol_new cs42l43_##name##_mux = \ 53 + SOC_DAPM_ENUM("Route", cs42l43_##name##_enum) 54 + 48 55 #define CS42L43_DECL_MIXER(name, reg) \ 49 56 CS42L43_DECL_MUX(name##_in1, reg); \ 50 57 CS42L43_DECL_MUX(name##_in2, reg + 0x4); \ 51 58 CS42L43_DECL_MUX(name##_in3, reg + 0x8); \ 52 59 CS42L43_DECL_MUX(name##_in4, reg + 0xC) 60 + 61 + #define CS42L43B_DECL_MIXER(name, reg) \ 62 + CS42L43B_DECL_MUX(name##_in1, reg); \ 63 + CS42L43B_DECL_MUX(name##_in2, reg + 0x4); \ 64 + CS42L43B_DECL_MUX(name##_in3, reg + 0x8); \ 65 + CS42L43B_DECL_MUX(name##_in4, reg + 0xC) 53 66 54 67 #define CS42L43_DAPM_MUX(name_str, name) \ 55 68 SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux) ··· 112 99 { name_str, "EQ1", "EQ" }, \ 113 100 { name_str, "EQ2", "EQ" } 114 101 102 + #define CS42L43B_BASE_ROUTES(name_str) \ 103 + { name_str, "Decimator 5", "Decimator 5" }, \ 104 + { name_str, "Decimator 6", "Decimator 6" }, \ 105 + { name_str, "ISRC1 DEC3", "ISRC1DEC3" }, \ 106 + { name_str, "ISRC1 DEC4", "ISRC1DEC4" }, \ 107 + { name_str, "ISRC2 DEC3", "ISRC2DEC3" }, \ 108 + { name_str, "ISRC2 DEC4", "ISRC2DEC4" } 109 + 115 110 #define CS42L43_MUX_ROUTES(name_str, widget) \ 116 111 { widget, NULL, name_str " Input" }, \ 117 112 { name_str " Input", NULL, "Mixer Core" }, \ 118 113 CS42L43_BASE_ROUTES(name_str " Input") 114 + 115 + #define CS42L43B_MUX_ROUTES(name_str, widget) \ 116 + CS42L43_MUX_ROUTES(name_str, widget), \ 117 + CS42L43B_BASE_ROUTES(name_str " Input") 119 118 120 119 #define CS42L43_MIXER_ROUTES(name_str, widget) \ 121 120 { name_str " Mixer", NULL, name_str " Input 1" }, \ ··· 140 115 CS42L43_BASE_ROUTES(name_str " Input 2"), \ 141 116 CS42L43_BASE_ROUTES(name_str " Input 3"), \ 142 117 CS42L43_BASE_ROUTES(name_str " Input 4") 118 + 119 + #define CS42L43B_MIXER_ROUTES(name_str, widget) \ 120 + CS42L43_MIXER_ROUTES(name_str, widget), \ 121 + CS42L43B_BASE_ROUTES(name_str " Input 1"), \ 122 + CS42L43B_BASE_ROUTES(name_str " Input 2"), \ 123 + CS42L43B_BASE_ROUTES(name_str " Input 3"), \ 124 + CS42L43B_BASE_ROUTES(name_str " Input 4") 143 125 144 126 #define CS42L43_MIXER_VOLUMES(name_str, base) \ 145 127 SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \ ··· 332 300 struct snd_soc_component *component = dai->component; 333 301 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 334 302 struct cs42l43 *cs42l43 = priv->core; 303 + int ret; 335 304 int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap, 336 305 CS42L43_ASP_CLK_CONFIG2, 337 306 CS42L43_ASP_MASTER_MODE_MASK); ··· 341 308 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK; 342 309 else 343 310 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK; 311 + 312 + if (cs42l43->variant_id == CS42L43_DEVID_VAL && (dai->id == 3 || dai->id == 4)) { 313 + ret = snd_pcm_hw_constraint_minmax(substream->runtime, 314 + SNDRV_PCM_HW_PARAM_CHANNELS, 315 + 1, 2); 316 + if (ret < 0) 317 + return ret; 318 + } 344 319 345 320 return snd_pcm_hw_constraint_list(substream->runtime, 0, 346 321 SNDRV_PCM_HW_PARAM_RATE, ··· 631 590 "Decimator 2 Switch", 632 591 "Decimator 3 Switch", 633 592 "Decimator 4 Switch", 593 + "Decimator 5 Switch", 594 + "Decimator 6 Switch", 634 595 }; 635 - int i; 596 + int control_size, i; 636 597 637 598 static_assert(ARRAY_SIZE(controls) == ARRAY_SIZE(priv->kctl)); 638 599 639 - for (i = 0; i < ARRAY_SIZE(controls); i++) { 600 + switch (priv->core->variant_id) { 601 + case CS42L43_DEVID_VAL: 602 + control_size = ARRAY_SIZE(controls) - 2; // ignore Decimator 5 and 6 603 + break; 604 + case CS42L43B_DEVID_VAL: 605 + control_size = ARRAY_SIZE(controls); 606 + break; 607 + default: 608 + return -EINVAL; 609 + } 610 + 611 + for (i = 0; i < control_size; i++) { 640 612 if (priv->kctl[i]) 641 613 continue; 642 614 ··· 757 703 .capture = { 758 704 .stream_name = "DP3 Capture", 759 705 .channels_min = 1, 760 - .channels_max = 2, 706 + .channels_max = 4, 761 707 .rates = SNDRV_PCM_RATE_KNOT, 762 708 .formats = CS42L43_SDW_FORMATS, 763 709 }, ··· 769 715 .capture = { 770 716 .stream_name = "DP4 Capture", 771 717 .channels_min = 1, 772 - .channels_max = 2, 718 + .channels_max = 4, 773 719 .rates = SNDRV_PCM_RATE_KNOT, 774 720 .formats = CS42L43_SDW_FORMATS, 775 721 }, ··· 862 808 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 863 809 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, 864 810 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 811 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_wnf_corner, CS42L43B_DECIM_HPF_WNF_CTRL5, 812 + CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 813 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_wnf_corner, CS42L43B_DECIM_HPF_WNF_CTRL6, 814 + CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 865 815 866 816 static const char * const cs42l43_hpf_corner_text[] = { 867 817 "3Hz", "12Hz", "48Hz", "96Hz", ··· 878 820 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3, 879 821 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 880 822 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, 823 + CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 824 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_hpf_corner, CS42L43B_DECIM_HPF_WNF_CTRL5, 825 + CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 826 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_hpf_corner, CS42L43B_DECIM_HPF_WNF_CTRL6, 881 827 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 882 828 883 829 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, ··· 900 838 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text); 901 839 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 902 840 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text); 841 + 842 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec1_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 843 + CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text); 844 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec1_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 845 + CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text); 846 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec2_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 847 + CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text); 848 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec2_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 849 + CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text); 850 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec3_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 851 + CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text); 852 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec3_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 853 + CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text); 854 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec4_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 855 + CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text); 856 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec4_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 857 + CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text); 858 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 859 + CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_SHIFT, cs42l43_ramp_text); 860 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 861 + CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_SHIFT, cs42l43_ramp_text); 862 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 863 + CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_SHIFT, cs42l43_ramp_text); 864 + static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 865 + CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_SHIFT, cs42l43_ramp_text); 903 866 904 867 static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0); 905 868 ··· 985 898 0x58, 0x59, // EQ1, 2 986 899 }; 987 900 901 + static const char * const cs42l43b_mixer_texts[] = { 902 + "None", 903 + "Tone Generator 1", "Tone Generator 2", 904 + "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4", "Decimator 5", "Decimator 6", 905 + "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6", 906 + "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2", 907 + "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4", 908 + "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4", 909 + "ISRC1 INT1", "ISRC1 INT2", 910 + "ISRC1 DEC1", "ISRC1 DEC2", "ISRC1 DEC3", "ISRC1 DEC4", 911 + "ISRC2 INT1", "ISRC2 INT2", 912 + "ISRC2 DEC1", "ISRC2 DEC2", "ISRC2 DEC3", "ISRC2 DEC4", 913 + "EQ1", "EQ2", 914 + }; 915 + 916 + static const unsigned int cs42l43b_mixer_values[] = { 917 + 0x00, // None 918 + 0x04, 0x05, // Tone Generator 1, 2 919 + 0x10, 0x11, 0x80, 0x81, 0x12, 0x13, // Decimator 1, 2, 3, 4, 5, 6 920 + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6 921 + 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2 922 + 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4 923 + 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4 924 + 0x50, 0x51, // ISRC1 INT1, 2 925 + 0x52, 0x53, 0x78, 0x79, // ISRC1 DEC1, 2, 3, 4 926 + 0x54, 0x55, // ISRC2 INT1, 2 927 + 0x56, 0x57, 0x7A, 0x7B, // ISRC2 DEC1, 2, 3, 4 928 + 0x58, 0x59, // EQ1, 2 929 + }; 930 + 931 + /* A variant */ 988 932 CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT); 989 933 CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT); 990 934 CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT); ··· 1063 945 1064 946 CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1); 1065 947 CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1); 948 + 949 + /* B variant */ 950 + CS42L43B_DECL_MUX(b_asptx1, CS42L43_ASPTX1_INPUT); 951 + CS42L43B_DECL_MUX(b_asptx2, CS42L43_ASPTX2_INPUT); 952 + CS42L43B_DECL_MUX(b_asptx3, CS42L43_ASPTX3_INPUT); 953 + CS42L43B_DECL_MUX(b_asptx4, CS42L43_ASPTX4_INPUT); 954 + CS42L43B_DECL_MUX(b_asptx5, CS42L43_ASPTX5_INPUT); 955 + CS42L43B_DECL_MUX(b_asptx6, CS42L43_ASPTX6_INPUT); 956 + 957 + CS42L43B_DECL_MUX(b_dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT); 958 + CS42L43B_DECL_MUX(b_dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT); 959 + CS42L43B_DECL_MUX(b_dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT); 960 + CS42L43B_DECL_MUX(b_dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT); 961 + CS42L43B_DECL_MUX(b_dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT); 962 + CS42L43B_DECL_MUX(b_dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT); 963 + CS42L43B_DECL_MUX(b_dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT); 964 + CS42L43B_DECL_MUX(b_dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT); 965 + CS42L43B_DECL_MUX(b_dp3tx3, CS42L43B_SWIRE_DP3_CH3_INPUT); 966 + CS42L43B_DECL_MUX(b_dp3tx4, CS42L43B_SWIRE_DP3_CH4_INPUT); 967 + CS42L43B_DECL_MUX(b_dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT); 968 + CS42L43B_DECL_MUX(b_dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT); 969 + CS42L43B_DECL_MUX(b_dp4tx3, CS42L43B_SWIRE_DP4_CH3_INPUT); 970 + CS42L43B_DECL_MUX(b_dp4tx4, CS42L43B_SWIRE_DP4_CH4_INPUT); 971 + 972 + CS42L43B_DECL_MUX(b_asrcint1, CS42L43_ASRC_INT1_INPUT1); 973 + CS42L43B_DECL_MUX(b_asrcint2, CS42L43_ASRC_INT2_INPUT1); 974 + CS42L43B_DECL_MUX(b_asrcint3, CS42L43_ASRC_INT3_INPUT1); 975 + CS42L43B_DECL_MUX(b_asrcint4, CS42L43_ASRC_INT4_INPUT1); 976 + CS42L43B_DECL_MUX(b_asrcdec1, CS42L43_ASRC_DEC1_INPUT1); 977 + CS42L43B_DECL_MUX(b_asrcdec2, CS42L43_ASRC_DEC2_INPUT1); 978 + CS42L43B_DECL_MUX(b_asrcdec3, CS42L43_ASRC_DEC3_INPUT1); 979 + CS42L43B_DECL_MUX(b_asrcdec4, CS42L43_ASRC_DEC4_INPUT1); 980 + 981 + CS42L43B_DECL_MUX(b_isrc1int1, CS42L43_ISRC1INT1_INPUT1); 982 + CS42L43B_DECL_MUX(b_isrc1int2, CS42L43_ISRC1INT2_INPUT1); 983 + CS42L43B_DECL_MUX(b_isrc1dec1, CS42L43_ISRC1DEC1_INPUT1); 984 + CS42L43B_DECL_MUX(b_isrc1dec2, CS42L43_ISRC1DEC2_INPUT1); 985 + CS42L43B_DECL_MUX(b_isrc1dec3, CS42L43B_ISRC1DEC3_INPUT1); 986 + CS42L43B_DECL_MUX(b_isrc1dec4, CS42L43B_ISRC1DEC4_INPUT1); 987 + CS42L43B_DECL_MUX(b_isrc2int1, CS42L43_ISRC2INT1_INPUT1); 988 + CS42L43B_DECL_MUX(b_isrc2int2, CS42L43_ISRC2INT2_INPUT1); 989 + CS42L43B_DECL_MUX(b_isrc2dec1, CS42L43_ISRC2DEC1_INPUT1); 990 + CS42L43B_DECL_MUX(b_isrc2dec2, CS42L43_ISRC2DEC2_INPUT1); 991 + CS42L43B_DECL_MUX(b_isrc2dec3, CS42L43B_ISRC2DEC3_INPUT1); 992 + CS42L43B_DECL_MUX(b_isrc2dec4, CS42L43B_ISRC2DEC4_INPUT1); 993 + 994 + CS42L43B_DECL_MUX(b_spdif1, CS42L43_SPDIF1_INPUT1); 995 + CS42L43B_DECL_MUX(b_spdif2, CS42L43_SPDIF2_INPUT1); 996 + 997 + CS42L43B_DECL_MIXER(b_eq1, CS42L43_EQ1MIX_INPUT1); 998 + CS42L43B_DECL_MIXER(b_eq2, CS42L43_EQ2MIX_INPUT1); 999 + 1000 + CS42L43B_DECL_MIXER(b_amp1, CS42L43_AMP1MIX_INPUT1); 1001 + CS42L43B_DECL_MIXER(b_amp2, CS42L43_AMP2MIX_INPUT1); 1002 + 1003 + CS42L43B_DECL_MIXER(b_amp3, CS42L43_AMP3MIX_INPUT1); 1004 + CS42L43B_DECL_MIXER(b_amp4, CS42L43_AMP4MIX_INPUT1); 1066 1005 1067 1006 static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol, 1068 1007 struct snd_ctl_elem_value *ucontrol) ··· 1348 1173 SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner), 1349 1174 SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner), 1350 1175 SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner), 1351 - 1352 - SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1353 - CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1354 - SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1355 - CS42L43_DECIM1_MUTE_SHIFT, 1, 1, 1356 - cs42l43_decim_get, cs42l43_dapm_put_volsw), 1357 - SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1358 - CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1359 - SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1360 - CS42L43_DECIM2_MUTE_SHIFT, 1, 1, 1361 - cs42l43_decim_get, cs42l43_dapm_put_volsw), 1362 - SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1363 - CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1364 - SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1365 - CS42L43_DECIM3_MUTE_SHIFT, 1, 1, 1366 - cs42l43_decim_get, cs42l43_dapm_put_volsw), 1367 - SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1368 - CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1369 - SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1370 - CS42L43_DECIM4_MUTE_SHIFT, 1, 1, 1371 - cs42l43_decim_get, cs42l43_dapm_put_volsw), 1372 - 1373 - SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up, 1374 - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1375 - SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down, 1376 - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1377 - SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up, 1378 - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1379 - SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down, 1380 - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1381 - SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up, 1382 - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1383 - SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down, 1384 - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1385 - SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up, 1386 - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1387 - SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down, 1388 - cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1389 1176 1390 1177 SOC_DOUBLE_R_EXT("Speaker Digital Switch", 1391 1178 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, ··· 1738 1601 unsigned int *val; 1739 1602 int ret; 1740 1603 1741 - switch (w->shift) { 1742 - case CS42L43_ADC1_EN_SHIFT: 1743 - case CS42L43_PDM1_DIN_L_EN_SHIFT: 1744 - reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1745 - ramp = CS42L43_DECIM1_VD_RAMP_MASK; 1746 - mute = CS42L43_DECIM1_MUTE_MASK; 1747 - val = &priv->decim_cache[0]; 1748 - break; 1749 - case CS42L43_ADC2_EN_SHIFT: 1750 - case CS42L43_PDM1_DIN_R_EN_SHIFT: 1751 - reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1752 - ramp = CS42L43_DECIM2_VD_RAMP_MASK; 1753 - mute = CS42L43_DECIM2_MUTE_MASK; 1754 - val = &priv->decim_cache[1]; 1755 - break; 1756 - case CS42L43_PDM2_DIN_L_EN_SHIFT: 1757 - reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1758 - ramp = CS42L43_DECIM3_VD_RAMP_MASK; 1759 - mute = CS42L43_DECIM3_MUTE_MASK; 1760 - val = &priv->decim_cache[2]; 1761 - break; 1762 - case CS42L43_PDM2_DIN_R_EN_SHIFT: 1763 - reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1764 - ramp = CS42L43_DECIM4_VD_RAMP_MASK; 1765 - mute = CS42L43_DECIM4_MUTE_MASK; 1766 - val = &priv->decim_cache[3]; 1767 - break; 1768 - default: 1769 - dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); 1604 + if (cs42l43->variant_id == CS42L43_DEVID_VAL) { 1605 + switch (w->shift) { 1606 + case CS42L43_ADC1_EN_SHIFT: 1607 + case CS42L43_PDM1_DIN_L_EN_SHIFT: 1608 + reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1609 + ramp = CS42L43_DECIM1_VD_RAMP_MASK; 1610 + mute = CS42L43_DECIM1_MUTE_MASK; 1611 + val = &priv->decim_cache[0]; 1612 + break; 1613 + case CS42L43_ADC2_EN_SHIFT: 1614 + case CS42L43_PDM1_DIN_R_EN_SHIFT: 1615 + reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1616 + ramp = CS42L43_DECIM2_VD_RAMP_MASK; 1617 + mute = CS42L43_DECIM2_MUTE_MASK; 1618 + val = &priv->decim_cache[1]; 1619 + break; 1620 + case CS42L43_PDM2_DIN_L_EN_SHIFT: 1621 + reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1622 + ramp = CS42L43_DECIM3_VD_RAMP_MASK; 1623 + mute = CS42L43_DECIM3_MUTE_MASK; 1624 + val = &priv->decim_cache[2]; 1625 + break; 1626 + case CS42L43_PDM2_DIN_R_EN_SHIFT: 1627 + reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1628 + ramp = CS42L43_DECIM4_VD_RAMP_MASK; 1629 + mute = CS42L43_DECIM4_MUTE_MASK; 1630 + val = &priv->decim_cache[3]; 1631 + break; 1632 + default: 1633 + dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); 1634 + return -EINVAL; 1635 + } 1636 + } else if (cs42l43->variant_id == CS42L43B_DEVID_VAL) { 1637 + switch (w->shift) { 1638 + case CS42L43_ADC1_EN_SHIFT: 1639 + reg = CS42L43B_DECIM_VOL_CTRL_CH1_CH2; 1640 + ramp = CS42L43_DECIM1_VD_RAMP_MASK; 1641 + mute = CS42L43_DECIM1_MUTE_MASK; 1642 + val = &priv->decim_cache[0]; 1643 + break; 1644 + case CS42L43_ADC2_EN_SHIFT: 1645 + reg = CS42L43B_DECIM_VOL_CTRL_CH1_CH2; 1646 + ramp = CS42L43_DECIM2_VD_RAMP_MASK; 1647 + mute = CS42L43_DECIM2_MUTE_MASK; 1648 + val = &priv->decim_cache[1]; 1649 + break; 1650 + case CS42L43_PDM1_DIN_L_EN_SHIFT: 1651 + reg = CS42L43B_DECIM_VOL_CTRL_CH3_CH4; 1652 + ramp = CS42L43_DECIM3_VD_RAMP_MASK; 1653 + mute = CS42L43_DECIM3_MUTE_MASK; 1654 + val = &priv->decim_cache[2]; 1655 + break; 1656 + case CS42L43_PDM1_DIN_R_EN_SHIFT: 1657 + reg = CS42L43B_DECIM_VOL_CTRL_CH3_CH4; 1658 + ramp = CS42L43_DECIM4_VD_RAMP_MASK; 1659 + mute = CS42L43_DECIM4_MUTE_MASK; 1660 + val = &priv->decim_cache[3]; 1661 + break; 1662 + case CS42L43_PDM2_DIN_L_EN_SHIFT: 1663 + reg = CS42L43B_DECIM_VOL_CTRL_CH5_CH6; 1664 + ramp = CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_MASK; 1665 + mute = CS42L43B_DECIM5_MUTE_MASK; 1666 + val = &priv->decim_cache[4]; 1667 + break; 1668 + case CS42L43_PDM2_DIN_R_EN_SHIFT: 1669 + reg = CS42L43B_DECIM_VOL_CTRL_CH5_CH6; 1670 + ramp = CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_MASK; 1671 + mute = CS42L43B_DECIM6_MUTE_MASK; 1672 + val = &priv->decim_cache[5]; 1673 + break; 1674 + default: 1675 + dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); 1676 + return -EINVAL; 1677 + } 1678 + } else { 1770 1679 return -EINVAL; 1771 1680 } 1772 1681 ··· 1904 1721 SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT, 1905 1722 0, NULL, 0, cs42l43_mic_ev, 1906 1723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1907 - 1908 - SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0, 1909 - &cs42l43_dec_mode_ctl[0]), 1910 - SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0, 1911 - &cs42l43_dec_mode_ctl[1]), 1912 1724 1913 1725 SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0), 1914 1726 SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0), ··· 2049 1871 2050 1872 SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT, 2051 1873 0, NULL, 0), 2052 - CS42L43_DAPM_MUX("ASPTX1", asptx1), 2053 - CS42L43_DAPM_MUX("ASPTX2", asptx2), 2054 - CS42L43_DAPM_MUX("ASPTX3", asptx3), 2055 - CS42L43_DAPM_MUX("ASPTX4", asptx4), 2056 - CS42L43_DAPM_MUX("ASPTX5", asptx5), 2057 - CS42L43_DAPM_MUX("ASPTX6", asptx6), 2058 - 2059 - CS42L43_DAPM_MUX("DP1TX1", dp1tx1), 2060 - CS42L43_DAPM_MUX("DP1TX2", dp1tx2), 2061 - CS42L43_DAPM_MUX("DP1TX3", dp1tx3), 2062 - CS42L43_DAPM_MUX("DP1TX4", dp1tx4), 2063 - CS42L43_DAPM_MUX("DP2TX1", dp2tx1), 2064 - CS42L43_DAPM_MUX("DP2TX2", dp2tx2), 2065 - CS42L43_DAPM_MUX("DP3TX1", dp3tx1), 2066 - CS42L43_DAPM_MUX("DP3TX2", dp3tx2), 2067 - CS42L43_DAPM_MUX("DP4TX1", dp4tx1), 2068 - CS42L43_DAPM_MUX("DP4TX2", dp4tx2), 2069 - 2070 - CS42L43_DAPM_MUX("ASRC INT1", asrcint1), 2071 - CS42L43_DAPM_MUX("ASRC INT2", asrcint2), 2072 - CS42L43_DAPM_MUX("ASRC INT3", asrcint3), 2073 - CS42L43_DAPM_MUX("ASRC INT4", asrcint4), 2074 - CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1), 2075 - CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2), 2076 - CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3), 2077 - CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4), 2078 - 2079 - CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1), 2080 - CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2), 2081 - CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1), 2082 - CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2), 2083 - CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1), 2084 - CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2), 2085 - CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1), 2086 - CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2), 2087 - 2088 - CS42L43_DAPM_MUX("SPDIF1", spdif1), 2089 - CS42L43_DAPM_MUX("SPDIF2", spdif2), 2090 - 2091 - CS42L43_DAPM_MIXER("EQ1", eq1), 2092 - CS42L43_DAPM_MIXER("EQ2", eq2), 2093 - 2094 - CS42L43_DAPM_MIXER("Speaker L", amp1), 2095 - CS42L43_DAPM_MIXER("Speaker R", amp2), 2096 - 2097 - CS42L43_DAPM_MIXER("Headphone L", amp3), 2098 - CS42L43_DAPM_MIXER("Headphone R", amp4), 2099 1874 }; 2100 1875 2101 1876 static const struct snd_soc_dapm_route cs42l43_routes[] = { ··· 2093 1962 { "PDM1R", NULL, "PDM1_DIN" }, 2094 1963 { "PDM2L", NULL, "PDM2_DIN" }, 2095 1964 { "PDM2R", NULL, "PDM2_DIN" }, 2096 - 2097 - { "Decimator 1 Mode", "PDM", "PDM1L" }, 2098 - { "Decimator 1 Mode", "ADC", "ADC1" }, 2099 - { "Decimator 2 Mode", "PDM", "PDM1R" }, 2100 - { "Decimator 2 Mode", "ADC", "ADC2" }, 2101 - 2102 - { "Decimator 1", NULL, "Decimator 1 Mode" }, 2103 - { "Decimator 2", NULL, "Decimator 2 Mode" }, 2104 - { "Decimator 3", NULL, "PDM2L" }, 2105 - { "Decimator 4", NULL, "PDM2R" }, 2106 1965 2107 1966 { "ASP Capture", NULL, "ASPTX1" }, 2108 1967 { "ASP Capture", NULL, "ASPTX2" }, ··· 2181 2060 { "ASRC_DEC4", NULL, "ASRC_DEC" }, 2182 2061 2183 2062 { "EQ", NULL, "EQ Clock" }, 2063 + }; 2064 + 2065 + static const struct snd_kcontrol_new cs42l43_a_controls[] = { 2066 + SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up, 2067 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2068 + SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down, 2069 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2070 + SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up, 2071 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2072 + SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down, 2073 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2074 + SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up, 2075 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2076 + SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down, 2077 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2078 + SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up, 2079 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2080 + SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down, 2081 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2082 + 2083 + SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 2084 + CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2085 + SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 2086 + CS42L43_DECIM1_MUTE_SHIFT, 1, 1, 2087 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2088 + SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 2089 + CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2090 + SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 2091 + CS42L43_DECIM2_MUTE_SHIFT, 1, 1, 2092 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2093 + SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 2094 + CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2095 + SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 2096 + CS42L43_DECIM3_MUTE_SHIFT, 1, 1, 2097 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2098 + SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 2099 + CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2100 + SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 2101 + CS42L43_DECIM4_MUTE_SHIFT, 1, 1, 2102 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2103 + }; 2104 + 2105 + static const struct snd_kcontrol_new cs42l43_b_controls[] = { 2106 + SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 2107 + CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2108 + SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 2109 + CS42L43_DECIM1_MUTE_SHIFT, 1, 1, 2110 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2111 + SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 2112 + CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2113 + SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 2114 + CS42L43_DECIM2_MUTE_SHIFT, 1, 1, 2115 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2116 + SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 2117 + CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2118 + SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 2119 + CS42L43_DECIM3_MUTE_SHIFT, 1, 1, 2120 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2121 + SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 2122 + CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2123 + SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 2124 + CS42L43_DECIM4_MUTE_SHIFT, 1, 1, 2125 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2126 + SOC_SINGLE_TLV("Decimator 5 Volume", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 2127 + CS42L43B_DECIM5_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2128 + SOC_SINGLE_EXT("Decimator 5 Switch", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 2129 + CS42L43B_DECIM5_MUTE_SHIFT, 1, 1, 2130 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2131 + SOC_SINGLE_TLV("Decimator 6 Volume", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 2132 + CS42L43B_DECIM6_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 2133 + SOC_SINGLE_EXT("Decimator 6 Switch", CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 2134 + CS42L43B_DECIM6_MUTE_SHIFT, 1, 1, 2135 + cs42l43_decim_get, cs42l43_dapm_put_volsw), 2136 + 2137 + SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43b_dec1_ramp_up, 2138 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2139 + SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43b_dec1_ramp_down, 2140 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2141 + SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43b_dec2_ramp_up, 2142 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2143 + SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43b_dec2_ramp_down, 2144 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2145 + SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43b_dec3_ramp_up, 2146 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2147 + SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43b_dec3_ramp_down, 2148 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2149 + SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43b_dec4_ramp_up, 2150 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2151 + SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43b_dec4_ramp_down, 2152 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2153 + SOC_ENUM_EXT("Decimator 5 Ramp Up", cs42l43b_dec5_ramp_up, 2154 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2155 + SOC_ENUM_EXT("Decimator 5 Ramp Down", cs42l43b_dec5_ramp_down, 2156 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2157 + SOC_ENUM_EXT("Decimator 6 Ramp Up", cs42l43b_dec6_ramp_up, 2158 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2159 + SOC_ENUM_EXT("Decimator 6 Ramp Down", cs42l43b_dec6_ramp_down, 2160 + cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 2161 + 2162 + SOC_SINGLE("Decimator 5 WNF Switch", CS42L43B_DECIM_HPF_WNF_CTRL5, 2163 + CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 2164 + SOC_SINGLE("Decimator 6 WNF Switch", CS42L43B_DECIM_HPF_WNF_CTRL6, 2165 + CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 2166 + 2167 + SOC_ENUM("Decimator 5 WNF Corner Frequency", cs42l43b_dec5_wnf_corner), 2168 + SOC_ENUM("Decimator 6 WNF Corner Frequency", cs42l43b_dec6_wnf_corner), 2169 + 2170 + SOC_SINGLE("Decimator 5 HPF Switch", CS42L43B_DECIM_HPF_WNF_CTRL5, 2171 + CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 2172 + SOC_SINGLE("Decimator 6 HPF Switch", CS42L43B_DECIM_HPF_WNF_CTRL6, 2173 + CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 2174 + 2175 + SOC_ENUM("Decimator 5 HPF Corner Frequency", cs42l43b_dec5_hpf_corner), 2176 + SOC_ENUM("Decimator 6 HPF Corner Frequency", cs42l43b_dec6_hpf_corner), 2177 + }; 2178 + 2179 + static const struct snd_soc_dapm_widget cs42l43_a_widgets[] = { 2180 + SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0, 2181 + &cs42l43_dec_mode_ctl[0]), 2182 + SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0, 2183 + &cs42l43_dec_mode_ctl[1]), 2184 + CS42L43_DAPM_MUX("ASPTX1", asptx1), 2185 + CS42L43_DAPM_MUX("ASPTX2", asptx2), 2186 + CS42L43_DAPM_MUX("ASPTX3", asptx3), 2187 + CS42L43_DAPM_MUX("ASPTX4", asptx4), 2188 + CS42L43_DAPM_MUX("ASPTX5", asptx5), 2189 + CS42L43_DAPM_MUX("ASPTX6", asptx6), 2190 + 2191 + CS42L43_DAPM_MUX("DP1TX1", dp1tx1), 2192 + CS42L43_DAPM_MUX("DP1TX2", dp1tx2), 2193 + CS42L43_DAPM_MUX("DP1TX3", dp1tx3), 2194 + CS42L43_DAPM_MUX("DP1TX4", dp1tx4), 2195 + CS42L43_DAPM_MUX("DP2TX1", dp2tx1), 2196 + CS42L43_DAPM_MUX("DP2TX2", dp2tx2), 2197 + CS42L43_DAPM_MUX("DP3TX1", dp3tx1), 2198 + CS42L43_DAPM_MUX("DP3TX2", dp3tx2), 2199 + CS42L43_DAPM_MUX("DP4TX1", dp4tx1), 2200 + CS42L43_DAPM_MUX("DP4TX2", dp4tx2), 2201 + 2202 + CS42L43_DAPM_MUX("ASRC INT1", asrcint1), 2203 + CS42L43_DAPM_MUX("ASRC INT2", asrcint2), 2204 + CS42L43_DAPM_MUX("ASRC INT3", asrcint3), 2205 + CS42L43_DAPM_MUX("ASRC INT4", asrcint4), 2206 + CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1), 2207 + CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2), 2208 + CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3), 2209 + CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4), 2210 + 2211 + CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1), 2212 + CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2), 2213 + CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1), 2214 + CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2), 2215 + CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1), 2216 + CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2), 2217 + CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1), 2218 + CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2), 2219 + 2220 + CS42L43_DAPM_MUX("SPDIF1", spdif1), 2221 + CS42L43_DAPM_MUX("SPDIF2", spdif2), 2222 + 2223 + CS42L43_DAPM_MIXER("EQ1", eq1), 2224 + CS42L43_DAPM_MIXER("EQ2", eq2), 2225 + 2226 + CS42L43_DAPM_MIXER("Speaker L", amp1), 2227 + CS42L43_DAPM_MIXER("Speaker R", amp2), 2228 + 2229 + CS42L43_DAPM_MIXER("Headphone L", amp3), 2230 + CS42L43_DAPM_MIXER("Headphone R", amp4), 2231 + }; 2232 + 2233 + static const struct snd_soc_dapm_widget cs42l43_b_widgets[] = { 2234 + SND_SOC_DAPM_AIF_OUT("DP3TX3", NULL, 2, SND_SOC_NOPM, 0, 0), 2235 + SND_SOC_DAPM_AIF_OUT("DP3TX4", NULL, 3, SND_SOC_NOPM, 0, 0), 2236 + SND_SOC_DAPM_AIF_OUT("DP4TX3", NULL, 2, SND_SOC_NOPM, 0, 0), 2237 + SND_SOC_DAPM_AIF_OUT("DP4TX4", NULL, 3, SND_SOC_NOPM, 0, 0), 2238 + 2239 + SND_SOC_DAPM_PGA("Decimator 5", SND_SOC_NOPM, 0, 0, NULL, 0), 2240 + SND_SOC_DAPM_PGA("Decimator 6", SND_SOC_NOPM, 0, 0, NULL, 0), 2241 + 2242 + SND_SOC_DAPM_PGA("ISRC1DEC3", CS42L43_ISRC1_CTRL, 2243 + CS42L43B_ISRC_DEC3_EN_SHIFT, 0, NULL, 0), 2244 + SND_SOC_DAPM_PGA("ISRC1DEC4", CS42L43_ISRC1_CTRL, 2245 + CS42L43B_ISRC_DEC4_EN_SHIFT, 0, NULL, 0), 2246 + SND_SOC_DAPM_PGA("ISRC2DEC3", CS42L43_ISRC2_CTRL, 2247 + CS42L43B_ISRC_DEC3_EN_SHIFT, 0, NULL, 0), 2248 + SND_SOC_DAPM_PGA("ISRC2DEC4", CS42L43_ISRC2_CTRL, 2249 + CS42L43B_ISRC_DEC4_EN_SHIFT, 0, NULL, 0), 2250 + 2251 + CS42L43_DAPM_MUX("ASPTX1", b_asptx1), 2252 + CS42L43_DAPM_MUX("ASPTX2", b_asptx2), 2253 + CS42L43_DAPM_MUX("ASPTX3", b_asptx3), 2254 + CS42L43_DAPM_MUX("ASPTX4", b_asptx4), 2255 + CS42L43_DAPM_MUX("ASPTX5", b_asptx5), 2256 + CS42L43_DAPM_MUX("ASPTX6", b_asptx6), 2257 + 2258 + CS42L43_DAPM_MUX("DP1TX1", b_dp1tx1), 2259 + CS42L43_DAPM_MUX("DP1TX2", b_dp1tx2), 2260 + CS42L43_DAPM_MUX("DP1TX3", b_dp1tx3), 2261 + CS42L43_DAPM_MUX("DP1TX4", b_dp1tx4), 2262 + CS42L43_DAPM_MUX("DP2TX1", b_dp2tx1), 2263 + CS42L43_DAPM_MUX("DP2TX2", b_dp2tx2), 2264 + CS42L43_DAPM_MUX("DP3TX1", b_dp3tx1), 2265 + CS42L43_DAPM_MUX("DP3TX2", b_dp3tx2), 2266 + CS42L43_DAPM_MUX("DP3TX3", b_dp3tx3), 2267 + CS42L43_DAPM_MUX("DP3TX4", b_dp3tx4), 2268 + CS42L43_DAPM_MUX("DP4TX1", b_dp4tx1), 2269 + CS42L43_DAPM_MUX("DP4TX2", b_dp4tx2), 2270 + CS42L43_DAPM_MUX("DP4TX3", b_dp4tx3), 2271 + CS42L43_DAPM_MUX("DP4TX4", b_dp4tx4), 2272 + 2273 + CS42L43_DAPM_MUX("ASRC INT1", b_asrcint1), 2274 + CS42L43_DAPM_MUX("ASRC INT2", b_asrcint2), 2275 + CS42L43_DAPM_MUX("ASRC INT3", b_asrcint3), 2276 + CS42L43_DAPM_MUX("ASRC INT4", b_asrcint4), 2277 + CS42L43_DAPM_MUX("ASRC DEC1", b_asrcdec1), 2278 + CS42L43_DAPM_MUX("ASRC DEC2", b_asrcdec2), 2279 + CS42L43_DAPM_MUX("ASRC DEC3", b_asrcdec3), 2280 + CS42L43_DAPM_MUX("ASRC DEC4", b_asrcdec4), 2281 + 2282 + CS42L43_DAPM_MUX("ISRC1INT1", b_isrc1int1), 2283 + CS42L43_DAPM_MUX("ISRC1INT2", b_isrc1int2), 2284 + CS42L43_DAPM_MUX("ISRC1DEC1", b_isrc1dec1), 2285 + CS42L43_DAPM_MUX("ISRC1DEC2", b_isrc1dec2), 2286 + CS42L43_DAPM_MUX("ISRC1DEC3", b_isrc1dec3), 2287 + CS42L43_DAPM_MUX("ISRC1DEC4", b_isrc1dec4), 2288 + CS42L43_DAPM_MUX("ISRC2INT1", b_isrc2int1), 2289 + CS42L43_DAPM_MUX("ISRC2INT2", b_isrc2int2), 2290 + CS42L43_DAPM_MUX("ISRC2DEC1", b_isrc2dec1), 2291 + CS42L43_DAPM_MUX("ISRC2DEC2", b_isrc2dec2), 2292 + CS42L43_DAPM_MUX("ISRC2DEC3", b_isrc2dec3), 2293 + CS42L43_DAPM_MUX("ISRC2DEC4", b_isrc2dec4), 2294 + 2295 + CS42L43_DAPM_MUX("SPDIF1", b_spdif1), 2296 + CS42L43_DAPM_MUX("SPDIF2", b_spdif2), 2297 + 2298 + CS42L43_DAPM_MIXER("EQ1", b_eq1), 2299 + CS42L43_DAPM_MIXER("EQ2", b_eq2), 2300 + 2301 + CS42L43_DAPM_MIXER("Speaker L", b_amp1), 2302 + CS42L43_DAPM_MIXER("Speaker R", b_amp2), 2303 + 2304 + CS42L43_DAPM_MIXER("Headphone L", b_amp3), 2305 + CS42L43_DAPM_MIXER("Headphone R", b_amp4), 2306 + }; 2307 + 2308 + static const struct snd_soc_dapm_route cs42l43_a_routes[] = { 2309 + { "Decimator 1 Mode", "PDM", "PDM1L" }, 2310 + { "Decimator 1 Mode", "ADC", "ADC1" }, 2311 + { "Decimator 2 Mode", "PDM", "PDM1R" }, 2312 + { "Decimator 2 Mode", "ADC", "ADC2" }, 2313 + 2314 + { "Decimator 1", NULL, "Decimator 1 Mode" }, 2315 + { "Decimator 2", NULL, "Decimator 2 Mode" }, 2316 + { "Decimator 3", NULL, "PDM2L" }, 2317 + { "Decimator 4", NULL, "PDM2R" }, 2184 2318 2185 2319 CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"), 2186 2320 CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"), ··· 2486 2110 CS42L43_MIXER_ROUTES("Headphone R", "HP"), 2487 2111 }; 2488 2112 2113 + static const struct snd_soc_dapm_route cs42l43_b_routes[] = { 2114 + { "Decimator 1", NULL, "ADC1" }, 2115 + { "Decimator 2", NULL, "ADC2" }, 2116 + { "Decimator 3", NULL, "PDM1L" }, 2117 + { "Decimator 4", NULL, "PDM1R" }, 2118 + { "Decimator 5", NULL, "PDM2L" }, 2119 + { "Decimator 6", NULL, "PDM2R" }, 2120 + 2121 + { "DP3 Capture", NULL, "DP3TX3" }, 2122 + { "DP3 Capture", NULL, "DP3TX4" }, 2123 + { "DP4 Capture", NULL, "DP4TX3" }, 2124 + { "DP4 Capture", NULL, "DP4TX4" }, 2125 + 2126 + { "ISRC1DEC3", NULL, "ISRC1" }, 2127 + { "ISRC1DEC4", NULL, "ISRC1" }, 2128 + { "ISRC2DEC3", NULL, "ISRC2" }, 2129 + { "ISRC2DEC4", NULL, "ISRC2" }, 2130 + 2131 + CS42L43B_MUX_ROUTES("ASPTX1", "ASPTX1"), 2132 + CS42L43B_MUX_ROUTES("ASPTX2", "ASPTX2"), 2133 + CS42L43B_MUX_ROUTES("ASPTX3", "ASPTX3"), 2134 + CS42L43B_MUX_ROUTES("ASPTX4", "ASPTX4"), 2135 + CS42L43B_MUX_ROUTES("ASPTX5", "ASPTX5"), 2136 + CS42L43B_MUX_ROUTES("ASPTX6", "ASPTX6"), 2137 + 2138 + CS42L43B_MUX_ROUTES("DP1TX1", "DP1TX1"), 2139 + CS42L43B_MUX_ROUTES("DP1TX2", "DP1TX2"), 2140 + CS42L43B_MUX_ROUTES("DP1TX3", "DP1TX3"), 2141 + CS42L43B_MUX_ROUTES("DP1TX4", "DP1TX4"), 2142 + CS42L43B_MUX_ROUTES("DP2TX1", "DP2TX1"), 2143 + CS42L43B_MUX_ROUTES("DP2TX2", "DP2TX2"), 2144 + CS42L43B_MUX_ROUTES("DP3TX1", "DP3TX1"), 2145 + CS42L43B_MUX_ROUTES("DP3TX2", "DP3TX2"), 2146 + CS42L43B_MUX_ROUTES("DP3TX3", "DP3TX3"), 2147 + CS42L43B_MUX_ROUTES("DP3TX4", "DP3TX4"), 2148 + CS42L43B_MUX_ROUTES("DP4TX1", "DP4TX1"), 2149 + CS42L43B_MUX_ROUTES("DP4TX2", "DP4TX2"), 2150 + CS42L43B_MUX_ROUTES("DP4TX3", "DP4TX3"), 2151 + CS42L43B_MUX_ROUTES("DP4TX4", "DP4TX4"), 2152 + 2153 + CS42L43B_MUX_ROUTES("ASRC INT1", "ASRC_INT1"), 2154 + CS42L43B_MUX_ROUTES("ASRC INT2", "ASRC_INT2"), 2155 + CS42L43B_MUX_ROUTES("ASRC INT3", "ASRC_INT3"), 2156 + CS42L43B_MUX_ROUTES("ASRC INT4", "ASRC_INT4"), 2157 + CS42L43B_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"), 2158 + CS42L43B_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"), 2159 + CS42L43B_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"), 2160 + CS42L43B_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"), 2161 + 2162 + CS42L43B_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), 2163 + CS42L43B_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), 2164 + CS42L43B_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), 2165 + CS42L43B_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), 2166 + CS42L43B_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), 2167 + CS42L43B_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), 2168 + CS42L43B_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), 2169 + CS42L43B_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), 2170 + CS42L43B_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), 2171 + CS42L43B_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), 2172 + CS42L43B_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"), 2173 + CS42L43B_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"), 2174 + 2175 + CS42L43B_MUX_ROUTES("SPDIF1", "SPDIF"), 2176 + CS42L43B_MUX_ROUTES("SPDIF2", "SPDIF"), 2177 + 2178 + CS42L43B_MIXER_ROUTES("EQ1", "EQ"), 2179 + CS42L43B_MIXER_ROUTES("EQ2", "EQ"), 2180 + 2181 + CS42L43B_MIXER_ROUTES("Speaker L", "AMP1"), 2182 + CS42L43B_MIXER_ROUTES("Speaker R", "AMP2"), 2183 + 2184 + CS42L43B_MIXER_ROUTES("Headphone L", "HP"), 2185 + CS42L43B_MIXER_ROUTES("Headphone R", "HP"), 2186 + }; 2187 + 2489 2188 static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id, 2490 2189 int src, unsigned int freq, int dir) 2491 2190 { ··· 2577 2126 2578 2127 static int cs42l43_component_probe(struct snd_soc_component *component) 2579 2128 { 2129 + struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2580 2130 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 2131 + unsigned int num_controls, num_widgets, num_routes; 2132 + const struct snd_soc_dapm_widget *widgets; 2133 + const struct snd_kcontrol_new *controls; 2134 + const struct snd_soc_dapm_route *routes; 2581 2135 struct cs42l43 *cs42l43 = priv->core; 2136 + int ret; 2582 2137 2583 2138 snd_soc_component_init_regmap(component, cs42l43->regmap); 2584 2139 ··· 2595 2138 2596 2139 priv->component = component; 2597 2140 priv->constraint = cs42l43_constraint; 2141 + 2142 + switch (cs42l43->variant_id) { 2143 + case CS42L43_DEVID_VAL: 2144 + controls = cs42l43_a_controls; 2145 + num_controls = ARRAY_SIZE(cs42l43_a_controls); 2146 + widgets = cs42l43_a_widgets; 2147 + num_widgets = ARRAY_SIZE(cs42l43_a_widgets); 2148 + routes = cs42l43_a_routes; 2149 + num_routes = ARRAY_SIZE(cs42l43_a_routes); 2150 + break; 2151 + case CS42L43B_DEVID_VAL: 2152 + controls = cs42l43_b_controls; 2153 + num_controls = ARRAY_SIZE(cs42l43_b_controls); 2154 + widgets = cs42l43_b_widgets; 2155 + num_widgets = ARRAY_SIZE(cs42l43_b_widgets); 2156 + routes = cs42l43_b_routes; 2157 + num_routes = ARRAY_SIZE(cs42l43_b_routes); 2158 + break; 2159 + default: 2160 + return -EINVAL; 2161 + } 2162 + 2163 + ret = snd_soc_add_component_controls(component, controls, num_controls); 2164 + if (ret) 2165 + return ret; 2166 + 2167 + ret = snd_soc_dapm_new_controls(dapm, widgets, num_widgets); 2168 + if (ret) 2169 + return ret; 2170 + 2171 + ret = snd_soc_dapm_add_routes(dapm, routes, num_routes); 2172 + if (ret) 2173 + return ret; 2598 2174 2599 2175 return 0; 2600 2176 }

+2 -2

sound/soc/codecs/cs42l43.h

··· 61 61 unsigned int refclk_freq; 62 62 struct completion pll_ready; 63 63 64 - unsigned int decim_cache[4]; 64 + unsigned int decim_cache[6]; 65 65 unsigned int adc_ena; 66 66 unsigned int hp_ena; 67 67 ··· 103 103 bool hp_ilimited; 104 104 int hp_ilimit_count; 105 105 106 - struct snd_kcontrol *kctl[5]; 106 + struct snd_kcontrol *kctl[7]; 107 107 }; 108 108 109 109 #if IS_REACHABLE(CONFIG_SND_SOC_CS42L43_SDW)

+54

sound/soc/sdw_utils/soc_sdw_utils.c

··· 724 724 .dai_num = 4, 725 725 }, 726 726 { 727 + .part_id = 0x2A3B, 728 + .name_prefix = "cs42l43", 729 + .count_sidecar = asoc_sdw_bridge_cs35l56_count_sidecar, 730 + .add_sidecar = asoc_sdw_bridge_cs35l56_add_sidecar, 731 + .dais = { 732 + { 733 + .direction = {true, false}, 734 + .codec_name = "cs42l43-codec", 735 + .dai_name = "cs42l43-dp5", 736 + .dai_type = SOC_SDW_DAI_TYPE_JACK, 737 + .dailink = {SOC_SDW_JACK_OUT_DAI_ID, SOC_SDW_UNUSED_DAI_ID}, 738 + .rtd_init = asoc_sdw_cs42l43_hs_rtd_init, 739 + .controls = generic_jack_controls, 740 + .num_controls = ARRAY_SIZE(generic_jack_controls), 741 + .widgets = generic_jack_widgets, 742 + .num_widgets = ARRAY_SIZE(generic_jack_widgets), 743 + }, 744 + { 745 + .direction = {false, true}, 746 + .codec_name = "cs42l43-codec", 747 + .dai_name = "cs42l43-dp1", 748 + .dai_type = SOC_SDW_DAI_TYPE_MIC, 749 + .dailink = {SOC_SDW_UNUSED_DAI_ID, SOC_SDW_DMIC_DAI_ID}, 750 + .rtd_init = asoc_sdw_cs42l43_dmic_rtd_init, 751 + .widgets = generic_dmic_widgets, 752 + .num_widgets = ARRAY_SIZE(generic_dmic_widgets), 753 + .quirk = SOC_SDW_CODEC_MIC, 754 + .quirk_exclude = true, 755 + }, 756 + { 757 + .direction = {false, true}, 758 + .codec_name = "cs42l43-codec", 759 + .dai_name = "cs42l43-dp2", 760 + .dai_type = SOC_SDW_DAI_TYPE_JACK, 761 + .dailink = {SOC_SDW_UNUSED_DAI_ID, SOC_SDW_JACK_IN_DAI_ID}, 762 + }, 763 + { 764 + .direction = {true, false}, 765 + .codec_name = "cs42l43-codec", 766 + .dai_name = "cs42l43-dp6", 767 + .dai_type = SOC_SDW_DAI_TYPE_AMP, 768 + .dailink = {SOC_SDW_AMP_OUT_DAI_ID, SOC_SDW_UNUSED_DAI_ID}, 769 + .init = asoc_sdw_cs42l43_spk_init, 770 + .rtd_init = asoc_sdw_cs42l43_spk_rtd_init, 771 + .controls = generic_spk_controls, 772 + .num_controls = ARRAY_SIZE(generic_spk_controls), 773 + .widgets = generic_spk_widgets, 774 + .num_widgets = ARRAY_SIZE(generic_spk_widgets), 775 + .quirk = SOC_SDW_CODEC_SPKR | SOC_SDW_SIDECAR_AMPS, 776 + }, 777 + }, 778 + .dai_num = 4, 779 + }, 780 + { 727 781 .part_id = 0x4245, 728 782 .name_prefix = "cs42l45", 729 783 .dais = {

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