Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv/for-v5.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Paul Walmsley:
"A few minor RISC-V updates for v5.3-rc4:
- Remove __udivdi3() from the 32-bit Linux port, converting the only
upstream user to use do_div(), per Linux policy
- Convert the RISC-V standard clocksource away from per-cpu data
structures, since only one is used by Linux, even on a multi-CPU
system
- A set of DT binding updates that remove an obsolete text binding in
favor of a YAML binding, fix a bogus compatible string in the
schema (thus fixing a "make dtbs_check" warning), and clarifies the
future values expected in one of the RISC-V CPU properties"
* tag 'riscv/for-v5.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed board
dt-bindings: riscv: remove obsolete cpus.txt
RISC-V: Remove udivdi3
riscv: delay: use do_div() instead of __udivdi3()
dt-bindings: Update the riscv,isa string description
RISC-V: Remove per cpu clocksource
+24
-202
-162
Documentation/devicetree/bindings/riscv/cpus.txt
-162
Documentation/devicetree/bindings/riscv/cpus.txt
···
1
-
===================
2
-
RISC-V CPU Bindings
3
-
===================
4
-
5
-
The device tree allows to describe the layout of CPUs in a system through
6
-
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7
-
defining properties for every cpu.
8
-
9
-
Bindings for CPU nodes follow the Devicetree Specification, available from:
10
-
11
-
https://www.devicetree.org/specifications/
12
-
13
-
with updates for 32-bit and 64-bit RISC-V systems provided in this document.
14
-
15
-
===========
16
-
Terminology
17
-
===========
18
-
19
-
This document uses some terminology common to the RISC-V community that is not
20
-
widely used, the definitions of which are listed here:
21
-
22
-
* hart: A hardware execution context, which contains all the state mandated by
23
-
the RISC-V ISA: a PC and some registers. This terminology is designed to
24
-
disambiguate software's view of execution contexts from any particular
25
-
microarchitectural implementation strategy. For example, my Intel laptop is
26
-
described as having one socket with two cores, each of which has two hyper
27
-
threads. Therefore this system has four harts.
28
-
29
-
=====================================
30
-
cpus and cpu node bindings definition
31
-
=====================================
32
-
33
-
The RISC-V architecture, in accordance with the Devicetree Specification,
34
-
requires the cpus and cpu nodes to be present and contain the properties
35
-
described below.
36
-
37
-
- cpus node
38
-
39
-
Description: Container of cpu nodes
40
-
41
-
The node name must be "cpus".
42
-
43
-
A cpus node must define the following properties:
44
-
45
-
- #address-cells
46
-
Usage: required
47
-
Value type: <u32>
48
-
Definition: must be set to 1
49
-
- #size-cells
50
-
Usage: required
51
-
Value type: <u32>
52
-
Definition: must be set to 0
53
-
54
-
- cpu node
55
-
56
-
Description: Describes a hart context
57
-
58
-
PROPERTIES
59
-
60
-
- device_type
61
-
Usage: required
62
-
Value type: <string>
63
-
Definition: must be "cpu"
64
-
- reg
65
-
Usage: required
66
-
Value type: <u32>
67
-
Definition: The hart ID of this CPU node
68
-
- compatible:
69
-
Usage: required
70
-
Value type: <stringlist>
71
-
Definition: must contain "riscv", may contain one of
72
-
"sifive,rocket0"
73
-
- mmu-type:
74
-
Usage: optional
75
-
Value type: <string>
76
-
Definition: Specifies the CPU's MMU type. Possible values are
77
-
"riscv,sv32"
78
-
"riscv,sv39"
79
-
"riscv,sv48"
80
-
- riscv,isa:
81
-
Usage: required
82
-
Value type: <string>
83
-
Definition: Contains the RISC-V ISA string of this hart. These
84
-
ISA strings are defined by the RISC-V ISA manual.
85
-
86
-
Example: SiFive Freedom U540G Development Kit
87
-
---------------------------------------------
88
-
89
-
This system contains two harts: a hart marked as disabled that's used for
90
-
low-level system tasks and should be ignored by Linux, and a second hart that
91
-
Linux is allowed to run on.
92
-
93
-
cpus {
94
-
#address-cells = <1>;
95
-
#size-cells = <0>;
96
-
timebase-frequency = <1000000>;
97
-
cpu@0 {
98
-
clock-frequency = <1600000000>;
99
-
compatible = "sifive,rocket0", "riscv";
100
-
device_type = "cpu";
101
-
i-cache-block-size = <64>;
102
-
i-cache-sets = <128>;
103
-
i-cache-size = <16384>;
104
-
next-level-cache = <&L15 &L0>;
105
-
reg = <0>;
106
-
riscv,isa = "rv64imac";
107
-
status = "disabled";
108
-
L10: interrupt-controller {
109
-
#interrupt-cells = <1>;
110
-
compatible = "riscv,cpu-intc";
111
-
interrupt-controller;
112
-
};
113
-
};
114
-
cpu@1 {
115
-
clock-frequency = <1600000000>;
116
-
compatible = "sifive,rocket0", "riscv";
117
-
d-cache-block-size = <64>;
118
-
d-cache-sets = <64>;
119
-
d-cache-size = <32768>;
120
-
d-tlb-sets = <1>;
121
-
d-tlb-size = <32>;
122
-
device_type = "cpu";
123
-
i-cache-block-size = <64>;
124
-
i-cache-sets = <64>;
125
-
i-cache-size = <32768>;
126
-
i-tlb-sets = <1>;
127
-
i-tlb-size = <32>;
128
-
mmu-type = "riscv,sv39";
129
-
next-level-cache = <&L15 &L0>;
130
-
reg = <1>;
131
-
riscv,isa = "rv64imafdc";
132
-
status = "okay";
133
-
tlb-split;
134
-
L13: interrupt-controller {
135
-
#interrupt-cells = <1>;
136
-
compatible = "riscv,cpu-intc";
137
-
interrupt-controller;
138
-
};
139
-
};
140
-
};
141
-
142
-
Example: Spike ISA Simulator with 1 Hart
143
-
----------------------------------------
144
-
145
-
This device tree matches the Spike ISA golden model as run with `spike -p1`.
146
-
147
-
cpus {
148
-
cpu@0 {
149
-
device_type = "cpu";
150
-
reg = <0x00000000>;
151
-
status = "okay";
152
-
compatible = "riscv";
153
-
riscv,isa = "rv64imafdc";
154
-
mmu-type = "riscv,sv48";
155
-
clock-frequency = <0x3b9aca00>;
156
-
interrupt-controller {
157
-
#interrupt-cells = <0x00000001>;
158
-
interrupt-controller;
159
-
compatible = "riscv,cpu-intc";
160
-
}
161
-
}
162
-
}
+16
Documentation/devicetree/bindings/riscv/cpus.yaml
+16
Documentation/devicetree/bindings/riscv/cpus.yaml
···
10
10
- Paul Walmsley <paul.walmsley@sifive.com>
11
11
- Palmer Dabbelt <palmer@sifive.com>
12
12
13
+
description: |
14
+
This document uses some terminology common to the RISC-V community
15
+
that is not widely used, the definitions of which are listed here:
16
+
17
+
hart: A hardware execution context, which contains all the state
18
+
mandated by the RISC-V ISA: a PC and some registers. This
19
+
terminology is designed to disambiguate software's view of execution
20
+
contexts from any particular microarchitectural implementation
21
+
strategy. For example, an Intel laptop containing one socket with
22
+
two cores, each of which has two hyperthreads, could be described as
23
+
having four harts.
24
+
13
25
properties:
14
26
compatible:
15
27
items:
···
61
49
supported by the hart. These are documented in the RISC-V
62
50
User-Level ISA document, available from
63
51
https://riscv.org/specifications/
52
+
53
+
While the isa strings in ISA specification are case
54
+
insensitive, letters in the riscv,isa string must be all
55
+
lowercase to simplify parsing.
64
56
65
57
timebase-frequency:
66
58
type: integer
+1
-1
Documentation/devicetree/bindings/riscv/sifive.yaml
+1
-1
Documentation/devicetree/bindings/riscv/sifive.yaml
-2
arch/riscv/lib/Makefile
-2
arch/riscv/lib/Makefile
+5
-1
arch/riscv/lib/delay.c
+5
-1
arch/riscv/lib/delay.c
···
81
81
void udelay(unsigned long usecs)
82
82
{
83
83
u64 ucycles = (u64)usecs * lpj_fine * UDELAY_MULT;
84
+
u64 n;
84
85
85
86
if (unlikely(usecs > MAX_UDELAY_US)) {
86
-
__delay((u64)usecs * riscv_timebase / 1000000ULL);
87
+
n = (u64)usecs * riscv_timebase;
88
+
do_div(n, 1000000);
89
+
90
+
__delay(n);
87
91
return;
88
92
}
89
93
-32
arch/riscv/lib/udivdi3.S
-32
arch/riscv/lib/udivdi3.S
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* Copyright (C) 2016-2017 Free Software Foundation, Inc.
4
-
*/
5
-
6
-
#include <linux/linkage.h>
7
-
8
-
ENTRY(__udivdi3)
9
-
mv a2, a1
10
-
mv a1, a0
11
-
li a0, -1
12
-
beqz a2, .L5
13
-
li a3, 1
14
-
bgeu a2, a1, .L2
15
-
.L1:
16
-
blez a2, .L2
17
-
slli a2, a2, 1
18
-
slli a3, a3, 1
19
-
bgtu a1, a2, .L1
20
-
.L2:
21
-
li a0, 0
22
-
.L3:
23
-
bltu a1, a2, .L4
24
-
sub a1, a1, a2
25
-
or a0, a0, a3
26
-
.L4:
27
-
srli a3, a3, 1
28
-
srli a2, a2, 1
29
-
bnez a3, .L3
30
-
.L5:
31
-
ret
32
-
ENDPROC(__udivdi3)
+2
-4
drivers/clocksource/timer-riscv.c
+2
-4
drivers/clocksource/timer-riscv.c
···
55
55
return get_cycles64();
56
56
}
57
57
58
-
static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
58
+
static struct clocksource riscv_clocksource = {
59
59
.name = "riscv_clocksource",
60
60
.rating = 300,
61
61
.mask = CLOCKSOURCE_MASK(64),
···
92
92
static int __init riscv_timer_init_dt(struct device_node *n)
93
93
{
94
94
int cpuid, hartid, error;
95
-
struct clocksource *cs;
96
95
97
96
hartid = riscv_of_processor_hartid(n);
98
97
if (hartid < 0) {
···
111
112
112
113
pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
113
114
__func__, cpuid, hartid);
114
-
cs = per_cpu_ptr(&riscv_clocksource, cpuid);
115
-
error = clocksource_register_hz(cs, riscv_timebase);
115
+
error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
116
116
if (error) {
117
117
pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
118
118
error, cpuid);