Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge master.kernel.org:/home/rmk/linux-2.6-arm
+57
-253
+3
-1
Documentation/arm/memory.txt
+3
-1
Documentation/arm/memory.txt
···
1
1
Kernel Memory Layout on ARM Linux
2
2
3
3
Russell King <rmk@arm.linux.org.uk>
4
-
May 21, 2004 (2.6.6)
4
+
November 17, 2005 (2.6.15)
5
5
6
6
This document describes the virtual memory layout which the Linux
7
7
kernel uses for ARM processors. It indicates which regions are
···
37
37
mapping region.
38
38
39
39
VMALLOC_END feffffff Free for platform use, recommended.
40
+
VMALLOC_END must be aligned to a 2MB
41
+
boundary.
40
42
41
43
VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
42
44
Memory returned by vmalloc/ioremap will
-1
arch/arm/kernel/armksyms.c
-1
arch/arm/kernel/armksyms.c
+1
-2
arch/arm/kernel/entry-common.S
+1
-2
arch/arm/kernel/entry-common.S
+12
-13
arch/arm/kernel/signal.c
+12
-13
arch/arm/kernel/signal.c
···
595
595
*/
596
596
ret |= !valid_user_regs(regs);
597
597
598
-
/*
599
-
* Block the signal if we were unsuccessful.
600
-
*/
601
598
if (ret != 0) {
602
-
spin_lock_irq(&tsk->sighand->siglock);
603
-
sigorsets(&tsk->blocked, &tsk->blocked,
604
-
&ka->sa.sa_mask);
605
-
if (!(ka->sa.sa_flags & SA_NODEFER))
606
-
sigaddset(&tsk->blocked, sig);
607
-
recalc_sigpending();
608
-
spin_unlock_irq(&tsk->sighand->siglock);
599
+
force_sigsegv(sig, tsk);
600
+
return;
609
601
}
610
602
611
-
if (ret == 0)
612
-
return;
603
+
/*
604
+
* Block the signal if we were successful.
605
+
*/
606
+
spin_lock_irq(&tsk->sighand->siglock);
607
+
sigorsets(&tsk->blocked, &tsk->blocked,
608
+
&ka->sa.sa_mask);
609
+
if (!(ka->sa.sa_flags & SA_NODEFER))
610
+
sigaddset(&tsk->blocked, sig);
611
+
recalc_sigpending();
612
+
spin_unlock_irq(&tsk->sighand->siglock);
613
613
614
-
force_sigsegv(sig, tsk);
615
614
}
616
615
617
616
/*
+5
-1
arch/arm/kernel/vmlinux.lds.S
+5
-1
arch/arm/kernel/vmlinux.lds.S
···
172
172
.comment 0 : { *(.comment) }
173
173
}
174
174
175
-
/* those must never be empty */
175
+
/*
176
+
* These must never be empty
177
+
* If you have to comment these two assert statements out, your
178
+
* binutils is too old (for other reasons as well)
179
+
*/
176
180
ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support")
177
181
ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")
-11
arch/arm/lib/getuser.S
-11
arch/arm/lib/getuser.S
···
54
54
mov r0, #0
55
55
mov pc, lr
56
56
57
-
.global __get_user_8
58
-
__get_user_8:
59
-
5: ldrt r2, [r0], #4
60
-
6: ldrt r3, [r0]
61
-
mov r0, #0
62
-
mov pc, lr
63
-
64
-
__get_user_bad_8:
65
-
mov r3, #0
66
57
__get_user_bad:
67
58
mov r2, #0
68
59
mov r0, #-EFAULT
···
64
73
.long 2b, __get_user_bad
65
74
.long 3b, __get_user_bad
66
75
.long 4b, __get_user_bad
67
-
.long 5b, __get_user_bad_8
68
-
.long 6b, __get_user_bad_8
69
76
.previous
+1
-1
arch/arm/mm/Makefile
+1
-1
arch/arm/mm/Makefile
-185
arch/arm/mm/blockops.c
-185
arch/arm/mm/blockops.c
···
1
-
#include <linux/kernel.h>
2
-
#include <linux/init.h>
3
-
#include <linux/errno.h>
4
-
#include <linux/mm.h>
5
-
6
-
#include <asm/memory.h>
7
-
#include <asm/ptrace.h>
8
-
#include <asm/cacheflush.h>
9
-
#include <asm/traps.h>
10
-
11
-
extern struct cpu_cache_fns blk_cache_fns;
12
-
13
-
#define HARVARD_CACHE
14
-
15
-
/*
16
-
* blk_flush_kern_dcache_page(kaddr)
17
-
*
18
-
* Ensure that the data held in the page kaddr is written back
19
-
* to the page in question.
20
-
*
21
-
* - kaddr - kernel address (guaranteed to be page aligned)
22
-
*/
23
-
static void __attribute__((naked))
24
-
blk_flush_kern_dcache_page(void *kaddr)
25
-
{
26
-
asm(
27
-
"add r1, r0, %0 \n\
28
-
sub r1, r1, %1 \n\
29
-
1: .word 0xec401f0e @ mcrr p15, 0, r0, r1, c14, 0 @ blocking \n\
30
-
mov r0, #0 \n\
31
-
mcr p15, 0, r0, c7, c5, 0 \n\
32
-
mcr p15, 0, r0, c7, c10, 4 \n\
33
-
mov pc, lr"
34
-
:
35
-
: "I" (PAGE_SIZE), "I" (L1_CACHE_BYTES));
36
-
}
37
-
38
-
/*
39
-
* blk_dma_inv_range(start,end)
40
-
*
41
-
* Invalidate the data cache within the specified region; we will
42
-
* be performing a DMA operation in this region and we want to
43
-
* purge old data in the cache.
44
-
*
45
-
* - start - virtual start address of region
46
-
* - end - virtual end address of region
47
-
*/
48
-
static void __attribute__((naked))
49
-
blk_dma_inv_range_unified(unsigned long start, unsigned long end)
50
-
{
51
-
asm(
52
-
"tst r0, %0 \n\
53
-
mcrne p15, 0, r0, c7, c11, 1 @ clean unified line \n\
54
-
tst r1, %0 \n\
55
-
mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line\n\
56
-
.word 0xec401f06 @ mcrr p15, 0, r1, r0, c6, 0 @ blocking \n\
57
-
mov r0, #0 \n\
58
-
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer \n\
59
-
mov pc, lr"
60
-
:
61
-
: "I" (L1_CACHE_BYTES - 1));
62
-
}
63
-
64
-
static void __attribute__((naked))
65
-
blk_dma_inv_range_harvard(unsigned long start, unsigned long end)
66
-
{
67
-
asm(
68
-
"tst r0, %0 \n\
69
-
mcrne p15, 0, r0, c7, c10, 1 @ clean D line \n\
70
-
tst r1, %0 \n\
71
-
mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line \n\
72
-
.word 0xec401f06 @ mcrr p15, 0, r1, r0, c6, 0 @ blocking \n\
73
-
mov r0, #0 \n\
74
-
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer \n\
75
-
mov pc, lr"
76
-
:
77
-
: "I" (L1_CACHE_BYTES - 1));
78
-
}
79
-
80
-
/*
81
-
* blk_dma_clean_range(start,end)
82
-
* - start - virtual start address of region
83
-
* - end - virtual end address of region
84
-
*/
85
-
static void __attribute__((naked))
86
-
blk_dma_clean_range(unsigned long start, unsigned long end)
87
-
{
88
-
asm(
89
-
".word 0xec401f0c @ mcrr p15, 0, r1, r0, c12, 0 @ blocking \n\
90
-
mov r0, #0 \n\
91
-
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer \n\
92
-
mov pc, lr");
93
-
}
94
-
95
-
/*
96
-
* blk_dma_flush_range(start,end)
97
-
* - start - virtual start address of region
98
-
* - end - virtual end address of region
99
-
*/
100
-
static void __attribute__((naked))
101
-
blk_dma_flush_range(unsigned long start, unsigned long end)
102
-
{
103
-
asm(
104
-
".word 0xec401f0e @ mcrr p15, 0, r1, r0, c14, 0 @ blocking \n\
105
-
mov pc, lr");
106
-
}
107
-
108
-
static int blockops_trap(struct pt_regs *regs, unsigned int instr)
109
-
{
110
-
regs->ARM_r4 |= regs->ARM_r2;
111
-
regs->ARM_pc += 4;
112
-
return 0;
113
-
}
114
-
115
-
static char *func[] = {
116
-
"Prefetch data range",
117
-
"Clean+Invalidate data range",
118
-
"Clean data range",
119
-
"Invalidate data range",
120
-
"Invalidate instr range"
121
-
};
122
-
123
-
static struct undef_hook blockops_hook __initdata = {
124
-
.instr_mask = 0x0fffffd0,
125
-
.instr_val = 0x0c401f00,
126
-
.cpsr_mask = PSR_T_BIT,
127
-
.cpsr_val = 0,
128
-
.fn = blockops_trap,
129
-
};
130
-
131
-
static int __init blockops_check(void)
132
-
{
133
-
register unsigned int err asm("r4") = 0;
134
-
unsigned int err_pos = 1;
135
-
unsigned int cache_type;
136
-
int i;
137
-
138
-
asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (cache_type));
139
-
140
-
printk("Checking V6 block cache operations:\n");
141
-
register_undef_hook(&blockops_hook);
142
-
143
-
__asm__ ("mov r0, %0\n\t"
144
-
"mov r1, %1\n\t"
145
-
"mov r2, #1\n\t"
146
-
".word 0xec401f2c @ mcrr p15, 0, r1, r0, c12, 2\n\t"
147
-
"mov r2, #2\n\t"
148
-
".word 0xec401f0e @ mcrr p15, 0, r1, r0, c14, 0\n\t"
149
-
"mov r2, #4\n\t"
150
-
".word 0xec401f0c @ mcrr p15, 0, r1, r0, c12, 0\n\t"
151
-
"mov r2, #8\n\t"
152
-
".word 0xec401f06 @ mcrr p15, 0, r1, r0, c6, 0\n\t"
153
-
"mov r2, #16\n\t"
154
-
".word 0xec401f05 @ mcrr p15, 0, r1, r0, c5, 0\n\t"
155
-
:
156
-
: "r" (PAGE_OFFSET), "r" (PAGE_OFFSET + 128)
157
-
: "r0", "r1", "r2");
158
-
159
-
unregister_undef_hook(&blockops_hook);
160
-
161
-
for (i = 0; i < ARRAY_SIZE(func); i++, err_pos <<= 1)
162
-
printk("%30s: %ssupported\n", func[i], err & err_pos ? "not " : "");
163
-
164
-
if ((err & 8) == 0) {
165
-
printk(" --> Using %s block cache invalidate\n",
166
-
cache_type & (1 << 24) ? "harvard" : "unified");
167
-
if (cache_type & (1 << 24))
168
-
cpu_cache.dma_inv_range = blk_dma_inv_range_harvard;
169
-
else
170
-
cpu_cache.dma_inv_range = blk_dma_inv_range_unified;
171
-
}
172
-
if ((err & 4) == 0) {
173
-
printk(" --> Using block cache clean\n");
174
-
cpu_cache.dma_clean_range = blk_dma_clean_range;
175
-
}
176
-
if ((err & 2) == 0) {
177
-
printk(" --> Using block cache clean+invalidate\n");
178
-
cpu_cache.dma_flush_range = blk_dma_flush_range;
179
-
cpu_cache.flush_kern_dcache_page = blk_flush_kern_dcache_page;
180
-
}
181
-
182
-
return 0;
183
-
}
184
-
185
-
__initcall(blockops_check);
+13
-11
arch/arm/mm/init.c
+13
-11
arch/arm/mm/init.c
···
420
420
* Set up device the mappings. Since we clear out the page tables for all
421
421
* mappings above VMALLOC_END, we will remove any debug device mappings.
422
422
* This means you have to be careful how you debug this function, or any
423
-
* called function. (Do it by code inspection!)
423
+
* called function. This means you can't use any function or debugging
424
+
* method which may touch any device, otherwise the kernel _will_ crash.
424
425
*/
425
426
static void __init devicemaps_init(struct machine_desc *mdesc)
426
427
{
427
428
struct map_desc map;
428
429
unsigned long addr;
429
430
void *vectors;
431
+
432
+
/*
433
+
* Allocate the vector page early.
434
+
*/
435
+
vectors = alloc_bootmem_low_pages(PAGE_SIZE);
436
+
BUG_ON(!vectors);
430
437
431
438
for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
432
439
pmd_clear(pmd_off_k(addr));
···
468
461
create_mapping(&map);
469
462
#endif
470
463
471
-
flush_cache_all();
472
-
local_flush_tlb_all();
473
-
474
-
vectors = alloc_bootmem_low_pages(PAGE_SIZE);
475
-
BUG_ON(!vectors);
476
-
477
464
/*
478
465
* Create a mapping for the machine vectors at the high-vectors
479
466
* location (0xffff0000). If we aren't using high-vectors, also
···
492
491
mdesc->map_io();
493
492
494
493
/*
495
-
* Finally flush the tlb again - this ensures that we're in a
496
-
* consistent state wrt the writebuffer if the writebuffer needs
497
-
* draining. After this point, we can start to touch devices
498
-
* again.
494
+
* Finally flush the caches and tlb to ensure that we're in a
495
+
* consistent state wrt the writebuffer. This also ensures that
496
+
* any write-allocated cache lines in the vector page are written
497
+
* back. After this point, we can start to touch devices again.
499
498
*/
500
499
local_flush_tlb_all();
500
+
flush_cache_all();
501
501
}
502
502
503
503
/*
+1
-2
arch/arm/mm/ioremap.c
+1
-2
arch/arm/mm/ioremap.c
···
130
130
* mapping. See include/asm-arm/proc-armv/pgtable.h for more information.
131
131
*/
132
132
void __iomem *
133
-
__ioremap(unsigned long phys_addr, size_t size, unsigned long flags,
134
-
unsigned long align)
133
+
__ioremap(unsigned long phys_addr, size_t size, unsigned long flags)
135
134
{
136
135
void * addr;
137
136
struct vm_struct * area;
+3
-3
drivers/mtd/maps/ipaq-flash.c
+3
-3
drivers/mtd/maps/ipaq-flash.c
···
246
246
ipaq_map[i].size = h3xxx_max_flash_size;
247
247
ipaq_map[i].set_vpp = h3xxx_set_vpp;
248
248
ipaq_map[i].phys = cs_phys[i];
249
-
ipaq_map[i].virt = __ioremap(cs_phys[i], 0x04000000, 0, 1);
249
+
ipaq_map[i].virt = ioremap(cs_phys[i], 0x04000000);
250
250
if (machine_is_h3100 () || machine_is_h1900())
251
251
ipaq_map[i].bankwidth = 2;
252
252
}
···
280
280
nb_parts = ARRAY_SIZE(jornada_partitions);
281
281
ipaq_map[0].size = jornada_max_flash_size;
282
282
ipaq_map[0].set_vpp = jornada56x_set_vpp;
283
-
ipaq_map[0].virt = (__u32)__ioremap(0x0, 0x04000000, 0, 1);
283
+
ipaq_map[0].virt = (__u32)ioremap(0x0, 0x04000000);
284
284
}
285
285
#endif
286
286
#ifdef CONFIG_SA1100_JORNADA720
···
442
442
ipaq_map[0].size = 0x80000;
443
443
ipaq_map[0].set_vpp = h3xxx_set_vpp;
444
444
ipaq_map[0].phys = 0x0;
445
-
ipaq_map[0].virt = __ioremap(0x0, 0x04000000, 0, 1);
445
+
ipaq_map[0].virt = ioremap(0x0, 0x04000000);
446
446
ipaq_map[0].bankwidth = 2;
447
447
448
448
printk(KERN_NOTICE "iPAQ flash: probing %d-bit flash bus, window=%lx with JEDEC.\n", ipaq_map[0].bankwidth*8, ipaq_map[0].virt);
+1
-1
drivers/mtd/nand/h1910.c
+1
-1
drivers/mtd/nand/h1910.c
+3
-6
include/asm-arm/arch-ixp4xx/io.h
+3
-6
include/asm-arm/arch-ixp4xx/io.h
···
59
59
* fallback to the default.
60
60
*/
61
61
static inline void __iomem *
62
-
__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned long align)
62
+
__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags)
63
63
{
64
-
extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
65
64
if((addr < 0x48000000) || (addr > 0x4fffffff))
66
-
return __ioremap(addr, size, flags, align);
65
+
return __ioremap(addr, size, flags);
67
66
68
67
return (void *)addr;
69
68
}
···
70
71
static inline void
71
72
__ixp4xx_iounmap(void __iomem *addr)
72
73
{
73
-
extern void __iounmap(void __iomem *addr);
74
-
75
74
if ((u32)addr >= VMALLOC_START)
76
75
__iounmap(addr);
77
76
}
78
77
79
-
#define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x)
78
+
#define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f)
80
79
#define __arch_iounmap(a) __ixp4xx_iounmap(a)
81
80
82
81
#define writeb(v, p) __ixp4xx_writeb(v, p)
+12
-9
include/asm-arm/io.h
+12
-9
include/asm-arm/io.h
···
55
55
#define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a))
56
56
57
57
/*
58
+
* Architecture ioremap implementation.
59
+
*/
60
+
extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
61
+
extern void __iounmap(void __iomem *addr);
62
+
63
+
/*
58
64
* Bad read/write accesses...
59
65
*/
60
66
extern void __readwrite_bug(const char *fn);
···
262
256
* ioremap takes a PCI memory address, as specified in
263
257
* Documentation/IO-mapping.txt.
264
258
*/
265
-
extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
266
-
extern void __iounmap(void __iomem *addr);
267
-
268
259
#ifndef __arch_ioremap
269
-
#define ioremap(cookie,size) __ioremap(cookie,size,0,1)
270
-
#define ioremap_nocache(cookie,size) __ioremap(cookie,size,0,1)
271
-
#define ioremap_cached(cookie,size) __ioremap(cookie,size,L_PTE_CACHEABLE,1)
260
+
#define ioremap(cookie,size) __ioremap(cookie,size,0)
261
+
#define ioremap_nocache(cookie,size) __ioremap(cookie,size,0)
262
+
#define ioremap_cached(cookie,size) __ioremap(cookie,size,L_PTE_CACHEABLE)
272
263
#define iounmap(cookie) __iounmap(cookie)
273
264
#else
274
-
#define ioremap(cookie,size) __arch_ioremap((cookie),(size),0,1)
275
-
#define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0,1)
276
-
#define ioremap_cached(cookie,size) __arch_ioremap((cookie),(size),L_PTE_CACHEABLE,1)
265
+
#define ioremap(cookie,size) __arch_ioremap((cookie),(size),0)
266
+
#define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0)
267
+
#define ioremap_cached(cookie,size) __arch_ioremap((cookie),(size),L_PTE_CACHEABLE)
277
268
#define iounmap(cookie) __arch_iounmap(cookie)
278
269
#endif
279
270
+2
-6
include/asm-arm/uaccess.h
+2
-6
include/asm-arm/uaccess.h
···
100
100
extern int __get_user_1(void *);
101
101
extern int __get_user_2(void *);
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extern int __get_user_4(void *);
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-
extern int __get_user_8(void *);
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extern int __get_user_bad(void);
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104
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#define __get_user_x(__r2,__p,__e,__s,__i...) \
···
113
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#define get_user(x,p) \
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({ \
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const register typeof(*(p)) __user *__p asm("r0") = (p);\
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register typeof(*(p)) __r2 asm("r2"); \
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+
register unsigned int __r2 asm("r2"); \
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register int __e asm("r0"); \
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119
switch (sizeof(*(__p))) { \
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case 1: \
···
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case 4: \
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__get_user_x(__r2, __p, __e, 4, "lr"); \
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break; \
128
-
case 8: \
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-
__get_user_x(__r2, __p, __e, 8, "lr"); \
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-
break; \
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129
default: __e = __get_user_bad(); break; \
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130
} \
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-
x = __r2; \
131
+
x = (typeof(*(p))) __r2; \
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__e; \
135
133
})
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134