Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Add Visual Confirm Support for Testing
[WHY+HOW]
Adding visual confirm to visually track changes in refresh rate.
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Muaaz Nisar <muanisar@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Muaaz Nisar
and committed by
Alex Deucher
29c9087b
ff374446
+105
-69
+79
-69
drivers/gpu/drm/amd/display/dc/core/dc.c
+79
-69
drivers/gpu/drm/amd/display/dc/core/dc.c
···
443
443
}
444
444
445
445
/**
446
-
* dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
447
-
* @dc: dc reference
448
-
* @stream: Initial dc stream state
449
-
* @adjust: Updated parameters for vertical_total_min and vertical_total_max
450
-
*
451
-
* Looks up the pipe context of dc_stream_state and updates the
452
-
* vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
453
-
* Rate, which is a power-saving feature that targets reducing panel
454
-
* refresh rate while the screen is static
455
-
*
456
-
* Return: %true if the pipe context is found and adjusted;
457
-
* %false if the pipe context is not found.
458
-
*/
459
-
bool dc_stream_adjust_vmin_vmax(struct dc *dc,
460
-
struct dc_stream_state *stream,
461
-
struct dc_crtc_timing_adjust *adjust)
462
-
{
463
-
int i;
464
-
465
-
/*
466
-
* Don't adjust DRR while there's bandwidth optimizations pending to
467
-
* avoid conflicting with firmware updates.
468
-
*/
469
-
if (dc->ctx->dce_version > DCE_VERSION_MAX) {
470
-
if (dc->optimized_required &&
471
-
(stream->adjust.v_total_max != adjust->v_total_max ||
472
-
stream->adjust.v_total_min != adjust->v_total_min)) {
473
-
stream->adjust.timing_adjust_pending = true;
474
-
return false;
475
-
}
476
-
}
477
-
478
-
dc_exit_ips_for_hw_access(dc);
479
-
480
-
stream->adjust.v_total_max = adjust->v_total_max;
481
-
stream->adjust.v_total_mid = adjust->v_total_mid;
482
-
stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
483
-
stream->adjust.v_total_min = adjust->v_total_min;
484
-
stream->adjust.allow_otg_v_count_halt = adjust->allow_otg_v_count_halt;
485
-
486
-
if (dc->caps.max_v_total != 0 &&
487
-
(adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) {
488
-
stream->adjust.timing_adjust_pending = false;
489
-
if (adjust->allow_otg_v_count_halt)
490
-
return set_long_vtotal(dc, stream, adjust);
491
-
else
492
-
return false;
493
-
}
494
-
495
-
for (i = 0; i < MAX_PIPES; i++) {
496
-
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
497
-
498
-
if (pipe->stream == stream && pipe->stream_res.tg) {
499
-
dc->hwss.set_drr(&pipe,
500
-
1,
501
-
*adjust);
502
-
stream->adjust.timing_adjust_pending = false;
503
-
504
-
if (dc->hwss.notify_cursor_offload_drr_update)
505
-
dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream);
506
-
507
-
return true;
508
-
}
509
-
}
510
-
511
-
return false;
512
-
}
513
-
514
-
/**
515
446
* dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of
516
447
* dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate)
517
448
*
···
1205
1274
get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1206
1275
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_VABC)
1207
1276
get_vabc_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1277
+
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE)
1278
+
get_refresh_rate_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1208
1279
}
1209
1280
}
1210
1281
}
···
1254
1321
}
1255
1322
}
1256
1323
}
1324
+
}
1325
+
1326
+
/**
1327
+
* dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
1328
+
* @dc: dc reference
1329
+
* @stream: Initial dc stream state
1330
+
* @adjust: Updated parameters for vertical_total_min and vertical_total_max
1331
+
*
1332
+
* Looks up the pipe context of dc_stream_state and updates the
1333
+
* vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
1334
+
* Rate, which is a power-saving feature that targets reducing panel
1335
+
* refresh rate while the screen is static
1336
+
*
1337
+
* Return: %true if the pipe context is found and adjusted;
1338
+
* %false if the pipe context is not found.
1339
+
*/
1340
+
bool dc_stream_adjust_vmin_vmax(struct dc *dc,
1341
+
struct dc_stream_state *stream,
1342
+
struct dc_crtc_timing_adjust *adjust)
1343
+
{
1344
+
int i;
1345
+
1346
+
/*
1347
+
* Don't adjust DRR while there's bandwidth optimizations pending to
1348
+
* avoid conflicting with firmware updates.
1349
+
*/
1350
+
if (dc->ctx->dce_version > DCE_VERSION_MAX) {
1351
+
if (dc->optimized_required &&
1352
+
(stream->adjust.v_total_max != adjust->v_total_max ||
1353
+
stream->adjust.v_total_min != adjust->v_total_min)) {
1354
+
stream->adjust.timing_adjust_pending = true;
1355
+
return false;
1356
+
}
1357
+
}
1358
+
1359
+
dc_exit_ips_for_hw_access(dc);
1360
+
1361
+
stream->adjust.v_total_max = adjust->v_total_max;
1362
+
stream->adjust.v_total_mid = adjust->v_total_mid;
1363
+
stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
1364
+
stream->adjust.v_total_min = adjust->v_total_min;
1365
+
stream->adjust.allow_otg_v_count_halt = adjust->allow_otg_v_count_halt;
1366
+
1367
+
if (dc->caps.max_v_total != 0 &&
1368
+
(adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) {
1369
+
stream->adjust.timing_adjust_pending = false;
1370
+
if (adjust->allow_otg_v_count_halt)
1371
+
return set_long_vtotal(dc, stream, adjust);
1372
+
else
1373
+
return false;
1374
+
}
1375
+
1376
+
for (i = 0; i < MAX_PIPES; i++) {
1377
+
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1378
+
1379
+
if (pipe->stream == stream && pipe->stream_res.tg) {
1380
+
dc->hwss.set_drr(&pipe,
1381
+
1,
1382
+
*adjust);
1383
+
stream->adjust.timing_adjust_pending = false;
1384
+
1385
+
if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE) {
1386
+
if (pipe->stream && pipe->plane_state) {
1387
+
dc_update_visual_confirm_color(dc, dc->current_state, pipe);
1388
+
dc->hwss.update_visual_confirm_color(dc, pipe, pipe->plane_res.hubp->mpcc_id);
1389
+
1390
+
}
1391
+
}
1392
+
1393
+
if (dc->hwss.notify_cursor_offload_drr_update)
1394
+
dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream);
1395
+
1396
+
return true;
1397
+
}
1398
+
}
1399
+
1400
+
return false;
1257
1401
}
1258
1402
1259
1403
static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+21
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+21
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
···
4108
4108
(*seq_state->num_steps)++;
4109
4109
}
4110
4110
}
4111
+
4112
+
4113
+
void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *color)
4114
+
{
4115
+
uint32_t color_value = MAX_TG_COLOR_VALUE;
4116
+
unsigned int refresh_rate = 0;
4117
+
uint32_t scaling_factor = 0;
4118
+
if (pipe_ctx && pipe_ctx->stream && color) {
4119
+
refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100) / (pipe_ctx->stream->adjust.v_total_max * pipe_ctx->stream->timing.h_total);
4120
+
4121
+
uint32_t min_refresh_rate = pipe_ctx->stream->timing.min_refresh_in_uhz / 1000000;
4122
+
uint32_t max_refresh_rate = pipe_ctx->stream->timing.max_refresh_in_uhz / 1000000;
4123
+
4124
+
if (max_refresh_rate - min_refresh_rate)
4125
+
scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate);
4126
+
4127
+
pipe_ctx->visual_confirm_color.color_r_cr = color_value;
4128
+
pipe_ctx->visual_confirm_color.color_g_y = scaling_factor;
4129
+
pipe_ctx->visual_confirm_color.color_b_cb = color_value;
4130
+
}
4131
+
}
+1
drivers/gpu/drm/amd/display/dc/dc.h
+1
drivers/gpu/drm/amd/display/dc/dc.h
+4
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+4
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
···
1365
1365
struct pipe_ctx *pipe_ctx,
1366
1366
struct tg_color *color);
1367
1367
1368
+
void get_refresh_rate_confirm_color(
1369
+
struct pipe_ctx *pipe_ctx,
1370
+
struct tg_color *color);
1371
+
1368
1372
void set_p_state_switch_method(
1369
1373
struct dc *dc,
1370
1374
struct dc_state *context,