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phy: rockchip: add support for the rk356x variant to rockchip-inno-csidphy

This adds support for variant found in Rockchip RK356x SoCs. Note that
only the basic operating mode is supported, in which all four CSI lines
are controlled by the Rockchip ISP.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220720091527.1270365-3-michael.riesch@wolfvision.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Michael Riesch and committed by
Vinod Koul 29c99fb0 22c8e0a6

+24
+24
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
··· 27 27 28 28 #define RK3368_GRF_SOC_CON6_OFFSET 0x0418 29 29 30 + #define RK3568_GRF_VI_CON0 0x0340 31 + #define RK3568_GRF_VI_CON1 0x0344 32 + 30 33 /* PHY */ 31 34 #define CSIDPHY_CTRL_LANE_ENABLE 0x00 32 35 #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6) ··· 61 58 #define RK1808_CSIDPHY_CLK_WR_THS_SETTLE 0x160 62 59 #define RK3326_CSIDPHY_CLK_WR_THS_SETTLE 0x100 63 60 #define RK3368_CSIDPHY_CLK_WR_THS_SETTLE 0x100 61 + #define RK3568_CSIDPHY_CLK_WR_THS_SETTLE 0x160 64 62 65 63 /* Calibration reception enable */ 66 64 #define RK1808_CSIDPHY_CLK_CALIB_EN 0x168 65 + #define RK3568_CSIDPHY_CLK_CALIB_EN 0x168 67 66 68 67 /* 69 68 * The higher 16-bit of this register is used for write protection ··· 106 101 107 102 static const struct dphy_reg rk3368_grf_dphy_regs[] = { 108 103 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8), 104 + }; 105 + 106 + static const struct dphy_reg rk3568_grf_dphy_regs[] = { 107 + [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3568_GRF_VI_CON0, 4, 0), 108 + [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 4, 4), 109 + [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 1, 8), 109 110 }; 110 111 111 112 struct hsfreq_range { ··· 363 352 .grf_regs = rk3368_grf_dphy_regs, 364 353 }; 365 354 355 + static const struct dphy_drv_data rk3568_mipidphy_drv_data = { 356 + .pwrctl_offset = -1, 357 + .ths_settle_offset = RK3568_CSIDPHY_CLK_WR_THS_SETTLE, 358 + .calib_offset = RK3568_CSIDPHY_CLK_CALIB_EN, 359 + .hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges, 360 + .num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), 361 + .grf_regs = rk3568_grf_dphy_regs, 362 + }; 363 + 366 364 static const struct of_device_id rockchip_inno_csidphy_match_id[] = { 367 365 { 368 366 .compatible = "rockchip,px30-csi-dphy", ··· 388 368 { 389 369 .compatible = "rockchip,rk3368-csi-dphy", 390 370 .data = &rk3368_mipidphy_drv_data, 371 + }, 372 + { 373 + .compatible = "rockchip,rk3568-csi-dphy", 374 + .data = &rk3568_mipidphy_drv_data, 391 375 }, 392 376 {} 393 377 };