tjh.dev / kernel
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drm/msm/registers: Make TPL1_BICUBIC_WEIGHTS_TABLE an array

Synced from mesa commit 77c42c1a5752 ("freedreno/registers: Make
TPL1_BICUBIC_WEIGHTS_TABLE an array").

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673552/

Rob Clark 29e087f3 90528176

+16 -20
+5 -5
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
··· 1355 1355 1356 1356 /* Applicable for X185, A750 */ 1357 1357 static const u32 a750_ifpc_reglist_regs[] = { 1358 - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 1359 - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 1360 - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 1361 - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 1362 - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 1358 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 1359 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 1360 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 1361 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 1362 + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 1363 1363 REG_A6XX_TPL1_NC_MODE_CNTL, 1364 1364 REG_A6XX_SP_NC_MODE_CNTL, 1365 1365 REG_A6XX_CP_DBG_ECO_CNTL,
+5 -5
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 1337 1337 1338 1338 /* Set weights for bicubic filtering */ 1339 1339 if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { 1340 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 1341 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 1340 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0); 1341 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 1342 1342 0x3fe05ff4); 1343 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 1343 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 1344 1344 0x3fa0ebee); 1345 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 1345 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 1346 1346 0x3f5193ed); 1347 - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 1347 + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 1348 1348 0x3f0243f0); 1349 1349 } 1350 1350
+6 -10
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
··· 3296 3296 </reg32> 3297 3297 <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? --> 3298 3298 3299 - <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/> 3300 - <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/> 3301 - <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/> 3302 - <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/> 3303 - <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/> 3299 + <array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A6XX"> 3300 + <reg32 offset="0" name="REG" low="0" high="29"/> 3301 + </array> 3304 3302 3305 - <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage="cmd"/> 3306 - <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage="cmd"/> 3307 - <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage="cmd"/> 3308 - <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage="cmd"/> 3309 - <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage="cmd"/> 3303 + <array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A7XX"> 3304 + <reg32 offset="0" name="REG" low="0" high="29" usage="cmd"/> 3305 + </array> 3310 3306 3311 3307 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/> 3312 3308 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/>