Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: r9a09g047: Add I2C clocks/resets
Add I2C{0..8} clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241216120029.143944-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Biju Das
and committed by
Geert Uytterhoeven
29ebc619
3baf0273
+32
+32
drivers/clk/renesas/r9a09g047-cpg.c
+32
drivers/clk/renesas/r9a09g047-cpg.c
···
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/* PLL Clocks */
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CLK_PLLCM33,
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+
CLK_PLLCLN,
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CLK_PLLDTY,
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CLK_PLLCA55,
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/* Internal Core Clocks */
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CLK_PLLCM33_DIV16,
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CLK_PLLCLN_DIV16,
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CLK_PLLDTY_ACPU,
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CLK_PLLDTY_ACPU_DIV4,
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···
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/* PLL Clocks */
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DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
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/* Internal Core Clocks */
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DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
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+
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DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
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DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
···
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BUS_MSTOP(3, BIT(5))),
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DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
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BUS_MSTOP(3, BIT(14))),
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DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
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BUS_MSTOP(3, BIT(13))),
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DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
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BUS_MSTOP(1, BIT(1))),
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DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
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BUS_MSTOP(1, BIT(2))),
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+
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
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BUS_MSTOP(1, BIT(3))),
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DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
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BUS_MSTOP(1, BIT(4))),
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DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
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BUS_MSTOP(1, BIT(5))),
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DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
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BUS_MSTOP(1, BIT(6))),
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DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
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BUS_MSTOP(1, BIT(7))),
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DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
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BUS_MSTOP(1, BIT(8))),
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110
};
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static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
···
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DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
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DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
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DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
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+
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
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DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
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DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
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DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
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DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
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DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
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DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
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DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
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+
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
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};
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const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {