Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux
Pull hardware timestamp engine updates from Dipen Patel:
"The changes for the hte subsystem include:
- Add Tegra234 HTE provider and relevant DT bindings
- Update MAINTAINERS file for the HTE subsystem"
* tag 'for-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux:
hte: tegra-194: Use proper includes
hte: Use device_match_of_node()
hte: tegra-194: Fix off by one in tegra_hte_map_to_line_id()
hte: tegra: fix 'struct of_device_id' build error
hte: Use of_property_present() for testing DT property presence
gpio: tegra186: Add Tegra234 hte support
hte: handle nvidia,gpio-controller property
hte: Deprecate nvidia,slices property
hte: Add Tegra234 provider
hte: Re-phrase tegra API document
arm64: tegra: Add Tegra234 GTE nodes
dt-bindings: timestamp: Deprecate nvidia,slices property
dt-bindings: timestamp: Add Tegra234 support
MAINTAINERS: Add HTE/timestamp subsystem details
+285
-72
+59
-7
Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml
+59
-7
Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml
···
4
4
$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Tegra194 on chip generic hardware timestamping engine (HTE)
7
+
title: Tegra on chip generic hardware timestamping engine (HTE) provider
8
8
9
9
maintainers:
10
10
- Dipen Patel <dipenp@nvidia.com>
···
23
23
enum:
24
24
- nvidia,tegra194-gte-aon
25
25
- nvidia,tegra194-gte-lic
26
+
- nvidia,tegra234-gte-aon
27
+
- nvidia,tegra234-gte-lic
26
28
27
29
reg:
28
30
maxItems: 1
···
42
40
43
41
nvidia,slices:
44
42
$ref: /schemas/types.yaml#/definitions/uint32
43
+
deprecated: true
45
44
description:
46
45
HTE lines are arranged in 32 bit slice where each bit represents different
47
46
line/signal that it can enable/configure for the timestamp. It is u32
48
-
property and depends on the HTE instance in the chip. The value 3 is for
49
-
GPIO GTE and 11 for IRQ GTE.
50
-
enum: [3, 11]
47
+
property and the value depends on the HTE instance in the chip. The AON
48
+
GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194
49
+
LIC instance has 11 slices and Tegra234 LIC has 17 slices.
50
+
enum: [3, 11, 17]
51
+
52
+
nvidia,gpio-controller:
53
+
$ref: /schemas/types.yaml#/definitions/phandle
54
+
description:
55
+
The phandle to AON gpio controller instance. This is required to handle
56
+
namespace conversion between GPIO and GTE.
51
57
52
58
'#timestamp-cells':
53
59
description:
···
69
59
- compatible
70
60
- reg
71
61
- interrupts
72
-
- nvidia,slices
73
62
- "#timestamp-cells"
63
+
64
+
allOf:
65
+
- if:
66
+
properties:
67
+
compatible:
68
+
contains:
69
+
enum:
70
+
- nvidia,tegra194-gte-aon
71
+
- nvidia,tegra234-gte-aon
72
+
then:
73
+
properties:
74
+
nvidia,slices:
75
+
const: 3
76
+
77
+
- if:
78
+
properties:
79
+
compatible:
80
+
contains:
81
+
enum:
82
+
- nvidia,tegra194-gte-lic
83
+
then:
84
+
properties:
85
+
nvidia,slices:
86
+
const: 11
87
+
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
contains:
92
+
enum:
93
+
- nvidia,tegra234-gte-lic
94
+
then:
95
+
properties:
96
+
nvidia,slices:
97
+
const: 17
98
+
99
+
- if:
100
+
properties:
101
+
compatible:
102
+
contains:
103
+
enum:
104
+
- nvidia,tegra234-gte-aon
105
+
then:
106
+
required:
107
+
- nvidia,gpio-controller
74
108
75
109
additionalProperties: false
76
110
···
125
71
reg = <0xc1e0000 0x10000>;
126
72
interrupts = <0 13 0x4>;
127
73
nvidia,int-threshold = <1>;
128
-
nvidia,slices = <3>;
129
74
#timestamp-cells = <1>;
130
75
};
131
76
···
134
81
reg = <0x3aa0000 0x10000>;
135
82
interrupts = <0 11 0x4>;
136
83
nvidia,int-threshold = <1>;
137
-
nvidia,slices = <11>;
138
84
#timestamp-cells = <1>;
139
85
};
140
86
+1
-1
Documentation/driver-api/hte/index.rst
+1
-1
Documentation/driver-api/hte/index.rst
+47
Documentation/driver-api/hte/tegra-hte.rst
+47
Documentation/driver-api/hte/tegra-hte.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0+
2
+
3
+
HTE Kernel provider driver
4
+
==========================
5
+
6
+
Description
7
+
-----------
8
+
The Nvidia tegra HTE provider also known as GTE (Generic Timestamping Engine)
9
+
driver implements two GTE instances: 1) GPIO GTE and 2) LIC
10
+
(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp
11
+
from the system counter TSC which has 31.25MHz clock rate, and the driver
12
+
converts clock tick rate to nanoseconds before storing it as timestamp value.
13
+
14
+
GPIO GTE
15
+
--------
16
+
17
+
This GTE instance timestamps GPIO in real time. For that to happen GPIO
18
+
needs to be configured as input. Only the always on (AON) GPIO controller
19
+
instance supports timestamping GPIOs in real time as it is tightly coupled with
20
+
the GPIO GTE. To support this, GPIOLIB adds two optional APIs as mentioned
21
+
below. The GPIO GTE code supports both kernel and userspace consumers. The
22
+
kernel space consumers can directly talk to HTE subsystem while userspace
23
+
consumers timestamp requests go through GPIOLIB CDEV framework to HTE
24
+
subsystem. The hte devicetree binding described at
25
+
``Documentation/devicetree/bindings/timestamp`` provides an example of how a
26
+
consumer can request an GPIO line.
27
+
28
+
See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns().
29
+
30
+
For userspace consumers, GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE flag must be
31
+
specified during IOCTL calls. Refer to ``tools/gpio/gpio-event-mon.c``, which
32
+
returns the timestamp in nanoseconds.
33
+
34
+
LIC (Legacy Interrupt Controller) IRQ GTE
35
+
-----------------------------------------
36
+
37
+
This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree
38
+
binding described at ``Documentation/devicetree/bindings/timestamp``
39
+
provides an example of how a consumer can request an IRQ line. Since it is a
40
+
one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ
41
+
number that they are interested in. There is no userspace consumer support for
42
+
this GTE instance in the HTE framework.
43
+
44
+
The provider source code of both IRQ and GPIO GTE instances is located at
45
+
``drivers/hte/hte-tegra194.c``. The test driver
46
+
``drivers/hte/hte-tegra194-test.c`` demonstrates HTE API usage for both IRQ
47
+
and GPIO GTE.
-48
Documentation/driver-api/hte/tegra194-hte.rst
-48
Documentation/driver-api/hte/tegra194-hte.rst
···
1
-
.. SPDX-License-Identifier: GPL-2.0+
2
-
3
-
HTE Kernel provider driver
4
-
==========================
5
-
6
-
Description
7
-
-----------
8
-
The Nvidia tegra194 HTE provider driver implements two GTE
9
-
(Generic Timestamping Engine) instances: 1) GPIO GTE and 2) LIC
10
-
(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the
11
-
timestamp from the system counter TSC which has 31.25MHz clock rate, and the
12
-
driver converts clock tick rate to nanoseconds before storing it as timestamp
13
-
value.
14
-
15
-
GPIO GTE
16
-
--------
17
-
18
-
This GTE instance timestamps GPIO in real time. For that to happen GPIO
19
-
needs to be configured as input. The always on (AON) GPIO controller instance
20
-
supports timestamping GPIOs in real time and it has 39 GPIO lines. The GPIO GTE
21
-
and AON GPIO controller are tightly coupled as it requires very specific bits
22
-
to be set in GPIO config register before GPIO GTE can be used, for that GPIOLIB
23
-
adds two optional APIs as below. The GPIO GTE code supports both kernel
24
-
and userspace consumers. The kernel space consumers can directly talk to HTE
25
-
subsystem while userspace consumers timestamp requests go through GPIOLIB CDEV
26
-
framework to HTE subsystem.
27
-
28
-
See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns().
29
-
30
-
For userspace consumers, GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE flag must be
31
-
specified during IOCTL calls. Refer to ``tools/gpio/gpio-event-mon.c``, which
32
-
returns the timestamp in nanoseconds.
33
-
34
-
LIC (Legacy Interrupt Controller) IRQ GTE
35
-
-----------------------------------------
36
-
37
-
This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ
38
-
lines which this instance can add timestamps to in real time. The hte
39
-
devicetree binding described at ``Documentation/devicetree/bindings/timestamp``
40
-
provides an example of how a consumer can request an IRQ line. Since it is a
41
-
one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ
42
-
number that they are interested in. There is no userspace consumer support for
43
-
this GTE instance in the HTE framework.
44
-
45
-
The provider source code of both IRQ and GPIO GTE instances is located at
46
-
``drivers/hte/hte-tegra194.c``. The test driver
47
-
``drivers/hte/hte-tegra194-test.c`` demonstrates HTE API usage for both IRQ
48
-
and GPIO GTE.
+3
MAINTAINERS
+3
MAINTAINERS
···
9489
9489
9490
9490
HTE SUBSYSTEM
9491
9491
M: Dipen Patel <dipenp@nvidia.com>
9492
+
L: timestamp@lists.linux.dev
9493
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git
9494
+
Q: https://patchwork.kernel.org/project/timestamp/list/
9492
9495
S: Maintained
9493
9496
F: Documentation/devicetree/bindings/timestamp/
9494
9497
F: Documentation/driver-api/hte/
+17
arch/arm64/boot/dts/nvidia/tegra234.dtsi
+17
arch/arm64/boot/dts/nvidia/tegra234.dtsi
···
1154
1154
clock-names = "fuse";
1155
1155
};
1156
1156
1157
+
hte_lic: hardware-timestamp@3aa0000 {
1158
+
compatible = "nvidia,tegra234-gte-lic";
1159
+
reg = <0x0 0x3aa0000 0x0 0x10000>;
1160
+
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1161
+
nvidia,int-threshold = <1>;
1162
+
#timestamp-cells = <1>;
1163
+
};
1164
+
1157
1165
hsp_top0: hsp@3c00000 {
1158
1166
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1159
1167
reg = <0x0 0x03c00000 0x0 0xa0000>;
···
1677
1669
*/
1678
1670
interrupt-names = "shared1", "shared2", "shared3", "shared4";
1679
1671
#mbox-cells = <2>;
1672
+
};
1673
+
1674
+
hte_aon: hardware-timestamp@c1e0000 {
1675
+
compatible = "nvidia,tegra234-gte-aon";
1676
+
reg = <0x0 0xc1e0000 0x0 0x10000>;
1677
+
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1678
+
nvidia,int-threshold = <1>;
1679
+
nvidia,gpio-controller = <&gpio_aon>;
1680
+
#timestamp-cells = <1>;
1680
1681
};
1681
1682
1682
1683
gen2_i2c: i2c@c240000 {
+1
drivers/gpio/gpio-tegra186.c
+1
drivers/gpio/gpio-tegra186.c
+1
-1
drivers/hte/hte-tegra194-test.c
+1
-1
drivers/hte/hte-tegra194-test.c
···
16
16
#include <linux/workqueue.h>
17
17
18
18
/*
19
-
* This sample HTE GPIO test driver demonstrates HTE API usage by enabling
19
+
* This sample HTE test driver demonstrates HTE API usage by enabling
20
20
* hardware timestamp on gpio_in and specified LIC IRQ lines.
21
21
*
22
22
* Note: gpio_out and gpio_in need to be shorted externally in order for this
+155
-14
drivers/hte/hte-tegra194.c
+155
-14
drivers/hte/hte-tegra194.c
···
62
62
#define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25
63
63
#define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26
64
64
#define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27
65
+
#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28
66
+
#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29
67
+
#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30
68
+
#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31
65
69
66
70
#define HTE_TECTRL 0x0
67
71
#define HTE_TETSCH 0x4
···
118
114
119
115
struct tegra_hte_data {
120
116
enum tegra_hte_type type;
117
+
u32 slices;
121
118
u32 map_sz;
122
119
u32 sec_map_sz;
123
120
const struct tegra_hte_line_mapped *map;
···
225
220
[39] = {NV_AON_SLICE_INVALID, 0},
226
221
};
227
222
228
-
static const struct tegra_hte_data aon_hte = {
223
+
static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = {
224
+
/* gpio, slice, bit_index */
225
+
/* AA port */
226
+
[0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
227
+
[1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
228
+
[2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
229
+
[3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
230
+
[4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
231
+
[5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
232
+
[6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
233
+
[7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
234
+
/* BB port */
235
+
[8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
236
+
[9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
237
+
[10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
238
+
[11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
239
+
/* CC port */
240
+
[12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
241
+
[13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
242
+
[14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
243
+
[15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
244
+
[16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
245
+
[17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
246
+
[18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
247
+
[19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
248
+
/* DD port */
249
+
[20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
250
+
[21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
251
+
[22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
252
+
/* EE port */
253
+
[23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
254
+
[24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
255
+
[25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
256
+
[26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
257
+
[27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
258
+
[28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
259
+
[29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
260
+
[30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
261
+
/* GG port */
262
+
[31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
263
+
};
264
+
265
+
static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = {
266
+
/* gpio, slice, bit_index */
267
+
/* AA port */
268
+
[0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
269
+
[1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
270
+
[2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
271
+
[3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
272
+
[4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
273
+
[5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
274
+
[6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
275
+
[7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
276
+
/* BB port */
277
+
[8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
278
+
[9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
279
+
[10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
280
+
[11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
281
+
[12] = {NV_AON_SLICE_INVALID, 0},
282
+
[13] = {NV_AON_SLICE_INVALID, 0},
283
+
[14] = {NV_AON_SLICE_INVALID, 0},
284
+
[15] = {NV_AON_SLICE_INVALID, 0},
285
+
/* CC port */
286
+
[16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
287
+
[17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
288
+
[18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
289
+
[19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
290
+
[20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
291
+
[21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
292
+
[22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
293
+
[23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
294
+
/* DD port */
295
+
[24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
296
+
[25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
297
+
[26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
298
+
[27] = {NV_AON_SLICE_INVALID, 0},
299
+
[28] = {NV_AON_SLICE_INVALID, 0},
300
+
[29] = {NV_AON_SLICE_INVALID, 0},
301
+
[30] = {NV_AON_SLICE_INVALID, 0},
302
+
[31] = {NV_AON_SLICE_INVALID, 0},
303
+
/* EE port */
304
+
[32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
305
+
[33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
306
+
[34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
307
+
[35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
308
+
[36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
309
+
[37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
310
+
[38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
311
+
[39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
312
+
/* GG port */
313
+
[40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
314
+
};
315
+
316
+
static const struct tegra_hte_data t194_aon_hte = {
229
317
.map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),
230
318
.map = tegra194_aon_gpio_map,
231
319
.sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map),
232
320
.sec_map = tegra194_aon_gpio_sec_map,
233
321
.type = HTE_TEGRA_TYPE_GPIO,
322
+
.slices = 3,
234
323
};
235
324
236
-
static const struct tegra_hte_data lic_hte = {
325
+
static const struct tegra_hte_data t234_aon_hte = {
326
+
.map_sz = ARRAY_SIZE(tegra234_aon_gpio_map),
327
+
.map = tegra234_aon_gpio_map,
328
+
.sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map),
329
+
.sec_map = tegra234_aon_gpio_sec_map,
330
+
.type = HTE_TEGRA_TYPE_GPIO,
331
+
.slices = 3,
332
+
};
333
+
334
+
static const struct tegra_hte_data t194_lic_hte = {
237
335
.map_sz = 0,
238
336
.map = NULL,
239
337
.type = HTE_TEGRA_TYPE_LIC,
338
+
.slices = 11,
339
+
};
340
+
341
+
static const struct tegra_hte_data t234_lic_hte = {
342
+
.map_sz = 0,
343
+
.map = NULL,
344
+
.type = HTE_TEGRA_TYPE_LIC,
345
+
.slices = 17,
240
346
};
241
347
242
348
static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg)
···
367
251
{
368
252
369
253
if (m) {
370
-
if (eid > map_sz)
254
+
if (eid >= map_sz)
371
255
return -EINVAL;
372
256
if (m[eid].slice == NV_AON_SLICE_INVALID)
373
257
return -EINVAL;
···
650
534
}
651
535
652
536
static const struct of_device_id tegra_hte_of_match[] = {
653
-
{ .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte},
654
-
{ .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte},
537
+
{ .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte},
538
+
{ .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
539
+
{ .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte},
540
+
{ .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
655
541
{ }
656
542
};
657
543
MODULE_DEVICE_TABLE(of, tegra_hte_of_match);
···
679
561
return !strcmp(chip->label, data);
680
562
}
681
563
564
+
static int tegra_gpiochip_match(struct gpio_chip *chip, void *data)
565
+
{
566
+
return chip->fwnode == of_node_to_fwnode(data);
567
+
}
568
+
682
569
static int tegra_hte_probe(struct platform_device *pdev)
683
570
{
684
571
int ret;
···
692
569
struct device *dev;
693
570
struct tegra_hte_soc *hte_dev;
694
571
struct hte_chip *gc;
572
+
struct device_node *gpio_ctrl;
695
573
696
574
dev = &pdev->dev;
697
-
698
-
ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices);
699
-
if (ret != 0) {
700
-
dev_err(dev, "Could not read slices\n");
701
-
return -EINVAL;
702
-
}
703
-
nlines = slices << 5;
704
575
705
576
hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL);
706
577
if (!hte_dev)
···
706
589
707
590
dev_set_drvdata(&pdev->dev, hte_dev);
708
591
hte_dev->prov_data = of_device_get_match_data(&pdev->dev);
592
+
593
+
ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices);
594
+
if (ret != 0)
595
+
slices = hte_dev->prov_data->slices;
596
+
597
+
dev_dbg(dev, "slices:%d\n", slices);
598
+
nlines = slices << 5;
709
599
710
600
hte_dev->regs = devm_platform_ioremap_resource(pdev, 0);
711
601
if (IS_ERR(hte_dev->regs))
···
759
635
760
636
gc->match_from_linedata = tegra_hte_match_from_linedata;
761
637
762
-
hte_dev->c = gpiochip_find("tegra194-gpio-aon",
763
-
tegra_get_gpiochip_from_name);
638
+
if (of_device_is_compatible(dev->of_node,
639
+
"nvidia,tegra194-gte-aon")) {
640
+
hte_dev->c = gpiochip_find("tegra194-gpio-aon",
641
+
tegra_get_gpiochip_from_name);
642
+
} else {
643
+
gpio_ctrl = of_parse_phandle(dev->of_node,
644
+
"nvidia,gpio-controller",
645
+
0);
646
+
if (!gpio_ctrl) {
647
+
dev_err(dev,
648
+
"gpio controller node not found\n");
649
+
return -ENODEV;
650
+
}
651
+
652
+
hte_dev->c = gpiochip_find(gpio_ctrl,
653
+
tegra_gpiochip_match);
654
+
of_node_put(gpio_ctrl);
655
+
}
656
+
764
657
if (!hte_dev->c)
765
658
return dev_err_probe(dev, -EPROBE_DEFER,
766
659
"wait for gpio controller\n");