Merge tag 'amd-drm-next-6.19-2025-11-07' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

+1 -1

MAINTAINERS

··· 1080 1080 M: Jun Lei <jun.lei@amd.com> 1081 1081 S: Supported 1082 1082 F: drivers/gpu/drm/amd/display/dc/dml/ 1083 - F: drivers/gpu/drm/amd/display/dc/dml2/ 1083 + F: drivers/gpu/drm/amd/display/dc/dml2_0/ 1084 1084 1085 1085 AMD FAM15H PROCESSOR POWER MONITORING DRIVER 1086 1086 M: Huang Rui <ray.huang@amd.com>

+1 -5

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 1316 1316 bool apu_prefer_gtt; 1317 1317 1318 1318 bool userq_halt_for_enforce_isolation; 1319 + struct work_struct userq_reset_work; 1319 1320 struct amdgpu_uid *uid_info; 1320 1321 1321 1322 /* KFD ··· 1540 1539 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1541 1540 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1542 1541 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1543 - #define amdgpu_asic_flush_hdp(adev, r) \ 1544 - ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1545 - #define amdgpu_asic_invalidate_hdp(adev, r) \ 1546 - ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1547 - ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1548 1542 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1549 1543 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1550 1544 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))

+4

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

··· 1274 1274 1275 1275 (void)amdgpu_vm_bo_unmap(adev, bo_va, entry->va); 1276 1276 1277 + /* VM entity stopped if process killed, don't clear freed pt bo */ 1278 + if (!amdgpu_vm_ready(vm)) 1279 + return 0; 1280 + 1277 1281 (void)amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update); 1278 1282 1279 1283 (void)amdgpu_sync_fence(sync, bo_va->last_pt_update, GFP_KERNEL);

+123 -18

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 71 71 72 72 #include "amdgpu_xgmi.h" 73 73 #include "amdgpu_ras.h" 74 + #include "amdgpu_ras_mgr.h" 74 75 #include "amdgpu_pmu.h" 75 76 #include "amdgpu_fru_eeprom.h" 76 77 #include "amdgpu_reset.h" ··· 179 178 BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) | 180 179 BIT(AMD_IP_BLOCK_TYPE_PSP) 181 180 }; 181 + 182 + static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev); 183 + static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev); 184 + static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev); 182 185 183 186 static void amdgpu_device_load_switch_state(struct amdgpu_device *adev); 184 187 ··· 2499 2494 [AMD_IP_BLOCK_TYPE_VPE] = "vpe", 2500 2495 [AMD_IP_BLOCK_TYPE_UMSCH_MM] = "umsch_mm", 2501 2496 [AMD_IP_BLOCK_TYPE_ISP] = "isp", 2497 + [AMD_IP_BLOCK_TYPE_RAS] = "ras", 2502 2498 }; 2503 2499 2504 2500 static const char *ip_block_name(struct amdgpu_device *adev, enum amd_ip_block_type type) ··· 3790 3784 */ 3791 3785 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) 3792 3786 { 3793 - int i, r; 3787 + int i, r, rec; 3794 3788 3795 3789 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 3796 3790 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); ··· 3813 3807 3814 3808 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]); 3815 3809 if (r) 3816 - return r; 3810 + goto unwind; 3817 3811 } 3818 3812 3819 3813 return 0; 3814 + unwind: 3815 + rec = amdgpu_device_ip_resume_phase3(adev); 3816 + if (rec) 3817 + dev_err(adev->dev, 3818 + "amdgpu_device_ip_resume_phase3 failed during unwind: %d\n", 3819 + rec); 3820 + 3821 + amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW); 3822 + 3823 + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); 3824 + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); 3825 + 3826 + return r; 3820 3827 } 3821 3828 3822 3829 /** ··· 3845 3826 */ 3846 3827 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) 3847 3828 { 3848 - int i, r; 3829 + int i, r, rec; 3849 3830 3850 3831 if (adev->in_s0ix) 3851 3832 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry); ··· 3908 3889 3909 3890 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]); 3910 3891 if (r) 3911 - return r; 3892 + goto unwind; 3912 3893 3913 3894 /* handle putting the SMC in the appropriate state */ 3914 3895 if (!amdgpu_sriov_vf(adev)) { ··· 3918 3899 dev_err(adev->dev, 3919 3900 "SMC failed to set mp1 state %d, %d\n", 3920 3901 adev->mp1_state, r); 3921 - return r; 3902 + goto unwind; 3922 3903 } 3923 3904 } 3924 3905 } 3925 3906 } 3926 3907 3927 3908 return 0; 3909 + unwind: 3910 + /* suspend phase 2 = resume phase 1 + resume phase 2 */ 3911 + rec = amdgpu_device_ip_resume_phase1(adev); 3912 + if (rec) { 3913 + dev_err(adev->dev, 3914 + "amdgpu_device_ip_resume_phase1 failed during unwind: %d\n", 3915 + rec); 3916 + return r; 3917 + } 3918 + 3919 + rec = amdgpu_device_fw_loading(adev); 3920 + if (rec) { 3921 + dev_err(adev->dev, 3922 + "amdgpu_device_fw_loading failed during unwind: %d\n", 3923 + rec); 3924 + return r; 3925 + } 3926 + 3927 + rec = amdgpu_device_ip_resume_phase2(adev); 3928 + if (rec) { 3929 + dev_err(adev->dev, 3930 + "amdgpu_device_ip_resume_phase2 failed during unwind: %d\n", 3931 + rec); 3932 + return r; 3933 + } 3934 + 3935 + return r; 3928 3936 } 3929 3937 3930 3938 /** ··· 4653 4607 } 4654 4608 4655 4609 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); 4610 + INIT_WORK(&adev->userq_reset_work, amdgpu_userq_reset_work); 4656 4611 4657 4612 adev->gfx.gfx_off_req_count = 1; 4658 4613 adev->gfx.gfx_off_residency = 0; ··· 5276 5229 int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) 5277 5230 { 5278 5231 struct amdgpu_device *adev = drm_to_adev(dev); 5279 - int r = 0; 5232 + int r, rec; 5280 5233 5281 5234 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 5282 5235 return 0; ··· 5292 5245 return r; 5293 5246 } 5294 5247 5295 - if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D3)) 5296 - dev_warn(adev->dev, "smart shift update failed\n"); 5248 + r = amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D3); 5249 + if (r) 5250 + goto unwind_sriov; 5297 5251 5298 5252 if (notify_clients) 5299 5253 drm_client_dev_suspend(adev_to_drm(adev)); ··· 5305 5257 5306 5258 r = amdgpu_device_ip_suspend_phase1(adev); 5307 5259 if (r) 5308 - return r; 5260 + goto unwind_smartshift; 5309 5261 5310 5262 amdgpu_amdkfd_suspend(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); 5311 5263 r = amdgpu_userq_suspend(adev); 5312 5264 if (r) 5313 - return r; 5265 + goto unwind_ip_phase1; 5314 5266 5315 5267 r = amdgpu_device_evict_resources(adev); 5316 5268 if (r) 5317 - return r; 5269 + goto unwind_userq; 5318 5270 5319 5271 amdgpu_ttm_set_buffer_funcs_status(adev, false); 5320 5272 ··· 5322 5274 5323 5275 r = amdgpu_device_ip_suspend_phase2(adev); 5324 5276 if (r) 5325 - return r; 5277 + goto unwind_evict; 5326 5278 5327 5279 if (amdgpu_sriov_vf(adev)) 5328 5280 amdgpu_virt_release_full_gpu(adev, false); 5329 5281 5330 - r = amdgpu_dpm_notify_rlc_state(adev, false); 5331 - if (r) 5332 - return r; 5333 - 5334 5282 return 0; 5283 + 5284 + unwind_evict: 5285 + if (adev->mman.buffer_funcs_ring->sched.ready) 5286 + amdgpu_ttm_set_buffer_funcs_status(adev, true); 5287 + amdgpu_fence_driver_hw_init(adev); 5288 + 5289 + unwind_userq: 5290 + rec = amdgpu_userq_resume(adev); 5291 + if (rec) { 5292 + dev_warn(adev->dev, "failed to re-initialize user queues: %d\n", rec); 5293 + return r; 5294 + } 5295 + rec = amdgpu_amdkfd_resume(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); 5296 + if (rec) { 5297 + dev_warn(adev->dev, "failed to re-initialize kfd: %d\n", rec); 5298 + return r; 5299 + } 5300 + 5301 + unwind_ip_phase1: 5302 + /* suspend phase 1 = resume phase 3 */ 5303 + rec = amdgpu_device_ip_resume_phase3(adev); 5304 + if (rec) { 5305 + dev_warn(adev->dev, "failed to re-initialize IPs phase1: %d\n", rec); 5306 + return r; 5307 + } 5308 + 5309 + unwind_smartshift: 5310 + rec = amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D0); 5311 + if (rec) { 5312 + dev_warn(adev->dev, "failed to re-update smart shift: %d\n", rec); 5313 + return r; 5314 + } 5315 + 5316 + if (notify_clients) 5317 + drm_client_dev_resume(adev_to_drm(adev)); 5318 + 5319 + amdgpu_ras_resume(adev); 5320 + 5321 + unwind_sriov: 5322 + if (amdgpu_sriov_vf(adev)) { 5323 + rec = amdgpu_virt_request_full_gpu(adev, true); 5324 + if (rec) { 5325 + dev_warn(adev->dev, "failed to reinitialize sriov: %d\n", rec); 5326 + return r; 5327 + } 5328 + } 5329 + 5330 + adev->in_suspend = adev->in_s0ix = adev->in_s3 = false; 5331 + 5332 + return r; 5335 5333 } 5336 5334 5337 5335 static inline int amdgpu_virt_resume(struct amdgpu_device *adev) ··· 6083 5989 if (r) 6084 5990 goto out; 6085 5991 5992 + r = amdgpu_userq_post_reset(tmp_adev, vram_lost); 5993 + if (r) 5994 + goto out; 5995 + 6086 5996 drm_client_dev_resume(adev_to_drm(tmp_adev)); 6087 5997 6088 5998 /* ··· 6309 6211 if (!amdgpu_sriov_vf(adev)) 6310 6212 cancel_work(&adev->reset_work); 6311 6213 #endif 6214 + cancel_work(&adev->userq_reset_work); 6312 6215 6313 6216 if (adev->kfd.dev) 6314 6217 cancel_work(&adev->kfd.reset_work); ··· 6429 6330 if (!need_emergency_restart && !amdgpu_reset_in_dpc(adev) && 6430 6331 amdgpu_device_ip_need_full_reset(tmp_adev)) 6431 6332 amdgpu_ras_suspend(tmp_adev); 6333 + 6334 + amdgpu_userq_pre_reset(tmp_adev); 6432 6335 6433 6336 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 6434 6337 struct amdgpu_ring *ring = tmp_adev->rings[i]; ··· 6661 6560 goto end_reset; 6662 6561 } 6663 6562 6563 + /* Cannot be called after locking reset domain */ 6564 + amdgpu_ras_pre_reset(adev, &device_list); 6565 + 6664 6566 /* We need to lock reset domain only once both for XGMI and single device */ 6665 6567 amdgpu_device_recovery_get_reset_lock(adev, &device_list); 6666 6568 ··· 6694 6590 amdgpu_device_gpu_resume(adev, &device_list, need_emergency_restart); 6695 6591 reset_unlock: 6696 6592 amdgpu_device_recovery_put_reset_lock(adev, &device_list); 6593 + amdgpu_ras_post_reset(adev, &device_list); 6697 6594 end_reset: 6698 6595 if (hive) { 6699 6596 mutex_unlock(&hive->hive_lock); ··· 7432 7327 return; 7433 7328 } 7434 7329 7435 - amdgpu_asic_flush_hdp(adev, ring); 7330 + amdgpu_hdp_flush(adev, ring); 7436 7331 } 7437 7332 7438 7333 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, ··· 7445 7340 if (adev->gmc.xgmi.connected_to_cpu) 7446 7341 return; 7447 7342 7448 - amdgpu_asic_invalidate_hdp(adev, ring); 7343 + amdgpu_hdp_invalidate(adev, ring); 7449 7344 } 7450 7345 7451 7346 int amdgpu_in_reset(struct amdgpu_device *adev)

+7

drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c

··· 81 81 struct drm_gem_object *obj = dmabuf->priv; 82 82 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 83 83 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 84 + int r; 84 85 85 86 if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) && 86 87 pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) 87 88 attach->peer2peer = false; 88 89 90 + r = dma_resv_lock(bo->tbo.base.resv, NULL); 91 + if (r) 92 + return r; 93 + 89 94 amdgpu_vm_bo_update_shared(bo); 95 + 96 + dma_resv_unlock(bo->tbo.base.resv); 90 97 91 98 return 0; 92 99 }

+7 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

··· 2625 2625 { 2626 2626 struct drm_device *drm_dev = dev_get_drvdata(dev); 2627 2627 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2628 + int r; 2628 2629 2629 - if (amdgpu_acpi_should_gpu_reset(adev)) 2630 - return amdgpu_asic_reset(adev); 2630 + if (amdgpu_acpi_should_gpu_reset(adev)) { 2631 + amdgpu_device_lock_reset_domain(adev->reset_domain); 2632 + r = amdgpu_asic_reset(adev); 2633 + amdgpu_device_unlock_reset_domain(adev->reset_domain); 2634 + return r; 2635 + } 2631 2636 2632 2637 return 0; 2633 2638 }

+16

drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c

··· 66 66 0); 67 67 } 68 68 } 69 + 70 + void amdgpu_hdp_invalidate(struct amdgpu_device *adev, struct amdgpu_ring *ring) 71 + { 72 + if (adev->asic_funcs && adev->asic_funcs->invalidate_hdp) 73 + adev->asic_funcs->invalidate_hdp(adev, ring); 74 + else if (adev->hdp.funcs && adev->hdp.funcs->invalidate_hdp) 75 + adev->hdp.funcs->invalidate_hdp(adev, ring); 76 + } 77 + 78 + void amdgpu_hdp_flush(struct amdgpu_device *adev, struct amdgpu_ring *ring) 79 + { 80 + if (adev->asic_funcs && adev->asic_funcs->flush_hdp) 81 + adev->asic_funcs->flush_hdp(adev, ring); 82 + else if (adev->hdp.funcs && adev->hdp.funcs->flush_hdp) 83 + adev->hdp.funcs->flush_hdp(adev, ring); 84 + }

+4

drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h

··· 46 46 int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev); 47 47 void amdgpu_hdp_generic_flush(struct amdgpu_device *adev, 48 48 struct amdgpu_ring *ring); 49 + void amdgpu_hdp_invalidate(struct amdgpu_device *adev, 50 + struct amdgpu_ring *ring); 51 + void amdgpu_hdp_flush(struct amdgpu_device *adev, 52 + struct amdgpu_ring *ring); 49 53 #endif /* __AMDGPU_HDP_H__ */

+1 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c

··· 287 287 if (!range) 288 288 return; 289 289 290 - if (range->hmm_range.hmm_pfns) 291 - kvfree(range->hmm_range.hmm_pfns); 292 - 290 + kvfree(range->hmm_range.hmm_pfns); 293 291 amdgpu_bo_unref(&range->bo); 294 292 kfree(range); 295 293 }

+15 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

··· 176 176 177 177 if (!ring->sched.ready) { 178 178 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); 179 - return -EINVAL; 179 + r = -EINVAL; 180 + goto free_fence; 180 181 } 181 182 182 183 if (vm && !job->vmid) { 183 184 dev_err(adev->dev, "VM IB without ID\n"); 184 - return -EINVAL; 185 + r = -EINVAL; 186 + goto free_fence; 185 187 } 186 188 187 189 if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) && 188 190 (!ring->funcs->secure_submission_supported)) { 189 191 dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name); 190 - return -EINVAL; 192 + r = -EINVAL; 193 + goto free_fence; 191 194 } 192 195 193 196 alloc_size = ring->funcs->emit_frame_size + num_ibs * ··· 199 196 r = amdgpu_ring_alloc(ring, alloc_size); 200 197 if (r) { 201 198 dev_err(adev->dev, "scheduling IB failed (%d).\n", r); 202 - return r; 199 + goto free_fence; 203 200 } 204 201 205 202 need_ctx_switch = ring->current_ctx != fence_ctx; ··· 305 302 return r; 306 303 } 307 304 *f = &af->base; 305 + /* get a ref for the job */ 306 + if (job) 307 + dma_fence_get(*f); 308 308 309 309 if (ring->funcs->insert_end) 310 310 ring->funcs->insert_end(ring); ··· 334 328 amdgpu_ring_commit(ring); 335 329 336 330 return 0; 331 + 332 + free_fence: 333 + if (!job) 334 + kfree(af); 335 + return r; 337 336 } 338 337 339 338 /**

+21 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

··· 130 130 } 131 131 132 132 /* attempt a per ring reset */ 133 - if (unlikely(adev->debug_disable_gpu_ring_reset)) { 134 - dev_err(adev->dev, "Ring reset disabled by debug mask\n"); 135 - } else if (amdgpu_gpu_recovery && 136 - amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && 137 - ring->funcs->reset) { 133 + if (amdgpu_gpu_recovery && 134 + amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && 135 + ring->funcs->reset) { 138 136 dev_err(adev->dev, "Starting %s ring reset\n", 139 137 s_job->sched->name); 140 138 r = amdgpu_ring_reset(ring, job->vmid, job->hw_fence); ··· 293 295 294 296 amdgpu_sync_free(&job->explicit_sync); 295 297 298 + if (job->hw_fence->base.ops) 299 + dma_fence_put(&job->hw_fence->base); 300 + else 301 + kfree(job->hw_fence); 302 + if (job->hw_vm_fence->base.ops) 303 + dma_fence_put(&job->hw_vm_fence->base); 304 + else 305 + kfree(job->hw_vm_fence); 306 + 296 307 kfree(job); 297 308 } 298 309 ··· 330 323 amdgpu_sync_free(&job->explicit_sync); 331 324 if (job->gang_submit != &job->base.s_fence->scheduled) 332 325 dma_fence_put(job->gang_submit); 326 + 327 + if (job->hw_fence->base.ops) 328 + dma_fence_put(&job->hw_fence->base); 329 + else 330 + kfree(job->hw_fence); 331 + if (job->hw_vm_fence->base.ops) 332 + dma_fence_put(&job->hw_vm_fence->base); 333 + else 334 + kfree(job->hw_vm_fence); 333 335 334 336 kfree(job); 335 337 }

+4 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

··· 2355 2355 if (!ret && !psp->securedisplay_context.context.resp_status) { 2356 2356 psp->securedisplay_context.context.initialized = true; 2357 2357 mutex_init(&psp->securedisplay_context.mutex); 2358 - } else 2358 + } else { 2359 + /* don't try again */ 2360 + psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2359 2361 return ret; 2362 + } 2360 2363 2361 2364 mutex_lock(&psp->securedisplay_context.mutex); 2362 2365

+41 -7

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

··· 1661 1661 inject_req.address = info->address; 1662 1662 inject_req.error_type = info->head.type; 1663 1663 inject_req.instance_mask = info->instance_mask; 1664 - inject_req.value = info->value; 1664 + inject_req.method = info->value; 1665 1665 1666 1666 return amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__INJECT_ERROR, 1667 1667 &inject_req, sizeof(inject_req), &rsp, sizeof(rsp)); ··· 2921 2921 type = amdgpu_ras_get_fatal_error_event(adev); 2922 2922 list_for_each_entry(remote_adev, 2923 2923 device_list_handle, gmc.xgmi.head) { 2924 - amdgpu_ras_query_err_status(remote_adev); 2925 - amdgpu_ras_log_on_err_counter(remote_adev, type); 2924 + if (amdgpu_uniras_enabled(remote_adev)) { 2925 + amdgpu_ras_mgr_update_ras_ecc(remote_adev); 2926 + } else { 2927 + amdgpu_ras_query_err_status(remote_adev); 2928 + amdgpu_ras_log_on_err_counter(remote_adev, type); 2929 + } 2926 2930 } 2927 2931 2928 2932 } ··· 3158 3154 int i = 0; 3159 3155 enum amdgpu_memory_partition save_nps; 3160 3156 3161 - save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; 3162 - bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); 3157 + if (!amdgpu_ras_smu_eeprom_supported(adev)) { 3158 + save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; 3159 + bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); 3160 + } else { 3161 + save_nps = nps; 3162 + } 3163 3163 3164 3164 if (save_nps == nps) { 3165 3165 if (amdgpu_umc_pages_in_a_row(adev, err_data, ··· 3229 3221 3230 3222 if (from_rom) { 3231 3223 /* there is no pa recs in V3, so skip pa recs processing */ 3232 - if (control->tbl_hdr.version < RAS_TABLE_VER_V3) { 3224 + if ((control->tbl_hdr.version < RAS_TABLE_VER_V3) && 3225 + !amdgpu_ras_smu_eeprom_supported(adev)) { 3233 3226 for (i = 0; i < pages; i++) { 3234 3227 if (control->ras_num_recs - i >= adev->umc.retire_unit) { 3235 3228 if ((bps[i].address == bps[i + 1].address) && ··· 3361 3352 /*In V3, there is no pa recs, and some cases(when address==0) may be parsed 3362 3353 as pa recs, so add verion check to avoid it. 3363 3354 */ 3364 - if (control->tbl_hdr.version < RAS_TABLE_VER_V3) { 3355 + if ((control->tbl_hdr.version < RAS_TABLE_VER_V3) && 3356 + !amdgpu_ras_smu_eeprom_supported(adev)) { 3365 3357 for (i = 0; i < control->ras_num_recs; i++) { 3366 3358 if ((control->ras_num_recs - i) >= adev->umc.retire_unit) { 3367 3359 if ((bps[i].address == bps[i + 1].address) && ··· 3777 3767 return 0; 3778 3768 3779 3769 control = &con->eeprom_control; 3770 + con->ras_smu_drv = amdgpu_dpm_get_ras_smu_driver(adev); 3771 + 3780 3772 ret = amdgpu_ras_eeprom_init(control); 3781 3773 control->is_eeprom_valid = !ret; 3782 3774 ··· 5682 5670 mutex_unlock(&con->critical_region_lock); 5683 5671 5684 5672 return ret; 5673 + } 5674 + 5675 + void amdgpu_ras_pre_reset(struct amdgpu_device *adev, 5676 + struct list_head *device_list) 5677 + { 5678 + struct amdgpu_device *tmp_adev = NULL; 5679 + 5680 + list_for_each_entry(tmp_adev, device_list, reset_list) { 5681 + if (amdgpu_uniras_enabled(tmp_adev)) 5682 + amdgpu_ras_mgr_pre_reset(tmp_adev); 5683 + } 5684 + } 5685 + 5686 + void amdgpu_ras_post_reset(struct amdgpu_device *adev, 5687 + struct list_head *device_list) 5688 + { 5689 + struct amdgpu_device *tmp_adev = NULL; 5690 + 5691 + list_for_each_entry(tmp_adev, device_list, reset_list) { 5692 + if (amdgpu_uniras_enabled(tmp_adev)) 5693 + amdgpu_ras_mgr_post_reset(tmp_adev); 5694 + } 5685 5695 }

+35

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

··· 503 503 uint64_t size; 504 504 }; 505 505 506 + struct ras_eeprom_table_version { 507 + uint32_t minor : 16; 508 + uint32_t major : 16; 509 + }; 510 + 511 + struct ras_eeprom_smu_funcs { 512 + int (*get_ras_table_version)(struct amdgpu_device *adev, 513 + uint32_t *table_version); 514 + int (*get_badpage_count)(struct amdgpu_device *adev, uint32_t *count, uint32_t timeout); 515 + int (*get_badpage_mca_addr)(struct amdgpu_device *adev, uint16_t index, uint64_t *mca_addr); 516 + int (*set_timestamp)(struct amdgpu_device *adev, uint64_t timestamp); 517 + int (*get_timestamp)(struct amdgpu_device *adev, 518 + uint16_t index, uint64_t *timestamp); 519 + int (*get_badpage_ipid)(struct amdgpu_device *adev, uint16_t index, uint64_t *ipid); 520 + int (*erase_ras_table)(struct amdgpu_device *adev, uint32_t *result); 521 + }; 522 + 523 + enum ras_smu_feature_flags { 524 + RAS_SMU_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), 525 + }; 526 + 527 + struct ras_smu_drv { 528 + const struct ras_eeprom_smu_funcs *smu_eeprom_funcs; 529 + void (*ras_smu_feature_flags)(struct amdgpu_device *adev, uint64_t *flags); 530 + }; 531 + 506 532 struct amdgpu_ras { 507 533 void *ras_mgr; 508 534 /* ras infrastructure */ ··· 617 591 618 592 /* Protect poison injection */ 619 593 struct mutex poison_lock; 594 + 595 + /* Disable/Enable uniras switch */ 596 + bool uniras_enabled; 597 + const struct ras_smu_drv *ras_smu_drv; 620 598 }; 621 599 622 600 struct ras_fs_data { ··· 1039 1009 const char *fmt, ...); 1040 1010 1041 1011 bool amdgpu_ras_is_rma(struct amdgpu_device *adev); 1012 + 1013 + void amdgpu_ras_pre_reset(struct amdgpu_device *adev, 1014 + struct list_head *device_list); 1015 + void amdgpu_ras_post_reset(struct amdgpu_device *adev, 1016 + struct list_head *device_list); 1042 1017 #endif

+338 -28

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

··· 444 444 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 445 445 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 446 446 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 447 + u32 erase_res = 0; 447 448 u8 csum; 448 449 int res; 449 450 450 451 mutex_lock(&control->ras_tbl_mutex); 451 452 452 - hdr->header = RAS_TABLE_HDR_VAL; 453 - amdgpu_ras_set_eeprom_table_version(control); 453 + if (!amdgpu_ras_smu_eeprom_supported(adev)) { 454 + hdr->header = RAS_TABLE_HDR_VAL; 455 + amdgpu_ras_set_eeprom_table_version(control); 454 456 455 - if (hdr->version >= RAS_TABLE_VER_V2_1) { 456 - hdr->first_rec_offset = RAS_RECORD_START_V2_1; 457 - hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 458 - RAS_TABLE_V2_1_INFO_SIZE; 459 - rai->rma_status = GPU_HEALTH_USABLE; 460 - /** 461 - * GPU health represented as a percentage. 462 - * 0 means worst health, 100 means fully health. 463 - */ 464 - rai->health_percent = 100; 465 - /* ecc_page_threshold = 0 means disable bad page retirement */ 466 - rai->ecc_page_threshold = con->bad_page_cnt_threshold; 457 + if (hdr->version >= RAS_TABLE_VER_V2_1) { 458 + hdr->first_rec_offset = RAS_RECORD_START_V2_1; 459 + hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 460 + RAS_TABLE_V2_1_INFO_SIZE; 461 + rai->rma_status = GPU_HEALTH_USABLE; 462 + 463 + control->ras_record_offset = RAS_RECORD_START_V2_1; 464 + control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 465 + /** 466 + * GPU health represented as a percentage. 467 + * 0 means worst health, 100 means fully health. 468 + */ 469 + rai->health_percent = 100; 470 + /* ecc_page_threshold = 0 means disable bad page retirement */ 471 + rai->ecc_page_threshold = con->bad_page_cnt_threshold; 472 + } else { 473 + hdr->first_rec_offset = RAS_RECORD_START; 474 + hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 475 + 476 + control->ras_record_offset = RAS_RECORD_START; 477 + control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 478 + } 479 + 480 + csum = __calc_hdr_byte_sum(control); 481 + if (hdr->version >= RAS_TABLE_VER_V2_1) 482 + csum += __calc_ras_info_byte_sum(control); 483 + csum = -csum; 484 + hdr->checksum = csum; 485 + res = __write_table_header(control); 486 + if (!res && hdr->version > RAS_TABLE_VER_V1) 487 + res = __write_table_ras_info(control); 467 488 } else { 468 - hdr->first_rec_offset = RAS_RECORD_START; 469 - hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 489 + res = amdgpu_ras_smu_erase_ras_table(adev, &erase_res); 490 + if (res || erase_res) { 491 + dev_warn(adev->dev, "RAS EEPROM reset failed, res:%d result:%d", 492 + res, erase_res); 493 + if (!res) 494 + res = -EIO; 495 + } 470 496 } 471 - 472 - csum = __calc_hdr_byte_sum(control); 473 - if (hdr->version >= RAS_TABLE_VER_V2_1) 474 - csum += __calc_ras_info_byte_sum(control); 475 - csum = -csum; 476 - hdr->checksum = csum; 477 - res = __write_table_header(control); 478 - if (!res && hdr->version > RAS_TABLE_VER_V1) 479 - res = __write_table_ras_info(control); 480 497 481 498 control->ras_num_recs = 0; 482 499 control->ras_num_bad_pages = 0; ··· 787 770 "Saved bad pages %d reaches threshold value %d\n", 788 771 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 789 772 790 - if (adev->cper.enabled && amdgpu_cper_generate_bp_threshold_record(adev)) 773 + if (adev->cper.enabled && !amdgpu_uniras_enabled(adev) && 774 + amdgpu_cper_generate_bp_threshold_record(adev)) 791 775 dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); 792 776 793 777 if ((amdgpu_bad_page_threshold != -1) && ··· 871 853 return res; 872 854 } 873 855 856 + int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control) 857 + { 858 + struct amdgpu_device *adev = to_amdgpu_device(control); 859 + 860 + if (!amdgpu_ras_smu_eeprom_supported(adev)) 861 + return 0; 862 + 863 + control->ras_num_recs_old = control->ras_num_recs; 864 + return amdgpu_ras_smu_get_badpage_count(adev, 865 + &(control->ras_num_recs), 12); 866 + } 867 + 874 868 /** 875 869 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 876 870 * @control: pointer to control structure ··· 901 871 const u32 num) 902 872 { 903 873 struct amdgpu_device *adev = to_amdgpu_device(control); 874 + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 904 875 int res, i; 905 876 uint64_t nps = AMDGPU_NPS1_PARTITION_MODE; 906 877 907 - if (!__is_ras_eeprom_supported(adev)) 878 + if (!__is_ras_eeprom_supported(adev) || !con) 908 879 return 0; 880 + 881 + if (amdgpu_ras_smu_eeprom_supported(adev)) { 882 + control->ras_num_bad_pages = con->bad_page_num; 883 + return 0; 884 + } 909 885 910 886 if (num == 0) { 911 887 dev_err(adev->dev, "will not append 0 records\n"); ··· 988 952 return res; 989 953 } 990 954 955 + int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, 956 + struct eeprom_table_record *record, u32 rec_idx, 957 + const u32 num) 958 + { 959 + struct amdgpu_device *adev = to_amdgpu_device(control); 960 + uint64_t ts, end_idx; 961 + int i, ret; 962 + u64 mca, ipid; 963 + 964 + if (!amdgpu_ras_smu_eeprom_supported(adev)) 965 + return 0; 966 + 967 + if (!adev->umc.ras || !adev->umc.ras->mca_ipid_parse) 968 + return -EOPNOTSUPP; 969 + 970 + end_idx = rec_idx + num; 971 + for (i = rec_idx; i < end_idx; i++) { 972 + ret = amdgpu_ras_smu_get_badpage_mca_addr(adev, i, &mca); 973 + if (ret) 974 + return ret; 975 + 976 + ret = amdgpu_ras_smu_get_badpage_ipid(adev, i, &ipid); 977 + if (ret) 978 + return ret; 979 + 980 + ret = amdgpu_ras_smu_get_timestamp(adev, i, &ts); 981 + if (ret) 982 + return ret; 983 + 984 + record[i - rec_idx].address = mca; 985 + /* retired_page (pa) is unused now */ 986 + record[i - rec_idx].retired_page = 0x1ULL; 987 + record[i - rec_idx].ts = ts; 988 + record[i - rec_idx].err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; 989 + record[i - rec_idx].cu = 0; 990 + 991 + adev->umc.ras->mca_ipid_parse(adev, ipid, NULL, 992 + (uint32_t *)&(record[i - rec_idx].mem_channel), 993 + (uint32_t *)&(record[i - rec_idx].mcumc_id), NULL); 994 + } 995 + 996 + return 0; 997 + } 998 + 991 999 /** 992 1000 * amdgpu_ras_eeprom_read -- read EEPROM 993 1001 * @control: pointer to control structure ··· 1052 972 int i, res; 1053 973 u8 *buf, *pp; 1054 974 u32 g0, g1; 975 + 976 + if (amdgpu_ras_smu_eeprom_supported(adev)) 977 + return amdgpu_ras_eeprom_read_idx(control, record, 0, num); 1055 978 1056 979 if (!__is_ras_eeprom_supported(adev)) 1057 980 return 0; ··· 1226 1143 const size_t orig_size = size; 1227 1144 int res = -EFAULT; 1228 1145 size_t data_len; 1146 + 1147 + /* pmfw manages eeprom data by itself */ 1148 + if (amdgpu_ras_smu_eeprom_supported(adev)) 1149 + return 0; 1229 1150 1230 1151 mutex_lock(&control->ras_tbl_mutex); 1231 1152 ··· 1461 1374 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1462 1375 } 1463 1376 1377 + static int amdgpu_ras_smu_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1378 + { 1379 + struct amdgpu_device *adev = to_amdgpu_device(control); 1380 + struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1381 + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1382 + uint64_t local_time; 1383 + int res; 1384 + 1385 + ras->is_rma = false; 1386 + 1387 + if (!__is_ras_eeprom_supported(adev)) 1388 + return 0; 1389 + mutex_init(&control->ras_tbl_mutex); 1390 + 1391 + res = amdgpu_ras_smu_get_table_version(adev, &(hdr->version)); 1392 + if (res) 1393 + return res; 1394 + 1395 + res = amdgpu_ras_smu_get_badpage_count(adev, 1396 + &(control->ras_num_recs), 100); 1397 + if (res) 1398 + return res; 1399 + 1400 + local_time = (uint64_t)ktime_get_real_seconds(); 1401 + res = amdgpu_ras_smu_set_timestamp(adev, local_time); 1402 + if (res) 1403 + return res; 1404 + 1405 + control->ras_max_record_count = 4000; 1406 + 1407 + control->ras_num_mca_recs = 0; 1408 + control->ras_num_pa_recs = 0; 1409 + 1410 + return 0; 1411 + } 1412 + 1464 1413 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) 1465 1414 { 1466 1415 struct amdgpu_device *adev = to_amdgpu_device(control); ··· 1504 1381 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1505 1382 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1506 1383 int res; 1384 + 1385 + if (amdgpu_ras_smu_eeprom_supported(adev)) 1386 + return amdgpu_ras_smu_eeprom_init(control); 1507 1387 1508 1388 ras->is_rma = false; 1509 1389 ··· 1574 1448 return 0; 1575 1449 } 1576 1450 1451 + static int amdgpu_ras_smu_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1452 + { 1453 + struct amdgpu_device *adev = to_amdgpu_device(control); 1454 + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1455 + 1456 + if (!__is_ras_eeprom_supported(adev)) 1457 + return 0; 1458 + 1459 + control->ras_num_bad_pages = ras->bad_page_num; 1460 + 1461 + if ((ras->bad_page_cnt_threshold < control->ras_num_bad_pages) && 1462 + amdgpu_bad_page_threshold != 0) { 1463 + dev_warn(adev->dev, 1464 + "RAS records:%d exceed threshold:%d\n", 1465 + control->ras_num_bad_pages, ras->bad_page_cnt_threshold); 1466 + if ((amdgpu_bad_page_threshold == -1) || 1467 + (amdgpu_bad_page_threshold == -2)) { 1468 + dev_warn(adev->dev, 1469 + "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1470 + } else { 1471 + ras->is_rma = true; 1472 + dev_warn(adev->dev, 1473 + "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1474 + } 1475 + 1476 + return 0; 1477 + } 1478 + 1479 + dev_dbg(adev->dev, 1480 + "Found existing EEPROM table with %d records", 1481 + control->ras_num_bad_pages); 1482 + 1483 + /* Warn if we are at 90% of the threshold or above 1484 + */ 1485 + if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) 1486 + dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1487 + control->ras_num_bad_pages, 1488 + ras->bad_page_cnt_threshold); 1489 + return 0; 1490 + } 1491 + 1577 1492 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) 1578 1493 { 1579 1494 struct amdgpu_device *adev = to_amdgpu_device(control); 1580 1495 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1581 1496 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1582 1497 int res = 0; 1498 + 1499 + if (amdgpu_ras_smu_eeprom_supported(adev)) 1500 + return amdgpu_ras_smu_eeprom_check(control); 1583 1501 1584 1502 if (!__is_ras_eeprom_supported(adev)) 1585 1503 return 0; ··· 1715 1545 struct amdgpu_ras_eeprom_control *control; 1716 1546 int res; 1717 1547 1718 - if (!__is_ras_eeprom_supported(adev) || !ras) 1548 + if (!__is_ras_eeprom_supported(adev) || !ras || 1549 + amdgpu_ras_smu_eeprom_supported(adev)) 1719 1550 return; 1720 1551 control = &ras->eeprom_control; 1721 1552 if (!control->is_eeprom_valid) ··· 1736 1565 control->is_eeprom_valid = false; 1737 1566 } 1738 1567 return; 1568 + } 1569 + 1570 + static const struct ras_smu_drv *amdgpu_ras_get_smu_ras_drv(struct amdgpu_device *adev) 1571 + { 1572 + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1573 + 1574 + if (!ras) 1575 + return NULL; 1576 + 1577 + return ras->ras_smu_drv; 1578 + } 1579 + 1580 + static uint64_t amdgpu_ras_smu_get_feature_flags(struct amdgpu_device *adev) 1581 + { 1582 + const struct ras_smu_drv *ras_smu_drv = amdgpu_ras_get_smu_ras_drv(adev); 1583 + uint64_t flags = 0ULL; 1584 + 1585 + if (!ras_smu_drv) 1586 + goto out; 1587 + 1588 + if (ras_smu_drv->ras_smu_feature_flags) 1589 + ras_smu_drv->ras_smu_feature_flags(adev, &flags); 1590 + 1591 + out: 1592 + return flags; 1593 + } 1594 + 1595 + bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev) 1596 + { 1597 + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1598 + uint64_t flags = 0ULL; 1599 + 1600 + if (!__is_ras_eeprom_supported(adev) || !smu_ras_drv) 1601 + return false; 1602 + 1603 + if (!smu_ras_drv->smu_eeprom_funcs) 1604 + return false; 1605 + 1606 + flags = amdgpu_ras_smu_get_feature_flags(adev); 1607 + 1608 + return !!(flags & RAS_SMU_FEATURE_BIT__RAS_EEPROM); 1609 + } 1610 + 1611 + int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev, 1612 + uint32_t *table_version) 1613 + { 1614 + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1615 + 1616 + if (!amdgpu_ras_smu_eeprom_supported(adev)) 1617 + return -EOPNOTSUPP; 1618 + 1619 + if (smu_ras_drv->smu_eeprom_funcs->get_ras_table_version) 1620 + return smu_ras_drv->smu_eeprom_funcs->get_ras_table_version(adev, 1621 + table_version); 1622 + return -EOPNOTSUPP; 1623 + } 1624 + 1625 + int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev, 1626 + uint32_t *count, uint32_t timeout) 1627 + { 1628 + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1629 + 1630 + if (!amdgpu_ras_smu_eeprom_supported(adev)) 1631 + return -EOPNOTSUPP; 1632 + 1633 + if (smu_ras_drv->smu_eeprom_funcs->get_badpage_count) 1634 + return smu_ras_drv->smu_eeprom_funcs->get_badpage_count(adev, 1635 + count, timeout); 1636 + return -EOPNOTSUPP; 1637 + } 1638 + 1639 + int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev, 1640 + uint16_t index, uint64_t *mca_addr) 1641 + { 1642 + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1643 + 1644 + if (!amdgpu_ras_smu_eeprom_supported(adev)) 1645 + return -EOPNOTSUPP; 1646 + 1647 + if (smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr) 1648 + return smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr(adev, 1649 + index, mca_addr); 1650 + return -EOPNOTSUPP; 1651 + } 1652 + 1653 + int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev, 1654 + uint64_t timestamp) 1655 + { 1656 + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1657 + 1658 + if (!amdgpu_ras_smu_eeprom_supported(adev)) 1659 + return -EOPNOTSUPP; 1660 + 1661 + if (smu_ras_drv->smu_eeprom_funcs->set_timestamp) 1662 + return smu_ras_drv->smu_eeprom_funcs->set_timestamp(adev, 1663 + timestamp); 1664 + return -EOPNOTSUPP; 1665 + } 1666 + 1667 + int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev, 1668 + uint16_t index, uint64_t *timestamp) 1669 + { 1670 + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1671 + 1672 + if (!amdgpu_ras_smu_eeprom_supported(adev)) 1673 + return -EOPNOTSUPP; 1674 + 1675 + if (smu_ras_drv->smu_eeprom_funcs->get_timestamp) 1676 + return smu_ras_drv->smu_eeprom_funcs->get_timestamp(adev, 1677 + index, timestamp); 1678 + return -EOPNOTSUPP; 1679 + } 1680 + 1681 + int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev, 1682 + uint16_t index, uint64_t *ipid) 1683 + { 1684 + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1685 + 1686 + if (!amdgpu_ras_smu_eeprom_supported(adev)) 1687 + return -EOPNOTSUPP; 1688 + 1689 + if (smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid) 1690 + return smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid(adev, 1691 + index, ipid); 1692 + return -EOPNOTSUPP; 1693 + } 1694 + 1695 + int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, 1696 + uint32_t *result) 1697 + { 1698 + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); 1699 + 1700 + if (!amdgpu_ras_smu_eeprom_supported(adev)) 1701 + return -EOPNOTSUPP; 1702 + 1703 + if (smu_ras_drv->smu_eeprom_funcs->erase_ras_table) 1704 + return smu_ras_drv->smu_eeprom_funcs->erase_ras_table(adev, 1705 + result); 1706 + return -EOPNOTSUPP; 1739 1707 }

+30

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h

··· 82 82 /* Number of records in the table. 83 83 */ 84 84 u32 ras_num_recs; 85 + u32 ras_num_recs_old; 85 86 86 87 /* the bad page number is ras_num_recs or 87 88 * ras_num_recs * umc.retire_unit ··· 163 162 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control); 164 163 165 164 void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev); 165 + 166 + bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev); 167 + 168 + int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev, 169 + uint32_t *table_version); 170 + 171 + int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev, 172 + uint32_t *count, uint32_t timeout); 173 + 174 + int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev, 175 + uint16_t index, uint64_t *mca_addr); 176 + 177 + int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev, 178 + uint64_t timestamp); 179 + 180 + int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev, 181 + uint16_t index, uint64_t *timestamp); 182 + 183 + int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev, 184 + uint16_t index, uint64_t *ipid); 185 + 186 + int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, 187 + uint32_t *result); 188 + 189 + int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, 190 + struct eeprom_table_record *record, u32 rec_idx, 191 + const u32 num); 192 + 193 + int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control); 166 194 167 195 extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; 168 196 extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops;

+59 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

··· 33 33 34 34 #include <drm/amdgpu_drm.h> 35 35 #include "amdgpu.h" 36 + #include "amdgpu_ras_mgr.h" 36 37 #include "atom.h" 37 38 38 39 /* ··· 469 468 ktime_t deadline; 470 469 bool ret; 471 470 472 - if (unlikely(ring->adev->debug_disable_soft_recovery)) 473 - return false; 474 - 475 471 deadline = ktime_add_us(ktime_get(), 10000); 476 472 477 473 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence) ··· 496 498 */ 497 499 #if defined(CONFIG_DEBUG_FS) 498 500 501 + static ssize_t amdgpu_ras_cper_debugfs_read(struct file *f, char __user *buf, 502 + size_t size, loff_t *offset) 503 + { 504 + const uint8_t ring_header_size = 12; 505 + struct amdgpu_ring *ring = file_inode(f)->i_private; 506 + struct ras_cmd_cper_snapshot_req *snapshot_req __free(kfree) = 507 + kzalloc(sizeof(struct ras_cmd_cper_snapshot_req), GFP_KERNEL); 508 + struct ras_cmd_cper_snapshot_rsp *snapshot_rsp __free(kfree) = 509 + kzalloc(sizeof(struct ras_cmd_cper_snapshot_rsp), GFP_KERNEL); 510 + struct ras_cmd_cper_record_req *record_req __free(kfree) = 511 + kzalloc(sizeof(struct ras_cmd_cper_record_req), GFP_KERNEL); 512 + struct ras_cmd_cper_record_rsp *record_rsp __free(kfree) = 513 + kzalloc(sizeof(struct ras_cmd_cper_record_rsp), GFP_KERNEL); 514 + uint8_t *ring_header __free(kfree) = 515 + kzalloc(ring_header_size, GFP_KERNEL); 516 + uint32_t total_cper_num; 517 + uint64_t start_cper_id; 518 + int r; 519 + 520 + if (!snapshot_req || !snapshot_rsp || !record_req || !record_rsp || 521 + !ring_header) 522 + return -ENOMEM; 523 + 524 + if (!(*offset)) { 525 + if (copy_to_user(buf, ring_header, ring_header_size)) 526 + return -EFAULT; 527 + buf += ring_header_size; 528 + } 529 + 530 + r = amdgpu_ras_mgr_handle_ras_cmd(ring->adev, 531 + RAS_CMD__GET_CPER_SNAPSHOT, 532 + snapshot_req, sizeof(struct ras_cmd_cper_snapshot_req), 533 + snapshot_rsp, sizeof(struct ras_cmd_cper_snapshot_rsp)); 534 + if (r || !snapshot_rsp->total_cper_num) 535 + return r; 536 + 537 + start_cper_id = snapshot_rsp->start_cper_id; 538 + total_cper_num = snapshot_rsp->total_cper_num; 539 + 540 + record_req->buf_ptr = (uint64_t)(uintptr_t)buf; 541 + record_req->buf_size = size; 542 + record_req->cper_start_id = start_cper_id + *offset; 543 + record_req->cper_num = total_cper_num; 544 + r = amdgpu_ras_mgr_handle_ras_cmd(ring->adev, RAS_CMD__GET_CPER_RECORD, 545 + record_req, sizeof(struct ras_cmd_cper_record_req), 546 + record_rsp, sizeof(struct ras_cmd_cper_record_rsp)); 547 + if (r) 548 + return r; 549 + 550 + r = *offset ? record_rsp->real_data_size : record_rsp->real_data_size + ring_header_size; 551 + (*offset) += record_rsp->real_cper_num; 552 + 553 + return r; 554 + } 555 + 499 556 /* Layout of file is 12 bytes consisting of 500 557 * - rptr 501 558 * - wptr ··· 566 513 uint64_t p; 567 514 loff_t i; 568 515 int r; 516 + 517 + if (ring->funcs->type == AMDGPU_RING_TYPE_CPER && amdgpu_uniras_enabled(ring->adev)) 518 + return amdgpu_ras_cper_debugfs_read(f, buf, size, pos); 569 519 570 520 if (*pos & 3 || size & 3) 571 521 return -EINVAL;

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

··· 83 83 AMDGPU_RING_TYPE_MES, 84 84 AMDGPU_RING_TYPE_UMSCH_MM, 85 85 AMDGPU_RING_TYPE_CPER, 86 + AMDGPU_RING_TYPE_MAX, 86 87 }; 87 88 88 89 enum amdgpu_ib_pool_type {

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h

··· 113 113 uint32_t (*get_die_id_from_pa)(struct amdgpu_device *adev, 114 114 uint64_t mca_addr, uint64_t retired_page); 115 115 void (*get_retire_flip_bits)(struct amdgpu_device *adev); 116 + void (*mca_ipid_parse)(struct amdgpu_device *adev, uint64_t ipid, 117 + uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid); 116 118 }; 117 119 118 120 struct amdgpu_umc_funcs {

+204 -12

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c

··· 25 25 #include <drm/drm_auth.h> 26 26 #include <drm/drm_exec.h> 27 27 #include <linux/pm_runtime.h> 28 + #include <drm/drm_drv.h> 28 29 29 30 #include "amdgpu.h" 31 + #include "amdgpu_reset.h" 30 32 #include "amdgpu_vm.h" 31 33 #include "amdgpu_userq.h" 32 34 #include "amdgpu_hmm.h" ··· 46 44 } 47 45 48 46 return userq_ip_mask; 47 + } 48 + 49 + static bool amdgpu_userq_is_reset_type_supported(struct amdgpu_device *adev, 50 + enum amdgpu_ring_type ring_type, int reset_type) 51 + { 52 + 53 + if (ring_type < 0 || ring_type >= AMDGPU_RING_TYPE_MAX) 54 + return false; 55 + 56 + switch (ring_type) { 57 + case AMDGPU_RING_TYPE_GFX: 58 + if (adev->gfx.gfx_supported_reset & reset_type) 59 + return true; 60 + break; 61 + case AMDGPU_RING_TYPE_COMPUTE: 62 + if (adev->gfx.compute_supported_reset & reset_type) 63 + return true; 64 + break; 65 + case AMDGPU_RING_TYPE_SDMA: 66 + if (adev->sdma.supported_reset & reset_type) 67 + return true; 68 + break; 69 + case AMDGPU_RING_TYPE_VCN_DEC: 70 + case AMDGPU_RING_TYPE_VCN_ENC: 71 + if (adev->vcn.supported_reset & reset_type) 72 + return true; 73 + break; 74 + case AMDGPU_RING_TYPE_VCN_JPEG: 75 + if (adev->jpeg.supported_reset & reset_type) 76 + return true; 77 + break; 78 + default: 79 + break; 80 + } 81 + return false; 82 + } 83 + 84 + static void amdgpu_userq_gpu_reset(struct amdgpu_device *adev) 85 + { 86 + if (amdgpu_device_should_recover_gpu(adev)) { 87 + amdgpu_reset_domain_schedule(adev->reset_domain, 88 + &adev->userq_reset_work); 89 + /* Wait for the reset job to complete */ 90 + flush_work(&adev->userq_reset_work); 91 + } 92 + } 93 + 94 + static int 95 + amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) 96 + { 97 + struct amdgpu_device *adev = uq_mgr->adev; 98 + const int queue_types[] = { 99 + AMDGPU_RING_TYPE_COMPUTE, 100 + AMDGPU_RING_TYPE_GFX, 101 + AMDGPU_RING_TYPE_SDMA 102 + }; 103 + const int num_queue_types = ARRAY_SIZE(queue_types); 104 + bool gpu_reset = false; 105 + int r = 0; 106 + int i; 107 + 108 + /* Warning if current process mutex is not held */ 109 + WARN_ON(!mutex_is_locked(&uq_mgr->userq_mutex)); 110 + 111 + if (unlikely(adev->debug_disable_gpu_ring_reset)) { 112 + dev_err(adev->dev, "userq reset disabled by debug mask\n"); 113 + return 0; 114 + } 115 + 116 + /* 117 + * If GPU recovery feature is disabled system-wide, 118 + * skip all reset detection logic 119 + */ 120 + if (!amdgpu_gpu_recovery) 121 + return 0; 122 + 123 + /* 124 + * Iterate through all queue types to detect and reset problematic queues 125 + * Process each queue type in the defined order 126 + */ 127 + for (i = 0; i < num_queue_types; i++) { 128 + int ring_type = queue_types[i]; 129 + const struct amdgpu_userq_funcs *funcs = adev->userq_funcs[ring_type]; 130 + 131 + if (!amdgpu_userq_is_reset_type_supported(adev, ring_type, AMDGPU_RESET_TYPE_PER_QUEUE)) 132 + continue; 133 + 134 + if (atomic_read(&uq_mgr->userq_count[ring_type]) > 0 && 135 + funcs && funcs->detect_and_reset) { 136 + r = funcs->detect_and_reset(adev, ring_type); 137 + if (r) { 138 + gpu_reset = true; 139 + break; 140 + } 141 + } 142 + } 143 + 144 + if (gpu_reset) 145 + amdgpu_userq_gpu_reset(adev); 146 + 147 + return r; 49 148 } 50 149 51 150 static int amdgpu_userq_buffer_va_list_add(struct amdgpu_usermode_queue *queue, ··· 279 176 struct amdgpu_device *adev = uq_mgr->adev; 280 177 const struct amdgpu_userq_funcs *userq_funcs = 281 178 adev->userq_funcs[queue->queue_type]; 179 + bool found_hung_queue = false; 282 180 int r = 0; 283 181 284 182 if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { 285 183 r = userq_funcs->preempt(uq_mgr, queue); 286 184 if (r) { 287 185 queue->state = AMDGPU_USERQ_STATE_HUNG; 186 + found_hung_queue = true; 288 187 } else { 289 188 queue->state = AMDGPU_USERQ_STATE_PREEMPTED; 290 189 } 291 190 } 191 + 192 + if (found_hung_queue) 193 + amdgpu_userq_detect_and_reset_queues(uq_mgr); 292 194 293 195 return r; 294 196 } ··· 326 218 struct amdgpu_device *adev = uq_mgr->adev; 327 219 const struct amdgpu_userq_funcs *userq_funcs = 328 220 adev->userq_funcs[queue->queue_type]; 221 + bool found_hung_queue = false; 329 222 int r = 0; 330 223 331 224 if ((queue->state == AMDGPU_USERQ_STATE_MAPPED) || 332 225 (queue->state == AMDGPU_USERQ_STATE_PREEMPTED)) { 333 226 r = userq_funcs->unmap(uq_mgr, queue); 334 - if (r) 227 + if (r) { 335 228 queue->state = AMDGPU_USERQ_STATE_HUNG; 336 - else 229 + found_hung_queue = true; 230 + } else { 337 231 queue->state = AMDGPU_USERQ_STATE_UNMAPPED; 232 + } 338 233 } 234 + 235 + if (found_hung_queue) 236 + amdgpu_userq_detect_and_reset_queues(uq_mgr); 237 + 339 238 return r; 340 239 } 341 240 ··· 359 244 r = userq_funcs->map(uq_mgr, queue); 360 245 if (r) { 361 246 queue->state = AMDGPU_USERQ_STATE_HUNG; 247 + amdgpu_userq_detect_and_reset_queues(uq_mgr); 362 248 } else { 363 249 queue->state = AMDGPU_USERQ_STATE_MAPPED; 364 250 } 365 251 } 252 + 366 253 return r; 367 254 } 368 255 ··· 592 475 amdgpu_bo_unreserve(queue->db_obj.obj); 593 476 } 594 477 amdgpu_bo_unref(&queue->db_obj.obj); 595 - 478 + atomic_dec(&uq_mgr->userq_count[queue->queue_type]); 596 479 #if defined(CONFIG_DEBUG_FS) 597 480 debugfs_remove_recursive(queue->debugfs_queue); 598 481 #endif 482 + amdgpu_userq_detect_and_reset_queues(uq_mgr); 599 483 r = amdgpu_userq_unmap_helper(uq_mgr, queue); 600 484 /*TODO: It requires a reset for userq hw unmap error*/ 601 485 if (unlikely(r != AMDGPU_USERQ_STATE_UNMAPPED)) { ··· 819 701 kfree(queue_name); 820 702 821 703 args->out.queue_id = qid; 704 + atomic_inc(&uq_mgr->userq_count[queue->queue_type]); 822 705 823 706 unlock: 824 707 mutex_unlock(&uq_mgr->userq_mutex); ··· 1062 943 /* Validate User Ptr BOs */ 1063 944 list_for_each_entry(bo_va, &vm->done, base.vm_status) { 1064 945 bo = bo_va->base.bo; 946 + if (!bo) 947 + continue; 1065 948 1066 949 if (!amdgpu_ttm_tt_is_userptr(bo->tbo.ttm)) 1067 950 continue; ··· 1166 1045 unsigned long queue_id; 1167 1046 int ret = 0, r; 1168 1047 1048 + amdgpu_userq_detect_and_reset_queues(uq_mgr); 1169 1049 /* Try to unmap all the queues in this process ctx */ 1170 1050 xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { 1171 1051 r = amdgpu_userq_preempt_helper(uq_mgr, queue); ··· 1177 1055 if (ret) 1178 1056 drm_file_err(uq_mgr->file, "Couldn't unmap all the queues\n"); 1179 1057 return ret; 1058 + } 1059 + 1060 + void amdgpu_userq_reset_work(struct work_struct *work) 1061 + { 1062 + struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 1063 + userq_reset_work); 1064 + struct amdgpu_reset_context reset_context; 1065 + 1066 + memset(&reset_context, 0, sizeof(reset_context)); 1067 + 1068 + reset_context.method = AMD_RESET_METHOD_NONE; 1069 + reset_context.reset_req_dev = adev; 1070 + reset_context.src = AMDGPU_RESET_SRC_USERQ; 1071 + set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 1072 + /*set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags);*/ 1073 + 1074 + amdgpu_device_gpu_recover(adev, NULL, &reset_context); 1180 1075 } 1181 1076 1182 1077 static int ··· 1223 1084 amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, 1224 1085 struct amdgpu_eviction_fence *ev_fence) 1225 1086 { 1226 - int ret; 1227 1087 struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); 1228 1088 struct amdgpu_eviction_fence_mgr *evf_mgr = &fpriv->evf_mgr; 1089 + struct amdgpu_device *adev = uq_mgr->adev; 1090 + int ret; 1229 1091 1230 1092 /* Wait for any pending userqueue fence work to finish */ 1231 1093 ret = amdgpu_userq_wait_for_signal(uq_mgr); 1232 - if (ret) { 1233 - drm_file_err(uq_mgr->file, "Not evicting userqueue, timeout waiting for work\n"); 1234 - return; 1235 - } 1094 + if (ret) 1095 + dev_err(adev->dev, "Not evicting userqueue, timeout waiting for work\n"); 1236 1096 1237 1097 ret = amdgpu_userq_evict_all(uq_mgr); 1238 - if (ret) { 1239 - drm_file_err(uq_mgr->file, "Failed to evict userqueue\n"); 1240 - return; 1241 - } 1098 + if (ret) 1099 + dev_err(adev->dev, "Failed to evict userqueue\n"); 1242 1100 1243 1101 /* Signal current eviction fence */ 1244 1102 amdgpu_eviction_fence_signal(evf_mgr, ev_fence); ··· 1269 1133 cancel_delayed_work_sync(&userq_mgr->resume_work); 1270 1134 1271 1135 mutex_lock(&userq_mgr->userq_mutex); 1136 + amdgpu_userq_detect_and_reset_queues(userq_mgr); 1272 1137 xa_for_each(&userq_mgr->userq_mgr_xa, queue_id, queue) { 1273 1138 amdgpu_userq_wait_for_last_fence(userq_mgr, queue); 1274 1139 amdgpu_userq_unmap_helper(userq_mgr, queue); ··· 1296 1159 uqm = queue->userq_mgr; 1297 1160 cancel_delayed_work_sync(&uqm->resume_work); 1298 1161 guard(mutex)(&uqm->userq_mutex); 1162 + amdgpu_userq_detect_and_reset_queues(uqm); 1299 1163 if (adev->in_s0ix) 1300 1164 r = amdgpu_userq_preempt_helper(uqm, queue); 1301 1165 else ··· 1355 1217 if (((queue->queue_type == AMDGPU_HW_IP_GFX) || 1356 1218 (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && 1357 1219 (queue->xcp_id == idx)) { 1220 + amdgpu_userq_detect_and_reset_queues(uqm); 1358 1221 r = amdgpu_userq_preempt_helper(uqm, queue); 1359 1222 if (r) 1360 1223 ret = r; ··· 1427 1288 } 1428 1289 1429 1290 return 0; 1291 + } 1292 + 1293 + void amdgpu_userq_pre_reset(struct amdgpu_device *adev) 1294 + { 1295 + const struct amdgpu_userq_funcs *userq_funcs; 1296 + struct amdgpu_usermode_queue *queue; 1297 + struct amdgpu_userq_mgr *uqm; 1298 + unsigned long queue_id; 1299 + 1300 + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { 1301 + uqm = queue->userq_mgr; 1302 + cancel_delayed_work_sync(&uqm->resume_work); 1303 + if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { 1304 + amdgpu_userq_wait_for_last_fence(uqm, queue); 1305 + userq_funcs = adev->userq_funcs[queue->queue_type]; 1306 + userq_funcs->unmap(uqm, queue); 1307 + /* just mark all queues as hung at this point. 1308 + * if unmap succeeds, we could map again 1309 + * in amdgpu_userq_post_reset() if vram is not lost 1310 + */ 1311 + queue->state = AMDGPU_USERQ_STATE_HUNG; 1312 + amdgpu_userq_fence_driver_force_completion(queue); 1313 + } 1314 + } 1315 + } 1316 + 1317 + int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost) 1318 + { 1319 + /* if any queue state is AMDGPU_USERQ_STATE_UNMAPPED 1320 + * at this point, we should be able to map it again 1321 + * and continue if vram is not lost. 1322 + */ 1323 + struct amdgpu_userq_mgr *uqm; 1324 + struct amdgpu_usermode_queue *queue; 1325 + const struct amdgpu_userq_funcs *userq_funcs; 1326 + unsigned long queue_id; 1327 + int r = 0; 1328 + 1329 + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { 1330 + uqm = queue->userq_mgr; 1331 + if (queue->state == AMDGPU_USERQ_STATE_HUNG && !vram_lost) { 1332 + userq_funcs = adev->userq_funcs[queue->queue_type]; 1333 + /* Re-map queue */ 1334 + r = userq_funcs->map(uqm, queue); 1335 + if (r) { 1336 + dev_err(adev->dev, "Failed to remap queue %ld\n", queue_id); 1337 + continue; 1338 + } 1339 + queue->state = AMDGPU_USERQ_STATE_MAPPED; 1340 + } 1341 + } 1342 + 1343 + return r; 1430 1344 }

+5

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h

··· 106 106 struct amdgpu_device *adev; 107 107 struct delayed_work resume_work; 108 108 struct drm_file *file; 109 + atomic_t userq_count[AMDGPU_RING_TYPE_MAX]; 109 110 }; 110 111 111 112 struct amdgpu_db_info { ··· 149 148 u32 idx); 150 149 int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, 151 150 u32 idx); 151 + void amdgpu_userq_reset_work(struct work_struct *work); 152 + void amdgpu_userq_pre_reset(struct amdgpu_device *adev); 153 + int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost); 154 + 152 155 int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue, 153 156 u64 addr, u64 expected_size); 154 157 int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev,

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c

··· 386 386 amdgpu_bo_unreserve(queue->vm->root.bo); 387 387 r = amdgpu_bo_reserve(bo, true); 388 388 if (r) { 389 + amdgpu_bo_unref(&bo); 389 390 DRM_ERROR("Failed to reserve userqueue wptr bo"); 390 391 return r; 391 392 }

+8 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

··· 484 484 spin_lock(&vm->status_lock); 485 485 while (!list_is_head(prev->next, &vm->done)) { 486 486 bo_va = list_entry(prev->next, typeof(*bo_va), base.vm_status); 487 - spin_unlock(&vm->status_lock); 488 487 489 488 bo = bo_va->base.bo; 490 489 if (bo) { 490 + amdgpu_bo_ref(bo); 491 + spin_unlock(&vm->status_lock); 492 + 491 493 ret = drm_exec_prepare_obj(exec, &bo->tbo.base, 1); 494 + amdgpu_bo_unref(&bo); 492 495 if (unlikely(ret)) 493 496 return ret; 497 + 498 + spin_lock(&vm->status_lock); 494 499 } 495 - spin_lock(&vm->status_lock); 496 500 prev = prev->next; 497 501 } 498 502 spin_unlock(&vm->status_lock); ··· 849 845 if (r) 850 846 return r; 851 847 fence = &job->hw_vm_fence->base; 848 + /* get a ref for the job */ 849 + dma_fence_get(fence); 852 850 } 853 851 854 852 if (vm_flush_needed) {

+2 -1

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c

··· 407 407 return -EINVAL; 408 408 } 409 409 410 - if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 410 + if (adev->kfd.init_complete && !amdgpu_in_reset(adev) && 411 + !adev->in_suspend) 411 412 flags |= AMDGPU_XCP_OPS_KFD; 412 413 413 414 if (flags & AMDGPU_XCP_OPS_KFD) {

+2 -1

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

··· 4956 4956 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4957 4957 adev->gfx.compute_supported_reset = 4958 4958 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4959 - if (!amdgpu_sriov_vf(adev)) { 4959 + if (!amdgpu_sriov_vf(adev) && 4960 + !adev->debug_disable_gpu_ring_reset) { 4960 4961 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 4961 4962 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 4962 4963 }

+4 -2

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

··· 1821 1821 case IP_VERSION(11, 0, 3): 1822 1822 if ((adev->gfx.me_fw_version >= 2280) && 1823 1823 (adev->gfx.mec_fw_version >= 2410) && 1824 - !amdgpu_sriov_vf(adev)) { 1824 + !amdgpu_sriov_vf(adev) && 1825 + !adev->debug_disable_gpu_ring_reset) { 1825 1826 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1826 1827 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1827 1828 } 1828 1829 break; 1829 1830 default: 1830 - if (!amdgpu_sriov_vf(adev)) { 1831 + if (!amdgpu_sriov_vf(adev) && 1832 + !adev->debug_disable_gpu_ring_reset) { 1831 1833 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1832 1834 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1833 1835 }

+2 -1

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

··· 1548 1548 case IP_VERSION(12, 0, 1): 1549 1549 if ((adev->gfx.me_fw_version >= 2660) && 1550 1550 (adev->gfx.mec_fw_version >= 2920) && 1551 - !amdgpu_sriov_vf(adev)) { 1551 + !amdgpu_sriov_vf(adev) && 1552 + !adev->debug_disable_gpu_ring_reset) { 1552 1553 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1553 1554 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1554 1555 }

+5

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

··· 3102 3102 return r; 3103 3103 } 3104 3104 3105 + adev->gfx.gfx_supported_reset = 3106 + amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 3107 + adev->gfx.compute_supported_reset = 3108 + amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 3109 + 3105 3110 return r; 3106 3111 } 3107 3112

+5

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

··· 4399 4399 4400 4400 gfx_v7_0_gpu_early_init(adev); 4401 4401 4402 + adev->gfx.gfx_supported_reset = 4403 + amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4404 + adev->gfx.compute_supported_reset = 4405 + amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4406 + 4402 4407 return r; 4403 4408 } 4404 4409

+5

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

··· 2023 2023 if (r) 2024 2024 return r; 2025 2025 2026 + adev->gfx.gfx_supported_reset = 2027 + amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 2028 + adev->gfx.compute_supported_reset = 2029 + amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 2030 + 2026 2031 return 0; 2027 2032 } 2028 2033

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

··· 2409 2409 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 2410 2410 adev->gfx.compute_supported_reset = 2411 2411 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 2412 - if (!amdgpu_sriov_vf(adev)) 2412 + if (!amdgpu_sriov_vf(adev) && !adev->debug_disable_gpu_ring_reset) 2413 2413 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2414 2414 2415 2415 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0);

+7 -3

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

··· 1149 1149 case IP_VERSION(9, 4, 3): 1150 1150 case IP_VERSION(9, 4, 4): 1151 1151 if ((adev->gfx.mec_fw_version >= 155) && 1152 - !amdgpu_sriov_vf(adev)) { 1152 + !amdgpu_sriov_vf(adev) && 1153 + !adev->debug_disable_gpu_ring_reset) { 1153 1154 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1154 1155 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1155 1156 } 1156 1157 break; 1157 1158 case IP_VERSION(9, 5, 0): 1158 1159 if ((adev->gfx.mec_fw_version >= 21) && 1159 - !amdgpu_sriov_vf(adev)) { 1160 + !amdgpu_sriov_vf(adev) && 1161 + !adev->debug_disable_gpu_ring_reset) { 1160 1162 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1161 1163 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1162 1164 } ··· 2291 2289 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2292 2290 2293 2291 } else { 2294 - if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2292 + if (adev->in_suspend) 2293 + amdgpu_xcp_restore_partition_mode(adev->xcp_mgr); 2294 + else if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2295 2295 AMDGPU_XCP_FL_NONE) == 2296 2296 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2297 2297 r = amdgpu_xcp_switch_partition_mode(

+25 -1

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

··· 142 142 return err; 143 143 } 144 144 145 + static int psp_v11_wait_for_tos_unload(struct psp_context *psp) 146 + { 147 + struct amdgpu_device *adev = psp->adev; 148 + uint32_t sol_reg1, sol_reg2; 149 + int retry_loop; 150 + 151 + /* Wait for the TOS to be unloaded */ 152 + for (retry_loop = 0; retry_loop < 20; retry_loop++) { 153 + sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 154 + usleep_range(1000, 2000); 155 + sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 156 + if (sol_reg1 == sol_reg2) 157 + return 0; 158 + } 159 + dev_err(adev->dev, "TOS unload failed, C2PMSG_33: %x C2PMSG_81: %x", 160 + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33), 161 + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)); 162 + 163 + return -ETIME; 164 + } 165 + 145 166 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 146 167 { 147 168 struct amdgpu_device *adev = psp->adev; 148 - 149 169 int ret; 150 170 int retry_loop; 171 + 172 + /* For a reset done at the end of S3, only wait for TOS to be unloaded */ 173 + if (adev->in_s3 && !(adev->flags & AMD_IS_APU) && amdgpu_in_reset(adev)) 174 + return psp_v11_wait_for_tos_unload(psp); 151 175 152 176 for (retry_loop = 0; retry_loop < 20; retry_loop++) { 153 177 /* Wait for bootloader to signify that is

+6 -2

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

··· 2361 2361 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2362 2362 case IP_VERSION(9, 4, 3): 2363 2363 case IP_VERSION(9, 4, 4): 2364 - if ((adev->gfx.mec_fw_version >= 0xb0) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2364 + if ((adev->gfx.mec_fw_version >= 0xb0) && 2365 + amdgpu_dpm_reset_sdma_is_supported(adev) && 2366 + !adev->debug_disable_gpu_ring_reset) 2365 2367 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2366 2368 break; 2367 2369 case IP_VERSION(9, 5, 0): 2368 - if ((adev->gfx.mec_fw_version >= 0xf) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2370 + if ((adev->gfx.mec_fw_version >= 0xf) && 2371 + amdgpu_dpm_reset_sdma_is_supported(adev) && 2372 + !adev->debug_disable_gpu_ring_reset) 2369 2373 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2370 2374 break; 2371 2375 default:

+2 -1

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

··· 1429 1429 case IP_VERSION(5, 0, 2): 1430 1430 case IP_VERSION(5, 0, 5): 1431 1431 if ((adev->sdma.instance[0].fw_version >= 35) && 1432 - !amdgpu_sriov_vf(adev)) 1432 + !amdgpu_sriov_vf(adev) && 1433 + !adev->debug_disable_gpu_ring_reset) 1433 1434 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1434 1435 break; 1435 1436 default:

+5 -3

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

··· 342 342 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 343 343 344 344 if (ring->me > 1) { 345 - amdgpu_asic_flush_hdp(adev, ring); 345 + amdgpu_hdp_flush(adev, ring); 346 346 } else { 347 347 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 348 348 ··· 1348 1348 case IP_VERSION(5, 2, 3): 1349 1349 case IP_VERSION(5, 2, 4): 1350 1350 if ((adev->sdma.instance[0].fw_version >= 76) && 1351 - !amdgpu_sriov_vf(adev)) 1351 + !amdgpu_sriov_vf(adev) && 1352 + !adev->debug_disable_gpu_ring_reset) 1352 1353 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1353 1354 break; 1354 1355 case IP_VERSION(5, 2, 5): 1355 1356 if ((adev->sdma.instance[0].fw_version >= 34) && 1356 - !amdgpu_sriov_vf(adev)) 1357 + !amdgpu_sriov_vf(adev) && 1358 + !adev->debug_disable_gpu_ring_reset) 1357 1359 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1358 1360 break; 1359 1361 default:

+2 -1

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

··· 1356 1356 case IP_VERSION(6, 0, 2): 1357 1357 case IP_VERSION(6, 0, 3): 1358 1358 if ((adev->sdma.instance[0].fw_version >= 21) && 1359 - !amdgpu_sriov_vf(adev)) 1359 + !amdgpu_sriov_vf(adev) && 1360 + !adev->debug_disable_gpu_ring_reset) 1360 1361 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1361 1362 break; 1362 1363 default:

+2 -1

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

··· 1337 1337 1338 1338 adev->sdma.supported_reset = 1339 1339 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1340 - if (!amdgpu_sriov_vf(adev)) 1340 + if (!amdgpu_sriov_vf(adev) && 1341 + !adev->debug_disable_gpu_ring_reset) 1341 1342 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1342 1343 1343 1344 r = amdgpu_sdma_sysfs_reset_mask_init(adev);

+14

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

··· 711 711 return die; 712 712 } 713 713 714 + static void umc_v12_0_mca_ipid_parse(struct amdgpu_device *adev, uint64_t ipid, 715 + uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid) 716 + { 717 + if (did) 718 + *did = MCA_IPID_2_DIE_ID(ipid); 719 + if (ch) 720 + *ch = MCA_IPID_2_UMC_CH(ipid); 721 + if (umc_inst) 722 + *umc_inst = MCA_IPID_2_UMC_INST(ipid); 723 + if (sid) 724 + *sid = MCA_IPID_2_SOCKET_ID(ipid); 725 + } 726 + 714 727 struct amdgpu_umc_ras umc_v12_0_ras = { 715 728 .ras_block = { 716 729 .hw_ops = &umc_v12_0_ras_hw_ops, ··· 737 724 .convert_ras_err_addr = umc_v12_0_convert_error_address, 738 725 .get_die_id_from_pa = umc_v12_0_get_die_id, 739 726 .get_retire_flip_bits = umc_v12_0_get_retire_flip_bits, 727 + .mca_ipid_parse = umc_v12_0_mca_ipid_parse, 740 728 }; 741 729

+8 -4

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

··· 2826 2826 2827 2827 static int runtime_disable(struct kfd_process *p) 2828 2828 { 2829 - int i = 0, ret; 2829 + int i = 0, ret = 0; 2830 2830 bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED; 2831 2831 2832 2832 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED; ··· 2863 2863 /* disable ttmp setup */ 2864 2864 for (i = 0; i < p->n_pdds; i++) { 2865 2865 struct kfd_process_device *pdd = p->pdds[i]; 2866 + int last_err = 0; 2866 2867 2867 2868 if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { 2868 2869 pdd->spi_dbg_override = ··· 2873 2872 pdd->dev->vm_info.last_vmid_kfd); 2874 2873 2875 2874 if (!pdd->dev->kfd->shared_resources.enable_mes) 2876 - debug_refresh_runlist(pdd->dev->dqm); 2875 + last_err = debug_refresh_runlist(pdd->dev->dqm); 2877 2876 else 2878 - kfd_dbg_set_mes_debug_mode(pdd, 2877 + last_err = kfd_dbg_set_mes_debug_mode(pdd, 2879 2878 !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2879 + 2880 + if (last_err) 2881 + ret = last_err; 2880 2882 } 2881 2883 } 2882 2884 2883 - return 0; 2885 + return ret; 2884 2886 } 2885 2887 2886 2888 static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data)

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

··· 2094 2094 2095 2095 while (*fence_addr != fence_value) { 2096 2096 /* Fatal err detected, this response won't come */ 2097 - if (amdgpu_amdkfd_is_fed(dqm->dev->adev)) 2097 + if (amdgpu_amdkfd_is_fed(dqm->dev->adev) || 2098 + amdgpu_in_reset(dqm->dev->adev)) 2098 2099 return -EIO; 2099 2100 2100 2101 if (time_after(jiffies, end_jiffies)) {

-11

drivers/gpu/drm/amd/amdkfd/kfd_events.c

··· 748 748 uint64_t *slots = page_slots(p->signal_page); 749 749 uint32_t id; 750 750 751 - /* 752 - * If id is valid but slot is not signaled, GPU may signal the same event twice 753 - * before driver have chance to process the first interrupt, then signal slot is 754 - * auto-reset after set_event wakeup the user space, just drop the second event as 755 - * the application only need wakeup once. 756 - */ 757 - if ((valid_id_bits > 31 || (1U << valid_id_bits) >= KFD_SIGNAL_EVENT_LIMIT) && 758 - partial_id < KFD_SIGNAL_EVENT_LIMIT && slots[partial_id] == UNSIGNALED_EVENT_SLOT) 759 - goto out_unlock; 760 - 761 751 if (valid_id_bits) 762 752 pr_debug_ratelimited("Partial ID invalid: %u (%u valid bits)\n", 763 753 partial_id, valid_id_bits); ··· 776 786 } 777 787 } 778 788 779 - out_unlock: 780 789 rcu_read_unlock(); 781 790 kfd_unref_process(p); 782 791 }

+3 -7

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

··· 1744 1744 else 1745 1745 r = -ENOMEM; 1746 1746 WRITE_ONCE(p->svms.faulting_task, NULL); 1747 - if (r) { 1748 - amdgpu_hmm_range_free(range); 1749 - range = NULL; 1747 + if (r) 1750 1748 pr_debug("failed %d to get svm range pages\n", r); 1751 - } 1752 1749 } else { 1753 1750 r = -EFAULT; 1754 1751 } ··· 1768 1771 pr_debug("hmm update the range, need validate again\n"); 1769 1772 r = -EAGAIN; 1770 1773 } 1771 - /* Free the hmm range */ 1772 - if (range) 1773 - amdgpu_hmm_range_free(range); 1774 1774 1775 + /* Free the hmm range */ 1776 + amdgpu_hmm_range_free(range); 1775 1777 1776 1778 if (!r && !list_empty(&prange->child_list)) { 1777 1779 pr_debug("range split by unmap in parallel, validate again\n");

+12 -4

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 3624 3624 /* Do mst topology probing after resuming cached state*/ 3625 3625 drm_connector_list_iter_begin(ddev, &iter); 3626 3626 drm_for_each_connector_iter(connector, &iter) { 3627 + bool init = false; 3627 3628 3628 3629 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3629 3630 continue; ··· 3634 3633 aconnector->mst_root) 3635 3634 continue; 3636 3635 3637 - drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 3636 + scoped_guard(mutex, &aconnector->mst_mgr.lock) { 3637 + init = !aconnector->mst_mgr.mst_primary; 3638 + } 3639 + if (init) 3640 + dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 3641 + aconnector->dc_link, false); 3642 + else 3643 + drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 3638 3644 } 3639 3645 drm_connector_list_iter_end(&iter); 3640 3646 ··· 7397 7389 default: 7398 7390 dm_new_state->abm_sysfs_forbidden = true; 7399 7391 dm_new_state->abm_level = val; 7400 - }; 7392 + } 7401 7393 ret = 0; 7402 7394 } 7403 7395 ··· 8224 8216 "mode %dx%d@%dHz is not native, enabling scaling\n", 8225 8217 adjusted_mode->hdisplay, adjusted_mode->vdisplay, 8226 8218 drm_mode_vrefresh(adjusted_mode)); 8227 - dm_new_connector_state->scaling = RMX_FULL; 8219 + dm_new_connector_state->scaling = RMX_ASPECT; 8228 8220 } 8229 8221 return 0; 8230 8222 } ··· 8698 8690 amdgpu_dm_connector->num_modes += 8699 8691 drm_add_modes_noedid(connector, 1920, 1080); 8700 8692 8701 - if (amdgpu_dm_connector->dc_sink->edid_caps.analog) { 8693 + if (amdgpu_dm_connector->dc_sink && amdgpu_dm_connector->dc_sink->edid_caps.analog) { 8702 8694 /* Analog monitor connected by DAC load detection. 8703 8695 * Add common modes. It will be up to the user to select one that works. 8704 8696 */

+2 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

··· 1303 1303 if (connector->status != connector_status_connected) 1304 1304 return -ENODEV; 1305 1305 1306 - if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) 1306 + if (pipe_ctx && pipe_ctx->stream_res.tg && 1307 + pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) 1307 1308 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments); 1308 1309 1309 1310 seq_printf(m, "%d\n", segments);

+9 -9

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

··· 201 201 struct mod_hdcp_link_adjustment link_adjust; 202 202 struct mod_hdcp_display_adjustment display_adjust; 203 203 unsigned int conn_index = aconnector->base.index; 204 + const struct dc *dc = aconnector->dc_link->dc; 204 205 205 206 guard(mutex)(&hdcp_w->mutex); 206 207 drm_connector_get(&aconnector->base); ··· 232 231 link_adjust.hdcp1.disable = 1; 233 232 link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1; 234 233 } 234 + link_adjust.hdcp2.use_fw_locality_check = 235 + (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable); 236 + link_adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback; 235 237 236 238 schedule_delayed_work(&hdcp_w->property_validate_dwork, 237 239 msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS)); ··· 538 534 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; 539 535 struct dc_sink *sink = NULL; 540 536 bool link_is_hdcp14 = false; 537 + const struct dc *dc = aconnector->dc_link->dc; 541 538 542 539 if (config->dpms_off) { 543 540 hdcp_remove_display(hdcp_work, link_index, aconnector); ··· 580 575 link->adjust.auth_delay = 2; 581 576 link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS; 582 577 link->adjust.hdcp1.disable = 0; 578 + link->adjust.hdcp2.use_fw_locality_check = (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable); 579 + link->adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback; 583 580 hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 584 581 585 582 DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, ··· 793 786 ddc_funcs->read_i2c = lp_read_i2c; 794 787 ddc_funcs->write_dpcd = lp_write_dpcd; 795 788 ddc_funcs->read_dpcd = lp_read_dpcd; 796 - 797 - config->debug.lc_enable_sw_fallback = dc->debug.hdcp_lc_enable_sw_fallback; 798 - if (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable) { 799 - ddc_funcs->atomic_write_poll_read_i2c = lp_atomic_write_poll_read_i2c; 800 - ddc_funcs->atomic_write_poll_read_aux = lp_atomic_write_poll_read_aux; 801 - } else { 802 - ddc_funcs->atomic_write_poll_read_i2c = NULL; 803 - ddc_funcs->atomic_write_poll_read_aux = NULL; 804 - } 789 + ddc_funcs->atomic_write_poll_read_i2c = lp_atomic_write_poll_read_i2c; 790 + ddc_funcs->atomic_write_poll_read_aux = lp_atomic_write_poll_read_aux; 805 791 806 792 memset(hdcp_work[i].aconnector, 0, 807 793 sizeof(struct amdgpu_dm_connector *) *

+4

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 3389 3389 for (i = 0; i < status->plane_count; i++) { 3390 3390 dc_plane_copy_config(status->plane_states[i], &scratch->plane_states[i]); 3391 3391 } 3392 + 3393 + // refcount is persistent 3394 + struct kref temp_refcount = stream->refcount; 3392 3395 *stream = scratch->stream_state; 3396 + stream->refcount = temp_refcount; 3393 3397 } 3394 3398 3395 3399 /**

+4 -1

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

··· 38 38 #include "dccg.h" 39 39 #include "abm.h" 40 40 #include "dcn10/dcn10_hubbub.h" 41 + #include "dce/dmub_hw_lock_mgr.h" 41 42 42 43 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 43 44 #define MAX_NUM_MCACHE 8 ··· 765 764 if (dc->hwss.dmub_hw_control_lock_fast) { 766 765 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc; 767 766 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true; 768 - block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context); 767 + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = 768 + dc_state_is_fams2_in_use(dc, context) || 769 + dmub_hw_lock_mgr_does_link_require_lock(dc, stream->link); 769 770 block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST; 770 771 (*num_steps)++; 771 772 }

+1 -1

drivers/gpu/drm/amd/display/dc/dc.h

··· 63 63 struct dcn_optc_reg_state; 64 64 struct dcn_dccg_reg_state; 65 65 66 - #define DC_VER "3.2.356" 66 + #define DC_VER "3.2.357" 67 67 68 68 /** 69 69 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC

+38 -20

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

··· 61 61 dc_dmub_srv_wait_for_inbox0_ack(dmub_srv); 62 62 } 63 63 64 + bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link) 65 + { 66 + if (!link) 67 + return false; 68 + 69 + if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) 70 + return true; 71 + 72 + if (link->replay_settings.replay_feature_enabled) 73 + return true; 74 + 75 + if (link->psr_settings.psr_version == DC_PSR_VERSION_1) { 76 + struct dc_link *edp_links[MAX_NUM_EDP]; 77 + int edp_num; 78 + 79 + dc_get_edp_links(dc, edp_links, &edp_num); 80 + if (edp_num == 1) 81 + return true; 82 + } 83 + return false; 84 + } 85 + 86 + bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context) 87 + { 88 + if (!context) 89 + return false; 90 + for (int i = 0; i < context->stream_count; i++) { 91 + const struct dc_link *link = context->streams[i]->link; 92 + 93 + if (dmub_hw_lock_mgr_does_link_require_lock(dc, link)) 94 + return true; 95 + } 96 + return false; 97 + } 98 + 64 99 bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link) 65 100 { 66 101 /* ASIC doesn't support DMUB */ 67 102 if (!dc->ctx->dmub_srv) 68 103 return false; 69 104 70 - if (link) { 105 + if (dc->ctx->dce_version >= DCN_VERSION_4_01) 106 + return false; 71 107 72 - if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) 73 - return true; 74 - 75 - if (link->replay_settings.replay_feature_enabled) 76 - return true; 77 - 78 - /* only use HW lock for PSR1 on single eDP */ 79 - if (link->psr_settings.psr_version == DC_PSR_VERSION_1) { 80 - struct dc_link *edp_links[MAX_NUM_EDP]; 81 - int edp_num; 82 - 83 - dc_get_edp_links(dc, edp_links, &edp_num); 84 - 85 - if (edp_num == 1) 86 - return true; 87 - } 88 - } 89 - 90 - return false; 108 + return dmub_hw_lock_mgr_does_link_require_lock(dc, link); 91 109 }

+2

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

··· 46 46 * Return: true if the inbox1 lock should be used, false otherwise 47 47 */ 48 48 bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link); 49 + bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link); 50 + bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context); 49 51 50 52 #endif /*_DMUB_HW_LOCK_MGR_H_ */

+2

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h

··· 121 121 uint32_t crq_expansion_mode; 122 122 uint32_t plane1_base_address; 123 123 uint32_t unbounded_request_enabled; 124 + bool pte_buffer_mode; 125 + bool force_one_row_for_frame; 124 126 125 127 // MRQ 126 128 uint32_t mrq_expansion_mode;

+10 -4

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h

··· 87 87 dml2_dp_rate_uhbr20 = 6 88 88 }; 89 89 90 + enum dml2_pstate_type { 91 + dml2_pstate_type_uclk = 0, 92 + dml2_pstate_type_fclk = 1, 93 + dml2_pstate_type_ppt = 2, 94 + dml2_pstate_type_temp_read = 3, 95 + dml2_pstate_type_dummy_pstate = 4, 96 + dml2_pstate_type_count = 5 97 + }; 98 + 90 99 enum dml2_uclk_pstate_change_strategy { 91 100 dml2_uclk_pstate_change_strategy_auto = 0, 92 101 dml2_uclk_pstate_change_strategy_force_vactive = 1, ··· 402 393 // reserved_vblank_time_ns is the minimum time to reserve in vblank for Twait 403 394 // The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override. 404 395 long reserved_vblank_time_ns; 405 - unsigned int max_vactive_det_fill_delay_us; // 0 = no reserved time, +ve = explicit max delay 406 - unsigned int vactive_latency_to_hide_for_pstate_admissibility_us; 396 + unsigned int max_vactive_det_fill_delay_us[dml2_pstate_type_count]; // 0 = no reserved time, +ve = explicit max delay 407 397 unsigned int gpuvm_min_page_size_kbytes; 408 398 unsigned int hostvm_min_page_size_kbytes; 409 399 ··· 431 423 bool disable_dynamic_odm; 432 424 bool disable_subvp; 433 425 int minimum_vblank_idle_requirement_us; 434 - bool minimize_active_latency_hiding; 435 426 436 427 struct { 437 428 struct { ··· 496 489 bool synchronize_ddr_displays_for_uclk_pstate_change; 497 490 bool max_outstanding_when_urgent_expected_disable; 498 491 bool enable_subvp_implicit_pmo; //enables PMO to switch pipe uclk strategy to subvp, and generate phantom programming 499 - unsigned int best_effort_min_active_latency_hiding_us; 500 492 bool all_streams_blanked; 501 493 } overrides; 502 494 };

+3 -3

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h

··· 89 89 90 90 struct dml2_soc_power_management_parameters { 91 91 double dram_clk_change_blackout_us; 92 - double dram_clk_change_read_only_us; 93 - double dram_clk_change_write_only_us; 92 + double dram_clk_change_read_only_us; // deprecated 93 + double dram_clk_change_write_only_us; // deprecated 94 94 double fclk_change_blackout_us; 95 95 double g7_ppt_blackout_us; 96 96 double g7_temperature_read_blackout_us; ··· 191 191 unsigned int subvp_prefetch_end_to_mall_start_us; 192 192 unsigned int subvp_fw_processing_delay; 193 193 unsigned int max_vactive_det_fill_delay_us; 194 - unsigned int ppt_max_allow_delay_ns; 194 + unsigned int ppt_max_allow_delay_us; 195 195 unsigned int temp_read_max_allow_delay_us; 196 196 unsigned int dummy_pstate_max_allow_delay_us; 197 197 /* FAMS2 delays */

+2 -8

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

··· 195 195 } informative; 196 196 }; 197 197 198 - enum dml2_pstate_type { 199 - dml2_pstate_type_uclk, 200 - dml2_pstate_type_ppt, 201 - dml2_pstate_type_temp_read, 202 - dml2_pstate_type_dummy_pstate, 203 - dml2_pstate_type_count 204 - }; 205 - 206 198 enum dml2_pstate_method { 207 199 dml2_pstate_method_na = 0, 208 200 /* hw exclusive modes */ ··· 676 684 unsigned int PrefetchMode[DML2_MAX_PLANES]; // LEGACY_ONLY 677 685 bool ROBUrgencyAvoidance; 678 686 double LowestPrefetchMargin; 687 + 688 + unsigned int pstate_recout_reduction_lines[DML2_MAX_PLANES]; 679 689 } misc; 680 690 681 691 struct dml2_mode_support_info mode_support_info;

+20 -19

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

··· 6972 6972 6973 6973 stream_index = p->display_cfg->plane_descriptors[plane_index].stream_index; 6974 6974 6975 - dst_lines_to_hide = (unsigned int)math_ceil(p->latency_to_hide_us / 6975 + dst_lines_to_hide = (unsigned int)math_ceil(p->latency_to_hide_us[0] / 6976 6976 ((double)p->display_cfg->stream_descriptors[stream_index].timing.h_total / 6977 6977 (double)p->display_cfg->stream_descriptors[stream_index].timing.pixel_clock_khz * 1000.0)); 6978 6978 ··· 7069 7069 excess_vactive_fill_bw_l[plane_index] = 0.0; 7070 7070 excess_vactive_fill_bw_c[plane_index] = 0.0; 7071 7071 7072 - if (display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us > 0) { 7073 - excess_vactive_fill_bw_l[plane_index] = (double)bytes_required_l[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us; 7074 - excess_vactive_fill_bw_c[plane_index] = (double)bytes_required_c[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us; 7072 + if (display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] > 0) { 7073 + excess_vactive_fill_bw_l[plane_index] = (double)bytes_required_l[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk]; 7074 + excess_vactive_fill_bw_c[plane_index] = (double)bytes_required_c[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk]; 7075 7075 } 7076 7076 } 7077 7077 } ··· 9051 9051 calculate_bytes_to_fetch_required_to_hide_latency_params->swath_width_c = mode_lib->ms.SwathWidthC; 9052 9052 calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_l = mode_lib->ms.SwathHeightY; 9053 9053 calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_c = mode_lib->ms.SwathHeightC; 9054 - calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us; 9054 + calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us[0] = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us; 9055 9055 9056 9056 /* outputs */ 9057 - calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l; 9058 - calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c; 9057 + calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l[dml2_pstate_type_uclk]; 9058 + calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c[dml2_pstate_type_uclk]; 9059 9059 9060 9060 calculate_bytes_to_fetch_required_to_hide_latency(calculate_bytes_to_fetch_required_to_hide_latency_params); 9061 9061 ··· 9063 9063 calculate_excess_vactive_bandwidth_required( 9064 9064 display_cfg, 9065 9065 mode_lib->ms.num_active_planes, 9066 - s->pstate_bytes_required_l, 9067 - s->pstate_bytes_required_c, 9066 + s->pstate_bytes_required_l[dml2_pstate_type_uclk], 9067 + s->pstate_bytes_required_c[dml2_pstate_type_uclk], 9068 9068 /* outputs */ 9069 9069 mode_lib->ms.excess_vactive_fill_bw_l, 9070 9070 mode_lib->ms.excess_vactive_fill_bw_c); ··· 9506 9506 calculate_vactive_det_fill_latency( 9507 9507 display_cfg, 9508 9508 mode_lib->ms.num_active_planes, 9509 - s->pstate_bytes_required_l, 9510 - s->pstate_bytes_required_c, 9509 + s->pstate_bytes_required_l[dml2_pstate_type_uclk], 9510 + s->pstate_bytes_required_c[dml2_pstate_type_uclk], 9511 9511 mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p0, 9512 9512 mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p1, 9513 9513 mode_lib->ms.vactive_sw_bw_l, ··· 9515 9515 mode_lib->ms.surface_avg_vactive_required_bw, 9516 9516 mode_lib->ms.surface_peak_required_bw, 9517 9517 /* outputs */ 9518 - mode_lib->ms.dram_change_vactive_det_fill_delay_us); 9518 + mode_lib->ms.pstate_vactive_det_fill_delay_us[dml2_pstate_type_uclk]); 9519 9519 9520 9520 #ifdef __DML_VBA_DEBUG__ 9521 9521 DML_LOG_VERBOSE("DML::%s: max_urgent_latency_us = %f\n", __func__, s->mSOCParameters.max_urgent_latency_us); ··· 11009 11009 calculate_bytes_to_fetch_required_to_hide_latency_params->swath_width_c = mode_lib->mp.SwathWidthC; 11010 11010 calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_l = mode_lib->mp.SwathHeightY; 11011 11011 calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_c = mode_lib->mp.SwathHeightC; 11012 - calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us; 11012 + calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us[0] = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us; 11013 11013 11014 11014 /* outputs */ 11015 - calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l; 11016 - calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c; 11015 + calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l[dml2_pstate_type_uclk]; 11016 + calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c[dml2_pstate_type_uclk]; 11017 11017 11018 11018 calculate_bytes_to_fetch_required_to_hide_latency(calculate_bytes_to_fetch_required_to_hide_latency_params); 11019 11019 ··· 11021 11021 calculate_excess_vactive_bandwidth_required( 11022 11022 display_cfg, 11023 11023 s->num_active_planes, 11024 - s->pstate_bytes_required_l, 11025 - s->pstate_bytes_required_c, 11024 + s->pstate_bytes_required_l[dml2_pstate_type_uclk], 11025 + s->pstate_bytes_required_c[dml2_pstate_type_uclk], 11026 11026 /* outputs */ 11027 11027 mode_lib->mp.excess_vactive_fill_bw_l, 11028 11028 mode_lib->mp.excess_vactive_fill_bw_c); ··· 12943 12943 12944 12944 out->active_latency_hiding_us = (int)mode_lib->ms.VActiveLatencyHidingUs[plane_idx]; 12945 12945 12946 - out->dram_change_vactive_det_fill_delay_us = (unsigned int)math_ceil(mode_lib->ms.dram_change_vactive_det_fill_delay_us[plane_idx]); 12946 + out->vactive_det_fill_delay_us[dml2_pstate_type_uclk] = 12947 + (unsigned int)math_ceil(mode_lib->ms.pstate_vactive_det_fill_delay_us[plane_idx][dml2_pstate_type_uclk]); 12947 12948 } 12948 12949 12949 12950 void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_stream_support_info *out, int plane_index) ··· 13025 13024 out->informative.mode_support_info.InvalidCombinationOfMALLUseForPState = mode_lib->ms.support.InvalidCombinationOfMALLUseForPState; 13026 13025 out->informative.mode_support_info.ExceededMALLSize = mode_lib->ms.support.ExceededMALLSize; 13027 13026 out->informative.mode_support_info.EnoughWritebackUnits = mode_lib->ms.support.EnoughWritebackUnits; 13028 - out->informative.mode_support_info.temp_read_or_ppt_support = mode_lib->ms.support.temp_read_or_ppt_support; 13027 + out->informative.mode_support_info.temp_read_or_ppt_support = mode_lib->ms.support.global_temp_read_or_ppt_supported; 13029 13028 out->informative.mode_support_info.g6_temp_read_support = mode_lib->ms.support.g6_temp_read_support; 13030 13029 13031 13030 out->informative.mode_support_info.ExceededMultistreamSlots = mode_lib->ms.support.ExceededMultistreamSlots;

+20 -14

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h

··· 264 264 bool DCCMetaBufferSizeNotExceeded; 265 265 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 266 266 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 267 + enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; 268 + bool global_dram_clock_change_support_required; 267 269 bool global_dram_clock_change_supported; 268 270 bool global_fclk_change_supported; 271 + bool global_temp_read_or_ppt_supported; 269 272 bool USRRetrainingSupport; 270 273 bool AvgBandwidthSupport; 271 274 bool UrgVactiveBandwidthSupport; ··· 339 336 bool incorrect_imall_usage; 340 337 341 338 bool g6_temp_read_support; 342 - bool temp_read_or_ppt_support; 343 339 344 340 struct dml2_core_internal_watermarks watermarks; 345 341 bool dcfclk_support; ··· 593 591 double VActiveLatencyHidingMargin[DML2_MAX_PLANES]; 594 592 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 595 593 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; 596 - double dram_change_vactive_det_fill_delay_us[DML2_MAX_PLANES]; 594 + double pstate_vactive_det_fill_delay_us[dml2_pstate_type_count][DML2_MAX_PLANES]; 597 595 598 596 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 599 597 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; ··· 623 621 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 624 622 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 625 623 626 - unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; 627 - unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; 624 + unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 625 + unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 628 626 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 629 627 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 630 628 ··· 648 646 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 649 647 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 650 648 651 - enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; 649 + enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; 652 650 }; 653 651 654 652 /// @brief A mega structure that houses various info for model programming step. ··· 839 837 double max_urgent_latency_us; 840 838 double df_response_time_us; 841 839 840 + enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; 842 841 // ------------------- 843 842 // Output 844 843 // ------------------- ··· 966 963 double MaxActiveFCLKChangeLatencySupported; 967 964 bool USRRetrainingSupport; 968 965 bool g6_temp_read_support; 969 - bool temp_read_or_ppt_support; 970 966 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 971 967 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 968 + enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; 972 969 bool global_dram_clock_change_supported; 973 970 bool global_fclk_change_supported; 971 + bool global_temp_read_or_ppt_supported; 974 972 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 975 973 double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; 976 974 double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; ··· 1138 1134 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1139 1135 bool stream_visited[DML2_MAX_PLANES]; 1140 1136 1141 - unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; 1142 - unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; 1137 + unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 1138 + unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 1143 1139 1144 1140 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1145 1141 double Tpre_rounded[DML2_MAX_PLANES]; ··· 1230 1226 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1231 1227 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1232 1228 1233 - unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; 1234 - unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; 1229 + unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; 1230 + unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; 1235 1231 1236 1232 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1237 1233 double Tpre_rounded[DML2_MAX_PLANES]; ··· 1317 1313 unsigned int HostVMMinPageSize; 1318 1314 unsigned int DCCMetaBufferSizeBytes; 1319 1315 bool mrq_present; 1320 - enum dml2_pstate_method *pstate_switch_modes; 1316 + enum dml2_pstate_method *uclk_pstate_switch_modes; 1321 1317 1322 1318 // Output 1323 1319 bool *PTEBufferSizeNotExceeded; ··· 1744 1740 unsigned int max_request_size_bytes; 1745 1741 unsigned int *meta_row_height_l; 1746 1742 unsigned int *meta_row_height_c; 1743 + enum dml2_pstate_method *uclk_pstate_switch_modes; 1747 1744 1748 1745 // Output 1749 1746 struct dml2_core_internal_watermarks *Watermark; 1750 1747 enum dml2_pstate_change_support *DRAMClockChangeSupport; 1748 + bool *global_dram_clock_change_support_required; 1751 1749 bool *global_dram_clock_change_supported; 1752 1750 double *MaxActiveDRAMClockChangeLatencySupported; 1753 1751 unsigned int *SubViewportLinesNeededInMALL; ··· 1760 1754 double *VActiveLatencyHidingMargin; 1761 1755 double *VActiveLatencyHidingUs; 1762 1756 bool *g6_temp_read_support; 1763 - bool *temp_read_or_ppt_support; 1757 + enum dml2_pstate_change_support *temp_read_or_ppt_support; 1758 + bool *global_temp_read_or_ppt_supported; 1764 1759 }; 1765 - 1766 1760 1767 1761 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params { 1768 1762 const struct dml2_display_cfg *display_cfg; ··· 2253 2247 unsigned int *swath_width_c; 2254 2248 unsigned int *swath_height_l; 2255 2249 unsigned int *swath_height_c; 2256 - double latency_to_hide_us; 2250 + double latency_to_hide_us[DML2_MAX_PLANES]; 2257 2251 2258 2252 /* outputs */ 2259 2253 unsigned int *bytes_required_l;

+2

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c

··· 306 306 DML_LOG_VERBOSE("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize); 307 307 if (!fail_only || support->g6_temp_read_support == 0) 308 308 DML_LOG_VERBOSE("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support); 309 + if (!fail_only || (support->global_dram_clock_change_supported == 0 && support->global_dram_clock_change_support_required)) 310 + DML_LOG_VERBOSE("DML: support: dram_clock_change_support = %d\n", support->global_dram_clock_change_supported); 309 311 if (!fail_only || support->ImmediateFlipSupport == 0) 310 312 DML_LOG_VERBOSE("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport); 311 313 if (!fail_only || support->LinkCapacitySupport == 0)

+8 -12

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

··· 1087 1087 1088 1088 /* check required stretch is allowed */ 1089 1089 if (stream_descriptor->timing.drr_config.max_instant_vtotal_delta > 0 && 1090 - stream_pstate_meta->method_drr.stretched_vtotal - stream_pstate_meta->nom_vtotal > stream_descriptor->timing.drr_config.max_instant_vtotal_delta) { 1090 + stream_pstate_meta->method_drr.stretched_vtotal - stream_pstate_meta->nom_vtotal > (int)stream_descriptor->timing.drr_config.max_instant_vtotal_delta) { 1091 1091 return false; 1092 1092 } 1093 1093 } ··· 1669 1669 return min_vactive_margin_us; 1670 1670 } 1671 1671 1672 - static unsigned int get_vactive_det_fill_latency_delay_us(const struct display_configuation_with_meta *display_cfg, int plane_mask) 1672 + static int get_vactive_det_fill_latency_delay_us(const struct display_configuation_with_meta *display_cfg, int plane_mask) 1673 1673 { 1674 1674 unsigned char i; 1675 - unsigned int max_vactive_fill_us = 0; 1675 + int max_vactive_fill_us = 0; 1676 1676 1677 1677 for (i = 0; i < DML2_MAX_PLANES; i++) { 1678 1678 if (is_bit_set_in_bitfield(plane_mask, i)) { 1679 - if (display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].dram_change_vactive_det_fill_delay_us > max_vactive_fill_us) 1680 - max_vactive_fill_us = display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].dram_change_vactive_det_fill_delay_us; 1679 + if (display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].vactive_det_fill_delay_us[dml2_pstate_type_uclk] > max_vactive_fill_us) 1680 + max_vactive_fill_us = display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].vactive_det_fill_delay_us[dml2_pstate_type_uclk]; 1681 1681 } 1682 1682 } 1683 1683 ··· 1962 1962 1963 1963 for (stream_index = 0; stream_index < display_config->display_config.num_streams; stream_index++) { 1964 1964 display_config->stage3.stream_svp_meta[stream_index].valid = false; 1965 - 1966 - display_config->display_config.stream_descriptors[stream_index].overrides.minimize_active_latency_hiding = false; 1967 - display_config->display_config.overrides.best_effort_min_active_latency_hiding_us = 0; 1968 1965 } 1969 1966 1970 1967 for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) { ··· 1994 1997 plane->overrides.uclk_pstate_change_strategy = dml2_uclk_pstate_change_strategy_force_drr; 1995 1998 1996 1999 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_drr; 1997 - 1998 2000 } 1999 2001 } 2000 2002 } ··· 2059 2063 plane->overrides.reserved_vblank_time_ns); 2060 2064 2061 2065 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_vblank; 2062 - 2063 2066 } 2064 2067 } 2065 2068 } ··· 2073 2078 for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) { 2074 2079 if (is_bit_set_in_bitfield(plane_mask, plane_index)) { 2075 2080 plane = &display_config->display_config.plane_descriptors[plane_index]; 2081 + 2076 2082 plane->overrides.reserved_vblank_time_ns = (long)(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000); 2077 2083 2078 2084 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_vblank_drr; ··· 2095 2099 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_vactive; 2096 2100 2097 2101 if (!pmo->options->disable_vactive_det_fill_bw_pad) { 2098 - display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us = 2102 + display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] = 2099 2103 (unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us); 2100 2104 } 2101 2105 } ··· 2116 2120 display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_vactive_drr; 2117 2121 2118 2122 if (!pmo->options->disable_vactive_det_fill_bw_pad) { 2119 - display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us = 2123 + display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] = 2120 2124 (unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us); 2121 2125 } 2122 2126 }

+24 -18

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h

··· 152 152 int active_latency_hiding_us; 153 153 int mall_svp_size_requirement_ways; 154 154 int nominal_vblank_pstate_latency_hiding_us; 155 - unsigned int dram_change_vactive_det_fill_delay_us; 155 + int vactive_det_fill_delay_us[dml2_pstate_type_count]; 156 156 }; 157 157 158 158 struct core_stream_support_info { ··· 209 209 210 210 unsigned int uclk_pstate_supported; 211 211 unsigned int fclk_pstate_supported; 212 + struct dml2_core_internal_watermarks watermarks; 212 213 } global; 213 214 214 215 struct { ··· 258 257 259 258 struct dml2_pstate_per_method_common_meta { 260 259 /* generic params */ 261 - unsigned int allow_start_otg_vline; 262 - unsigned int allow_end_otg_vline; 260 + int allow_start_otg_vline; 261 + int allow_end_otg_vline; 263 262 /* scheduling params */ 264 263 double allow_time_us; 265 264 double disallow_time_us; ··· 269 268 struct dml2_pstate_meta { 270 269 bool valid; 271 270 double otg_vline_time_us; 272 - unsigned int scheduling_delay_otg_vlines; 273 - unsigned int vertical_interrupt_ack_delay_otg_vlines; 274 - unsigned int allow_to_target_delay_otg_vlines; 275 - unsigned int contention_delay_otg_vlines; 276 - unsigned int min_allow_width_otg_vlines; 277 - unsigned int nom_vtotal; 278 - unsigned int vblank_start; 271 + int scheduling_delay_otg_vlines; 272 + int vertical_interrupt_ack_delay_otg_vlines; 273 + int allow_to_target_delay_otg_vlines; 274 + int contention_delay_otg_vlines; 275 + int min_allow_width_otg_vlines; 276 + int nom_vtotal; 277 + int vblank_start; 279 278 double nom_refresh_rate_hz; 280 279 double nom_frame_time_us; 281 - unsigned int max_vtotal; 280 + int max_vtotal; 282 281 double min_refresh_rate_hz; 283 282 double max_frame_time_us; 284 - unsigned int blackout_otg_vlines; 283 + int blackout_otg_vlines; 284 + int max_allow_delay_otg_vlines; 285 + double nom_vblank_time_us; 285 286 struct { 286 287 double max_vactive_det_fill_delay_us; 287 - unsigned int max_vactive_det_fill_delay_otg_vlines; 288 + double vactive_latency_hiding_us; 289 + double reserved_vblank_required_us; 290 + int max_vactive_det_fill_delay_otg_vlines; 291 + int reserved_blank_required_vlines; 288 292 struct dml2_pstate_per_method_common_meta common; 289 293 } method_vactive; 290 294 struct { 291 295 struct dml2_pstate_per_method_common_meta common; 292 296 } method_vblank; 293 297 struct { 294 - unsigned int programming_delay_otg_vlines; 295 - unsigned int df_throttle_delay_otg_vlines; 296 - unsigned int prefetch_to_mall_delay_otg_vlines; 298 + int programming_delay_otg_vlines; 299 + int df_throttle_delay_otg_vlines; 300 + int prefetch_to_mall_delay_otg_vlines; 297 301 unsigned long phantom_vactive; 298 302 unsigned long phantom_vfp; 299 303 unsigned long phantom_vtotal; 300 304 struct dml2_pstate_per_method_common_meta common; 301 305 } method_subvp; 302 306 struct { 303 - unsigned int programming_delay_otg_vlines; 304 - unsigned int stretched_vtotal; 307 + int programming_delay_otg_vlines; 308 + int stretched_vtotal; 305 309 struct dml2_pstate_per_method_common_meta common; 306 310 } method_drr; 307 311 };

+1

drivers/gpu/drm/amd/display/dc/link/link_detection.c

··· 1257 1257 !sink->edid_caps.edid_hdmi) 1258 1258 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1259 1259 else if (dc_is_dvi_signal(sink->sink_signal) && 1260 + dc_is_dvi_signal(link->connector_signal) && 1260 1261 aud_support->hdmi_audio_native && 1261 1262 sink->edid_caps.edid_hdmi) 1262 1263 sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;

+3 -2

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

··· 1847 1847 dc_state_set_stream_cursor_subvp_limit(stream, context, true); 1848 1848 status = DC_FAIL_HW_CURSOR_SUPPORT; 1849 1849 } 1850 - }; 1850 + } 1851 1851 } 1852 1852 1853 1853 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) { ··· 2200 2200 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ 2201 2201 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ 2202 2202 dc->caps.max_cursor_size = 64; 2203 - dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4) 2203 + /* floor(sqrt(buf_size_bytes / bpp ) * bpp, fixed_req_size) / bpp = max_width */ 2204 + dc->caps.max_buffered_cursor_size = 64; // floor(sqrt(16 * 1024 / 4) * 4, 256) / 4 = 64 2204 2205 dc->caps.min_horizontal_blanking_period = 80; 2205 2206 dc->caps.dmdata_alloc_size = 2048; 2206 2207 dc->caps.mall_size_per_mem_channel = 4;

+1 -1

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

··· 1671 1671 dc_state_set_stream_cursor_subvp_limit(stream, context, true); 1672 1672 status = DC_FAIL_HW_CURSOR_SUPPORT; 1673 1673 } 1674 - }; 1674 + } 1675 1675 } 1676 1676 1677 1677 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {

+407 -32

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

··· 599 599 uint32_t u32All; 600 600 }; 601 601 602 + /** 603 + * Flags that can be set by driver to change some Panel Replay behaviour. 604 + */ 605 + union pr_debug_flags { 606 + struct { 607 + /** 608 + * 0x1 (bit 0) 609 + * Enable visual confirm in FW. 610 + */ 611 + uint32_t visual_confirm : 1; 612 + 613 + /** 614 + * 0x2 (bit 1) 615 + * @skip_crc: Set if need to skip CRC. 616 + */ 617 + uint32_t skip_crc : 1; 618 + 619 + /** 620 + * 0x4 (bit 2) 621 + * @force_link_power_on: Force disable ALPM control 622 + */ 623 + uint32_t force_link_power_on : 1; 624 + 625 + /** 626 + * 0x8 (bit 3) 627 + * @force_phy_power_on: Force phy power on 628 + */ 629 + uint32_t force_phy_power_on : 1; 630 + 631 + /** 632 + * 0x10 (bit 4) 633 + * @skip_crtc_disabled: CRTC disable skipped 634 + */ 635 + uint32_t skip_crtc_disabled : 1; 636 + 637 + /* 638 + * 0x20 (bit 5) 639 + * @visual_confirm_rate_control: Enable Visual Confirm rate control detection 640 + */ 641 + uint32_t visual_confirm_rate_control : 1; 642 + 643 + uint32_t reserved : 26; 644 + } bitfields; 645 + 646 + uint32_t u32All; 647 + }; 648 + 649 + union pr_hw_flags { 650 + struct { 651 + /** 652 + * @allow_alpm_fw_standby_mode: To indicate whether the 653 + * ALPM FW standby mode is allowed 654 + */ 655 + uint32_t allow_alpm_fw_standby_mode : 1; 656 + 657 + /* 658 + * @dsc_enable_status: DSC enable status in driver 659 + */ 660 + uint32_t dsc_enable_status : 1; 661 + 662 + /** 663 + * @fec_enable_status: receive fec enable/disable status from driver 664 + */ 665 + uint32_t fec_enable_status : 1; 666 + 667 + /* 668 + * @smu_optimizations_en: SMU power optimization. 669 + * Only when active display is Replay capable and display enters Replay. 670 + * Trigger interrupt to SMU to powerup/down. 671 + */ 672 + uint32_t smu_optimizations_en : 1; 673 + 674 + /** 675 + * @phy_power_state: Indicates current phy power state 676 + */ 677 + uint32_t phy_power_state : 1; 678 + 679 + /** 680 + * @link_power_state: Indicates current link power state 681 + */ 682 + uint32_t link_power_state : 1; 683 + /** 684 + * Use TPS3 signal when restore main link. 685 + */ 686 + uint32_t force_wakeup_by_tps3 : 1; 687 + /** 688 + * @is_alpm_initialized: Indicates whether ALPM is initialized 689 + */ 690 + uint32_t is_alpm_initialized : 1; 691 + /** 692 + * @alpm_mode: Indicates ALPM mode selected 693 + */ 694 + uint32_t alpm_mode : 2; 695 + } bitfields; 696 + 697 + uint32_t u32All; 698 + }; 699 + 602 700 union fw_assisted_mclk_switch_version { 603 701 struct { 604 702 uint8_t minor : 5; ··· 1830 1732 DMUB_CMD__CURSOR_OFFLOAD = 92, 1831 1733 1832 1734 /** 1833 - * Command type used for all SMART_POWER_HDR commands. 1735 + * Command type used for all SMART_POWER_OLED commands. 1834 1736 */ 1835 - DMUB_CMD__SMART_POWER_HDR = 93, 1737 + DMUB_CMD__SMART_POWER_OLED = 93, 1738 + 1739 + /** 1740 + * Command type use for all Panel Replay commands. 1741 + */ 1742 + DMUB_CMD__PR = 94, 1743 + 1836 1744 1837 1745 /** 1838 1746 * Command type use for VBIOS shared commands. ··· 4252 4148 }; 4253 4149 4254 4150 /** 4151 + * Definition of a panel replay state 4152 + */ 4153 + enum pr_state { 4154 + PR_STATE_0 = 0x00, // State 0 steady state 4155 + // Pending SDP and Unlock before back to State 0 4156 + PR_STATE_0_PENDING_SDP_AND_UNLOCK = 0x01, 4157 + PR_STATE_1 = 0x10, // State 1 4158 + PR_STATE_2 = 0x20, // State 2 steady state 4159 + // Pending frame transmission before transition to State 2 4160 + PR_STATE_2_PENDING_FRAME_TRANSMISSION = 0x30, 4161 + // Active and Powered Up 4162 + PR_STATE_2_POWERED = 0x31, 4163 + // Active and Powered Down, but need to blank HUBP after DPG_EN latch 4164 + PR_STATE_2_PENDING_HUBP_BLANK = 0x32, 4165 + // Active and Pending Power Up 4166 + PR_STATE_2_PENDING_POWER_UP = 0x33, 4167 + // Active and Powered Up, Pending DPG latch 4168 + PR_STATE_2_PENDING_LOCK_FOR_DPG_POWER_ON = 0x34, 4169 + // Active and Powered Up, Pending SDP and Unlock 4170 + PR_STATE_2_PENDING_SDP_AND_UNLOCK = 0x35, 4171 + // Pending transmission of AS SDP for timing sync, but no rfb update 4172 + PR_STATE_2_PENDING_AS_SDP = 0x36, 4173 + // Invalid 4174 + PR_STATE_INVALID = 0xFF, 4175 + }; 4176 + 4177 + /** 4255 4178 * Replay command sub-types. 4256 4179 */ 4257 4180 enum dmub_cmd_replay_type { ··· 4326 4195 * Set Replay General command. 4327 4196 */ 4328 4197 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 4198 + }; 4199 + 4200 + /* 4201 + * Panel Replay sub-types 4202 + */ 4203 + enum dmub_cmd_panel_replay_type { 4204 + DMUB_CMD__PR_ENABLE = 0, 4205 + DMUB_CMD__PR_COPY_SETTINGS = 1, 4206 + DMUB_CMD__PR_UPDATE_STATE = 2, 4207 + DMUB_CMD__PR_GENERAL_CMD = 3, 4208 + }; 4209 + 4210 + enum dmub_cmd_panel_replay_state_update_subtype { 4211 + PR_STATE_UPDATE_COASTING_VTOTAL = 0x1, 4212 + PR_STATE_UPDATE_SYNC_MODE = 0x2, 4213 + }; 4214 + 4215 + enum dmub_cmd_panel_replay_general_subtype { 4216 + PR_GENERAL_CMD_DEBUG_OPTION = 0x1, 4329 4217 }; 4330 4218 4331 4219 /** ··· 4499 4349 */ 4500 4350 uint8_t panel_inst; 4501 4351 /** 4502 - * PSR version that FW should implement. 4352 + * Replay version that FW should implement. 4503 4353 */ 4504 4354 enum replay_version version; 4505 4355 /** 4506 - * PSR control version. 4507 - */ 4508 - uint8_t cmd_version; 4509 - /** 4510 4356 * Explicit padding to 4 byte boundary. 4511 4357 */ 4512 - uint8_t pad[2]; 4358 + uint8_t pad[3]; 4513 4359 }; 4514 4360 4515 4361 /** ··· 4551 4405 }; 4552 4406 4553 4407 /** 4554 - * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_ENABLE command. 4408 + * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 4555 4409 */ 4556 - struct dmub_rb_cmd_smart_power_hdr_enable_data { 4410 + struct dmub_rb_cmd_smart_power_oled_enable_data { 4557 4411 /** 4558 - * SMART_POWER_HDR enable or disable. 4412 + * SMART_POWER_OLED enable or disable. 4559 4413 */ 4560 4414 uint8_t enable; 4561 4415 /** ··· 4923 4777 }; 4924 4778 4925 4779 /** 4926 - * SMART POWER HDR command sub-types. 4780 + * SMART POWER OLED command sub-types. 4927 4781 */ 4928 - enum dmub_cmd_smart_power_hdr_type { 4782 + enum dmub_cmd_smart_power_oled_type { 4929 4783 4930 4784 /** 4931 - * Enable/Disable SMART_POWER_HDR. 4785 + * Enable/Disable SMART_POWER_OLED. 4932 4786 */ 4933 - DMUB_CMD__SMART_POWER_HDR_ENABLE = 1, 4787 + DMUB_CMD__SMART_POWER_OLED_ENABLE = 1, 4934 4788 /** 4935 - * Get current MaxCLL value if SMART POWER HDR is enabled. 4789 + * Get current MaxCLL value if SMART POWER OLED is enabled. 4936 4790 */ 4937 - DMUB_CMD__SMART_POWER_HDR_GETMAXCLL = 2, 4791 + DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2, 4938 4792 }; 4939 4793 4940 4794 /** 4941 - * Definition of a DMUB_CMD__SMART_POWER_HDR command. 4795 + * Definition of a DMUB_CMD__SMART_POWER_OLED command. 4942 4796 */ 4943 - struct dmub_rb_cmd_smart_power_hdr_enable { 4797 + struct dmub_rb_cmd_smart_power_oled_enable { 4944 4798 /** 4945 4799 * Command header. 4946 4800 */ 4947 4801 struct dmub_cmd_header header; 4948 4802 4949 - struct dmub_rb_cmd_smart_power_hdr_enable_data data; 4803 + struct dmub_rb_cmd_smart_power_oled_enable_data data; 4950 4804 }; 4951 4805 4952 - struct dmub_cmd_smart_power_hdr_getmaxcll_input { 4806 + struct dmub_cmd_smart_power_oled_getmaxcll_input { 4953 4807 uint8_t panel_inst; 4954 4808 uint8_t pad[3]; 4955 4809 }; 4956 4810 4957 - struct dmub_cmd_smart_power_hdr_getmaxcll_output { 4811 + struct dmub_cmd_smart_power_oled_getmaxcll_output { 4958 4812 uint16_t current_max_cll; 4959 4813 uint8_t pad[2]; 4960 4814 }; 4961 4815 4962 4816 /** 4963 - * Definition of a DMUB_CMD__SMART_POWER_HDR command. 4817 + * Definition of a DMUB_CMD__SMART_POWER_OLED command. 4964 4818 */ 4965 - struct dmub_rb_cmd_smart_power_hdr_getmaxcll { 4819 + struct dmub_rb_cmd_smart_power_oled_getmaxcll { 4966 4820 struct dmub_cmd_header header; /**< Command header */ 4967 4821 /** 4968 - * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. 4822 + * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 4969 4823 */ 4970 - union dmub_cmd_smart_power_hdr_getmaxcll_data { 4971 - struct dmub_cmd_smart_power_hdr_getmaxcll_input input; /**< Input */ 4972 - struct dmub_cmd_smart_power_hdr_getmaxcll_output output; /**< Output */ 4824 + union dmub_cmd_smart_power_oled_getmaxcll_data { 4825 + struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**< Input */ 4826 + struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**< Output */ 4973 4827 uint32_t output_raw; /**< Raw data output */ 4974 4828 } data; 4975 4829 }; ··· 6503 6357 }; 6504 6358 6505 6359 /** 6360 + * Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command. 6361 + */ 6362 + struct dmub_cmd_pr_enable_data { 6363 + /** 6364 + * Panel Replay enable or disable. 6365 + */ 6366 + uint8_t enable; 6367 + /** 6368 + * Panel Instance. 6369 + * Panel isntance to identify which replay_state to use 6370 + * Currently the support is only for 0 or 1 6371 + */ 6372 + uint8_t panel_inst; 6373 + /** 6374 + * Phy state to enter. 6375 + * Values to use are defined in dmub_phy_fsm_state 6376 + */ 6377 + uint8_t phy_fsm_state; 6378 + /** 6379 + * Phy rate for DP - RBR/HBR/HBR2/HBR3. 6380 + * Set this using enum phy_link_rate. 6381 + * This does not support HDMI/DP2 for now. 6382 + */ 6383 + uint8_t phy_rate; 6384 + /** 6385 + * @hpo_stream_enc_inst: HPO stream encoder instance 6386 + */ 6387 + uint8_t hpo_stream_enc_inst; 6388 + /** 6389 + * @hpo_link_enc_inst: HPO link encoder instance 6390 + */ 6391 + uint8_t hpo_link_enc_inst; 6392 + /** 6393 + * @pad: Align structure to 4 byte boundary. 6394 + */ 6395 + uint8_t pad[2]; 6396 + }; 6397 + 6398 + /** 6399 + * Definition of a DMUB_CMD__PR_ENABLE command. 6400 + * Panel Replay enable/disable is controlled using action in data. 6401 + */ 6402 + struct dmub_rb_cmd_pr_enable { 6403 + /** 6404 + * Command header. 6405 + */ 6406 + struct dmub_cmd_header header; 6407 + 6408 + struct dmub_cmd_pr_enable_data data; 6409 + }; 6410 + 6411 + /** 6412 + * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 6413 + */ 6414 + struct dmub_cmd_pr_copy_settings_data { 6415 + /** 6416 + * Flags that can be set by driver to change some replay behaviour. 6417 + */ 6418 + union pr_debug_flags debug; 6419 + 6420 + /** 6421 + * @flags: Flags used to determine feature functionality. 6422 + */ 6423 + union pr_hw_flags flags; 6424 + 6425 + /** 6426 + * DPP HW instance. 6427 + */ 6428 + uint8_t dpp_inst; 6429 + /** 6430 + * OTG HW instance. 6431 + */ 6432 + uint8_t otg_inst; 6433 + /** 6434 + * DIG FE HW instance. 6435 + */ 6436 + uint8_t digfe_inst; 6437 + /** 6438 + * DIG BE HW instance. 6439 + */ 6440 + uint8_t digbe_inst; 6441 + /** 6442 + * AUX HW instance. 6443 + */ 6444 + uint8_t aux_inst; 6445 + /** 6446 + * Panel Instance. 6447 + * Panel isntance to identify which psr_state to use 6448 + * Currently the support is only for 0 or 1 6449 + */ 6450 + uint8_t panel_inst; 6451 + /** 6452 + * Length of each horizontal line in ns. 6453 + */ 6454 + uint32_t line_time_in_ns; 6455 + /** 6456 + * PHY instance. 6457 + */ 6458 + uint8_t dpphy_inst; 6459 + /** 6460 + * Determines if SMU optimzations are enabled/disabled. 6461 + */ 6462 + uint8_t smu_optimizations_en; 6463 + /* 6464 + * Use FSM state for Replay power up/down 6465 + */ 6466 + uint8_t use_phy_fsm; 6467 + /* 6468 + * Use FSFT afftet pixel clk 6469 + */ 6470 + uint32_t pix_clk_100hz; 6471 + /* 6472 + * Use Original pixel clock 6473 + */ 6474 + uint32_t sink_pix_clk_100hz; 6475 + /** 6476 + * Use for AUX-less ALPM LFPS wake operation 6477 + */ 6478 + struct dmub_alpm_auxless_data auxless_alpm_data; 6479 + /** 6480 + * @hpo_stream_enc_inst: HPO stream encoder instance 6481 + */ 6482 + uint8_t hpo_stream_enc_inst; 6483 + /** 6484 + * @hpo_link_enc_inst: HPO link encoder instance 6485 + */ 6486 + uint8_t hpo_link_enc_inst; 6487 + /** 6488 + * @pad: Align structure to 4 byte boundary. 6489 + */ 6490 + uint8_t pad[2]; 6491 + }; 6492 + 6493 + /** 6494 + * Definition of a DMUB_CMD__PR_COPY_SETTINGS command. 6495 + */ 6496 + struct dmub_rb_cmd_pr_copy_settings { 6497 + /** 6498 + * Command header. 6499 + */ 6500 + struct dmub_cmd_header header; 6501 + /** 6502 + * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. 6503 + */ 6504 + struct dmub_cmd_pr_copy_settings_data data; 6505 + }; 6506 + 6507 + struct dmub_cmd_pr_update_state_data { 6508 + /** 6509 + * Panel Instance. 6510 + * Panel isntance to identify which psr_state to use 6511 + * Currently the support is only for 0 or 1 6512 + */ 6513 + uint8_t panel_inst; 6514 + 6515 + uint8_t pad[3]; // align to 4-byte boundary 6516 + /* 6517 + * Update flags to control the update behavior. 6518 + */ 6519 + uint32_t update_flag; 6520 + /** 6521 + * state/data to set. 6522 + */ 6523 + uint32_t coasting_vtotal; 6524 + uint32_t sync_mode; 6525 + }; 6526 + 6527 + struct dmub_cmd_pr_general_cmd_data { 6528 + /** 6529 + * Panel Instance. 6530 + * Panel isntance to identify which psr_state to use 6531 + * Currently the support is only for 0 or 1 6532 + */ 6533 + uint8_t panel_inst; 6534 + /** 6535 + * subtype: PR general cmd sub type 6536 + */ 6537 + uint8_t subtype; 6538 + 6539 + uint8_t pad[2]; 6540 + /** 6541 + * config data by different subtypes 6542 + */ 6543 + union { 6544 + uint32_t u32All; 6545 + } data; 6546 + }; 6547 + 6548 + /** 6549 + * Definition of a DMUB_CMD__PR_UPDATE_STATE command. 6550 + */ 6551 + struct dmub_rb_cmd_pr_update_state { 6552 + /** 6553 + * Command header. 6554 + */ 6555 + struct dmub_cmd_header header; 6556 + /** 6557 + * Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command. 6558 + */ 6559 + struct dmub_cmd_pr_update_state_data data; 6560 + }; 6561 + 6562 + /** 6563 + * Definition of a DMUB_CMD__PR_GENERAL_CMD command. 6564 + */ 6565 + struct dmub_rb_cmd_pr_general_cmd { 6566 + /** 6567 + * Command header. 6568 + */ 6569 + struct dmub_cmd_header header; 6570 + /** 6571 + * Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command. 6572 + */ 6573 + struct dmub_cmd_pr_general_cmd_data data; 6574 + }; 6575 + 6576 + /** 6506 6577 * union dmub_rb_cmd - DMUB inbox command. 6507 6578 */ 6508 6579 union dmub_rb_cmd { ··· 7061 6698 */ 7062 6699 struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; 7063 6700 /** 7064 - * Definition of a DMUB_CMD__SMART_POWER_HDR_ENABLE command. 6701 + * Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command. 7065 6702 */ 7066 - struct dmub_rb_cmd_smart_power_hdr_enable smart_power_hdr_enable; 6703 + struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable; 7067 6704 /** 7068 - * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. 6705 + * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. 7069 6706 */ 7070 - struct dmub_rb_cmd_smart_power_hdr_getmaxcll smart_power_hdr_getmaxcll; 6707 + struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll; 6708 + /* 6709 + * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6710 + */ 6711 + struct dmub_rb_cmd_pr_copy_settings pr_copy_settings; 6712 + /** 6713 + * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6714 + */ 6715 + struct dmub_rb_cmd_pr_enable pr_enable; 6716 + 6717 + struct dmub_rb_cmd_pr_update_state pr_update_state; 6718 + 6719 + struct dmub_rb_cmd_pr_general_cmd pr_general_cmd; 7071 6720 }; 7072 6721 7073 6722 /**

+1 -1

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

··· 66 66 #define DMUB_SCRATCH_MEM_SIZE (1024) 67 67 68 68 /* Default indirect buffer size. */ 69 - #define DMUB_IB_MEM_SIZE (1280) 69 + #define DMUB_IB_MEM_SIZE (2560) 70 70 71 71 /* Default LSDMA ring buffer size. */ 72 72 #define DMUB_LSDMA_RB_SIZE (64 * 1024)

+1

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h

··· 88 88 uint8_t lc_init_write; 89 89 uint8_t l_prime_available_poll; 90 90 uint8_t l_prime_read; 91 + uint8_t l_prime_combo_read; 91 92 uint8_t l_prime_validation; 92 93 uint8_t eks_prepare; 93 94 uint8_t eks_write;

+22 -46

drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c

··· 465 465 return status; 466 466 } 467 467 468 - static enum mod_hdcp_status locality_check_sw(struct mod_hdcp *hdcp, 469 - struct mod_hdcp_event_context *event_ctx, 470 - struct mod_hdcp_transition_input_hdcp2 *input) 471 - { 472 - enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; 473 - 474 - if (!mod_hdcp_execute_and_set(mod_hdcp_write_lc_init, 475 - &input->lc_init_write, &status, 476 - hdcp, "lc_init_write")) 477 - goto out; 478 - if (is_dp_hdcp(hdcp)) 479 - msleep(16); 480 - else 481 - if (!mod_hdcp_execute_and_set(poll_l_prime_available, 482 - &input->l_prime_available_poll, &status, 483 - hdcp, "l_prime_available_poll")) 484 - goto out; 485 - if (!mod_hdcp_execute_and_set(mod_hdcp_read_l_prime, 486 - &input->l_prime_read, &status, 487 - hdcp, "l_prime_read")) 488 - goto out; 489 - out: 490 - return status; 491 - } 492 - 493 - static enum mod_hdcp_status locality_check_fw(struct mod_hdcp *hdcp, 494 - struct mod_hdcp_event_context *event_ctx, 495 - struct mod_hdcp_transition_input_hdcp2 *input) 496 - { 497 - enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; 498 - 499 - if (!mod_hdcp_execute_and_set(mod_hdcp_write_poll_read_lc_fw, 500 - &input->l_prime_read, &status, 501 - hdcp, "l_prime_read")) 502 - goto out; 503 - 504 - out: 505 - return status; 506 - } 507 - 508 468 static enum mod_hdcp_status locality_check(struct mod_hdcp *hdcp, 509 469 struct mod_hdcp_event_context *event_ctx, 510 470 struct mod_hdcp_transition_input_hdcp2 *input) 511 471 { 512 472 enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; 513 - const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c 514 - && hdcp->config.ddc.funcs.atomic_write_poll_read_aux 515 - && !hdcp->connection.link.adjust.hdcp2.force_sw_locality_check; 516 473 517 474 if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) { 518 475 event_ctx->unexpected_event = 1; ··· 481 524 hdcp, "lc_init_prepare")) 482 525 goto out; 483 526 484 - status = (use_fw ? locality_check_fw : locality_check_sw)(hdcp, event_ctx, input); 485 - if (status != MOD_HDCP_STATUS_SUCCESS) 486 - goto out; 527 + if (hdcp->connection.link.adjust.hdcp2.use_fw_locality_check) { 528 + if (!mod_hdcp_execute_and_set(mod_hdcp_write_poll_read_lc_fw, 529 + &input->l_prime_combo_read, &status, 530 + hdcp, "l_prime_combo_read")) 531 + goto out; 532 + } else { 533 + if (!mod_hdcp_execute_and_set(mod_hdcp_write_lc_init, 534 + &input->lc_init_write, &status, 535 + hdcp, "lc_init_write")) 536 + goto out; 537 + if (is_dp_hdcp(hdcp)) 538 + msleep(16); 539 + else 540 + if (!mod_hdcp_execute_and_set(poll_l_prime_available, 541 + &input->l_prime_available_poll, &status, 542 + hdcp, "l_prime_available_poll")) 543 + goto out; 544 + if (!mod_hdcp_execute_and_set(mod_hdcp_read_l_prime, 545 + &input->l_prime_read, &status, 546 + hdcp, "l_prime_read")) 547 + goto out; 548 + } 487 549 488 550 if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_l_prime, 489 551 &input->l_prime_validation, &status,

+32 -29

drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c

··· 184 184 callback_in_ms(0, output); 185 185 set_state_id(hdcp, output, H2_A2_LOCALITY_CHECK); 186 186 break; 187 - case H2_A2_LOCALITY_CHECK: { 188 - const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c 189 - && !adjust->hdcp2.force_sw_locality_check; 190 - 191 - /* 192 - * 1A-05: consider disconnection after LC init a failure 193 - * 1A-13-1: consider invalid l' a failure 194 - * 1A-13-2: consider l' timeout a failure 195 - */ 187 + case H2_A2_LOCALITY_CHECK: 188 + /* 1A-05: consider disconnection after LC init a failure */ 196 189 if (hdcp->state.stay_count > 10 || 197 - input->lc_init_prepare != PASS || 198 - (!use_fw && input->lc_init_write != PASS) || 199 - (!use_fw && input->l_prime_available_poll != PASS)) { 190 + input->lc_init_prepare != PASS) { 200 191 fail_and_restart_in_ms(0, &status, output); 201 192 break; 202 - } else if (input->l_prime_read != PASS) { 203 - if (use_fw && hdcp->config.debug.lc_enable_sw_fallback) { 204 - adjust->hdcp2.force_sw_locality_check = true; 193 + } else if (adjust->hdcp2.use_fw_locality_check && 194 + input->l_prime_combo_read != PASS) { 195 + /* 1A-13-2: consider l' timeout a failure */ 196 + if (adjust->hdcp2.use_sw_locality_fallback) { 197 + /* switch to software locality check */ 198 + adjust->hdcp2.use_fw_locality_check = 0; 205 199 callback_in_ms(0, output); 200 + increment_stay_counter(hdcp); 206 201 break; 207 202 } 208 - 203 + fail_and_restart_in_ms(0, &status, output); 204 + break; 205 + } else if (!adjust->hdcp2.use_fw_locality_check && 206 + (input->lc_init_write != PASS || 207 + input->l_prime_available_poll != PASS || 208 + input->l_prime_read != PASS)) { 209 + /* 1A-13-2: consider l' timeout a failure */ 209 210 fail_and_restart_in_ms(0, &status, output); 210 211 break; 211 212 } else if (input->l_prime_validation != PASS) { 213 + /* 1A-13-1: consider invalid l' a failure */ 212 214 callback_in_ms(0, output); 213 215 increment_stay_counter(hdcp); 214 216 break; ··· 218 216 callback_in_ms(0, output); 219 217 set_state_id(hdcp, output, H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER); 220 218 break; 221 - } 222 219 case H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER: 223 220 if (input->eks_prepare != PASS || 224 221 input->eks_write != PASS) { ··· 511 510 callback_in_ms(0, output); 512 511 set_state_id(hdcp, output, D2_A2_LOCALITY_CHECK); 513 512 break; 514 - case D2_A2_LOCALITY_CHECK: { 515 - const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_aux 516 - && !adjust->hdcp2.force_sw_locality_check; 517 - 513 + case D2_A2_LOCALITY_CHECK: 518 514 if (hdcp->state.stay_count > 10 || 519 - input->lc_init_prepare != PASS || 520 - (!use_fw && input->lc_init_write != PASS)) { 521 - /* 1A-12: consider invalid l' a failure */ 515 + input->lc_init_prepare != PASS) { 522 516 fail_and_restart_in_ms(0, &status, output); 523 517 break; 524 - } else if (input->l_prime_read != PASS) { 525 - if (use_fw && hdcp->config.debug.lc_enable_sw_fallback) { 526 - adjust->hdcp2.force_sw_locality_check = true; 518 + } else if (adjust->hdcp2.use_fw_locality_check && 519 + input->l_prime_combo_read != PASS) { 520 + if (adjust->hdcp2.use_sw_locality_fallback) { 521 + /* switch to software locality check */ 522 + adjust->hdcp2.use_fw_locality_check = 0; 527 523 callback_in_ms(0, output); 524 + increment_stay_counter(hdcp); 528 525 break; 529 526 } 530 - 527 + fail_and_restart_in_ms(0, &status, output); 528 + break; 529 + } else if (!adjust->hdcp2.use_fw_locality_check && 530 + (input->lc_init_write != PASS || 531 + input->l_prime_read != PASS)) { 531 532 fail_and_restart_in_ms(0, &status, output); 532 533 break; 533 534 } else if (input->l_prime_validation != PASS) { 535 + /* 1A-12: consider invalid l' a failure */ 534 536 callback_in_ms(0, output); 535 537 increment_stay_counter(hdcp); 536 538 break; ··· 541 537 callback_in_ms(0, output); 542 538 set_state_id(hdcp, output, D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER); 543 539 break; 544 - } 545 540 case D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER: 546 541 if (input->eks_prepare != PASS || 547 542 input->eks_write != PASS) {

+1 -1

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

··· 758 758 { 759 759 const bool success = (is_dp_hdcp(hdcp) ? write_stall_read_lc_fw_aux : write_poll_read_lc_fw_i2c)(hdcp); 760 760 761 - return success ? MOD_HDCP_STATUS_SUCCESS : MOD_HDCP_STATUS_DDC_FAILURE; 761 + return success ? MOD_HDCP_STATUS_SUCCESS : MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE; 762 762 } 763 763

+2

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c

··· 248 248 return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE"; 249 249 case MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE: 250 250 return "MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE"; 251 + case MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE: 252 + return "MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE"; 251 253 default: 252 254 return "MOD_HDCP_STATUS_UNKNOWN"; 253 255 }

+4 -6

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

··· 98 98 MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE, 99 99 MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE, 100 100 MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE, 101 + MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE, 101 102 }; 102 103 103 104 struct mod_hdcp_displayport { ··· 215 214 uint8_t force_type : 2; 216 215 uint8_t force_no_stored_km : 1; 217 216 uint8_t increase_h_prime_timeout: 1; 218 - uint8_t force_sw_locality_check : 1; 219 - uint8_t reserved : 2; 217 + uint8_t use_fw_locality_check : 1; 218 + uint8_t use_sw_locality_fallback: 1; 219 + uint8_t reserved : 1; 220 220 }; 221 221 222 222 struct mod_hdcp_link_adjustment { ··· 319 317 struct mod_hdcp_config { 320 318 struct mod_hdcp_psp psp; 321 319 struct mod_hdcp_ddc ddc; 322 - struct { 323 - uint8_t lc_enable_sw_fallback : 1; 324 - uint8_t reserved : 7; 325 - } debug; 326 320 uint8_t index; 327 321 }; 328 322

+6

drivers/gpu/drm/amd/include/kgd_pp_interface.h

··· 1820 1820 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 1821 1821 }; 1822 1822 1823 + struct amdgpu_partition_metrics_v1_1 { 1824 + struct metrics_table_header common_header; 1825 + int attr_count; 1826 + struct gpu_metrics_attr metrics_attrs[]; 1827 + }; 1828 + 1823 1829 #endif

+7 -18

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

··· 195 195 return ret; 196 196 } 197 197 198 - int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en) 199 - { 200 - int ret = 0; 201 - const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 202 - 203 - if (pp_funcs && pp_funcs->notify_rlc_state) { 204 - mutex_lock(&adev->pm.mutex); 205 - 206 - ret = pp_funcs->notify_rlc_state( 207 - adev->powerplay.pp_handle, 208 - en); 209 - 210 - mutex_unlock(&adev->pm.mutex); 211 - } 212 - 213 - return ret; 214 - } 215 - 216 198 int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) 217 199 { 218 200 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ··· 2121 2139 mutex_unlock(&adev->pm.mutex); 2122 2140 2123 2141 return ret; 2142 + } 2143 + 2144 + const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) 2145 + { 2146 + void *pp_handle = adev->powerplay.pp_handle; 2147 + 2148 + return smu_get_ras_smu_driver(pp_handle); 2124 2149 }

+2 -2

drivers/gpu/drm/amd/pm/amdgpu_pm.c

··· 4723 4723 ret = devm_device_add_group(adev->dev, 4724 4724 &amdgpu_pm_policy_attr_group); 4725 4725 if (ret) 4726 - goto err_out0; 4726 + goto err_out1; 4727 4727 } 4728 4728 4729 4729 if (amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_GPUBOARD)) { 4730 4730 ret = devm_device_add_group(adev->dev, 4731 4731 &amdgpu_board_attr_group); 4732 4732 if (ret) 4733 - goto err_out0; 4733 + goto err_out1; 4734 4734 if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, 4735 4735 (void *)&tmp) != -EOPNOTSUPP) { 4736 4736 sysfs_add_file_to_group(&adev->dev->kobj,

+1 -2

drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h

··· 424 424 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 425 425 enum pp_mp1_state mp1_state); 426 426 427 - int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en); 428 - 429 427 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev); 430 428 431 429 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); ··· 612 614 bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev); 613 615 bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, 614 616 enum smu_temp_metric_type type); 617 + const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev); 615 618 616 619 #endif

+1 -9

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

··· 2558 2558 if (enable) { 2559 2559 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2560 2560 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2561 - if (smc_result != PPSMC_Result_OK) { 2561 + if (smc_result != PPSMC_Result_OK) 2562 2562 ret = -EINVAL; 2563 - ni_pi->pc_enabled = false; 2564 - } else { 2565 - ni_pi->pc_enabled = true; 2566 - } 2567 2563 } 2568 2564 } else { 2569 2565 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2570 2566 if (smc_result != PPSMC_Result_OK) 2571 2567 ret = -EINVAL; 2572 - ni_pi->pc_enabled = false; 2573 2568 } 2574 2569 } 2575 2570 ··· 7504 7509 pi->pasi = CYPRESS_HASI_DFLT; 7505 7510 pi->vrc = SISLANDS_VRC_DFLT; 7506 7511 7507 - pi->gfx_clock_gating = true; 7508 - 7509 7512 eg_pi->sclk_deep_sleep = true; 7510 7513 si_pi->sclk_deep_sleep_above_low = false; 7511 7514 ··· 7514 7521 7515 7522 eg_pi->dynamic_ac_timing = true; 7516 7523 7517 - eg_pi->light_sleep = true; 7518 7524 #if defined(CONFIG_ACPI) 7519 7525 eg_pi->pcie_performance_request = 7520 7526 amdgpu_acpi_is_pcie_performance_request_supported(adev);

-557

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.h

··· 38 38 #define MC_ARB_DRAM_TIMING2_2 0xa00 39 39 #define MC_ARB_DRAM_TIMING2_3 0xa01 40 40 41 - #define MAX_NO_OF_MVDD_VALUES 2 42 - #define MAX_NO_VREG_STEPS 32 43 41 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 44 - #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32 45 - #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 46 42 #define RV770_ASI_DFLT 1000 47 43 #define CYPRESS_HASI_DFLT 400000 48 44 #define PCIE_PERF_REQ_PECI_GEN1 2 ··· 47 51 #define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 48 52 #define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 49 53 50 - #define SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE 16 51 - 52 - #define RV770_SMC_TABLE_ADDRESS 0xB000 53 - #define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3 54 - 55 54 #define SMC_STROBE_RATIO 0x0F 56 55 #define SMC_STROBE_ENABLE 0x10 57 56 ··· 54 63 #define SMC_MC_EDC_WR_FLAG 0x02 55 64 #define SMC_MC_RTT_ENABLE 0x04 56 65 #define SMC_MC_STUTTER_EN 0x08 57 - 58 - #define RV770_SMC_VOLTAGEMASK_VDDC 0 59 - #define RV770_SMC_VOLTAGEMASK_MVDD 1 60 - #define RV770_SMC_VOLTAGEMASK_VDDCI 2 61 - #define RV770_SMC_VOLTAGEMASK_MAX 4 62 - 63 - #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 64 - #define NISLANDS_SMC_STROBE_RATIO 0x0F 65 - #define NISLANDS_SMC_STROBE_ENABLE 0x10 66 - 67 - #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01 68 - #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02 69 - #define NISLANDS_SMC_MC_RTT_ENABLE 0x04 70 - #define NISLANDS_SMC_MC_STUTTER_EN 0x08 71 - 72 - #define MAX_NO_VREG_STEPS 32 73 - 74 - #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0 75 - #define NISLANDS_SMC_VOLTAGEMASK_MVDD 1 76 - #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2 77 - #define NISLANDS_SMC_VOLTAGEMASK_MAX 4 78 66 79 67 #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0 80 68 #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1 ··· 189 219 SISLANDS_CACCONFIG_MAX 190 220 }; 191 221 192 - enum si_power_level { 193 - SI_POWER_LEVEL_LOW = 0, 194 - SI_POWER_LEVEL_MEDIUM = 1, 195 - SI_POWER_LEVEL_HIGH = 2, 196 - SI_POWER_LEVEL_CTXSW = 3, 197 - }; 198 - 199 - enum si_td { 200 - SI_TD_AUTO, 201 - SI_TD_UP, 202 - SI_TD_DOWN, 203 - }; 204 - 205 - enum si_display_watermark { 206 - SI_DISPLAY_WATERMARK_LOW = 0, 207 - SI_DISPLAY_WATERMARK_HIGH = 1, 208 - }; 209 - 210 - enum si_display_gap 211 - { 212 - SI_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 213 - SI_PM_DISPLAY_GAP_VBLANK = 1, 214 - SI_PM_DISPLAY_GAP_WATERMARK = 2, 215 - SI_PM_DISPLAY_GAP_IGNORE = 3, 216 - }; 217 - 218 222 extern const struct amdgpu_ip_block_version si_smu_ip_block; 219 223 220 224 struct ni_leakage_coeffients ··· 202 258 u32 t_ref; 203 259 }; 204 260 205 - struct SMC_Evergreen_MCRegisterAddress 206 - { 207 - uint16_t s0; 208 - uint16_t s1; 209 - }; 210 - 211 - typedef struct SMC_Evergreen_MCRegisterAddress SMC_Evergreen_MCRegisterAddress; 212 - 213 - struct evergreen_mc_reg_entry { 214 - u32 mclk_max; 215 - u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 216 - }; 217 - 218 - struct evergreen_mc_reg_table { 219 - u8 last; 220 - u8 num_entries; 221 - u16 valid_flag; 222 - struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 223 - SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 224 - }; 225 - 226 - struct SMC_Evergreen_MCRegisterSet 227 - { 228 - uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 229 - }; 230 - 231 - typedef struct SMC_Evergreen_MCRegisterSet SMC_Evergreen_MCRegisterSet; 232 - 233 - struct SMC_Evergreen_MCRegisters 234 - { 235 - uint8_t last; 236 - uint8_t reserved[3]; 237 - SMC_Evergreen_MCRegisterAddress address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 238 - SMC_Evergreen_MCRegisterSet data[5]; 239 - }; 240 - 241 - typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters; 242 - 243 - struct SMC_NIslands_MCRegisterSet 244 - { 245 - uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 246 - }; 247 - 248 - typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet; 249 - 250 - struct ni_mc_reg_entry { 251 - u32 mclk_max; 252 - u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 253 - }; 254 - 255 261 struct SMC_NIslands_MCRegisterAddress 256 262 { 257 263 uint16_t s0; ··· 210 316 211 317 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; 212 318 213 - struct SMC_NIslands_MCRegisters 214 - { 215 - uint8_t last; 216 - uint8_t reserved[3]; 217 - SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 218 - SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 219 - }; 220 - 221 - typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters; 222 - 223 - struct evergreen_ulv_param { 224 - bool supported; 225 - struct rv7xx_pl *pl; 226 - }; 227 - 228 - struct evergreen_arb_registers { 229 - u32 mc_arb_dram_timing; 230 - u32 mc_arb_dram_timing2; 231 - u32 mc_arb_rfsh_rate; 232 - u32 mc_arb_burst_time; 233 - }; 234 - 235 - struct at { 236 - u32 rlp; 237 - u32 rmp; 238 - u32 lhp; 239 - u32 lmp; 240 - }; 241 - 242 - struct ni_clock_registers { 243 - u32 cg_spll_func_cntl; 244 - u32 cg_spll_func_cntl_2; 245 - u32 cg_spll_func_cntl_3; 246 - u32 cg_spll_func_cntl_4; 247 - u32 cg_spll_spread_spectrum; 248 - u32 cg_spll_spread_spectrum_2; 249 - u32 mclk_pwrmgt_cntl; 250 - u32 dll_cntl; 251 - u32 mpll_ad_func_cntl; 252 - u32 mpll_ad_func_cntl_2; 253 - u32 mpll_dq_func_cntl; 254 - u32 mpll_dq_func_cntl_2; 255 - u32 mpll_ss1; 256 - u32 mpll_ss2; 257 - }; 258 - 259 - struct RV770_SMC_SCLK_VALUE 260 - { 261 - uint32_t vCG_SPLL_FUNC_CNTL; 262 - uint32_t vCG_SPLL_FUNC_CNTL_2; 263 - uint32_t vCG_SPLL_FUNC_CNTL_3; 264 - uint32_t vCG_SPLL_SPREAD_SPECTRUM; 265 - uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 266 - uint32_t sclk_value; 267 - }; 268 - 269 - typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE; 270 - 271 - struct RV770_SMC_MCLK_VALUE 272 - { 273 - uint32_t vMPLL_AD_FUNC_CNTL; 274 - uint32_t vMPLL_AD_FUNC_CNTL_2; 275 - uint32_t vMPLL_DQ_FUNC_CNTL; 276 - uint32_t vMPLL_DQ_FUNC_CNTL_2; 277 - uint32_t vMCLK_PWRMGT_CNTL; 278 - uint32_t vDLL_CNTL; 279 - uint32_t vMPLL_SS; 280 - uint32_t vMPLL_SS2; 281 - uint32_t mclk_value; 282 - }; 283 - 284 - typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE; 285 - 286 - 287 - struct RV730_SMC_MCLK_VALUE 288 - { 289 - uint32_t vMCLK_PWRMGT_CNTL; 290 - uint32_t vDLL_CNTL; 291 - uint32_t vMPLL_FUNC_CNTL; 292 - uint32_t vMPLL_FUNC_CNTL2; 293 - uint32_t vMPLL_FUNC_CNTL3; 294 - uint32_t vMPLL_SS; 295 - uint32_t vMPLL_SS2; 296 - uint32_t mclk_value; 297 - }; 298 - 299 - typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE; 300 - 301 - struct RV770_SMC_VOLTAGE_VALUE 302 - { 303 - uint16_t value; 304 - uint8_t index; 305 - uint8_t padding; 306 - }; 307 - 308 - typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE; 309 - 310 - union RV7XX_SMC_MCLK_VALUE 311 - { 312 - RV770_SMC_MCLK_VALUE mclk770; 313 - RV730_SMC_MCLK_VALUE mclk730; 314 - }; 315 - 316 - typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE; 317 - 318 - struct RV770_SMC_HW_PERFORMANCE_LEVEL 319 - { 320 - uint8_t arbValue; 321 - union{ 322 - uint8_t seqValue; 323 - uint8_t ACIndex; 324 - }; 325 - uint8_t displayWatermark; 326 - uint8_t gen2PCIE; 327 - uint8_t gen2XSP; 328 - uint8_t backbias; 329 - uint8_t strobeMode; 330 - uint8_t mcFlags; 331 - uint32_t aT; 332 - uint32_t bSP; 333 - RV770_SMC_SCLK_VALUE sclk; 334 - RV7XX_SMC_MCLK_VALUE mclk; 335 - RV770_SMC_VOLTAGE_VALUE vddc; 336 - RV770_SMC_VOLTAGE_VALUE mvdd; 337 - RV770_SMC_VOLTAGE_VALUE vddci; 338 - uint8_t reserved1; 339 - uint8_t reserved2; 340 - uint8_t stateFlags; 341 - uint8_t padding; 342 - }; 343 - 344 - typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL; 345 - 346 - struct RV770_SMC_SWSTATE 347 - { 348 - uint8_t flags; 349 - uint8_t padding1; 350 - uint8_t padding2; 351 - uint8_t padding3; 352 - RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 353 - }; 354 - 355 - typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE; 356 - 357 - struct RV770_SMC_VOLTAGEMASKTABLE 358 - { 359 - uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX]; 360 - uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX]; 361 - }; 362 - 363 - typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE; 364 - 365 - struct RV770_SMC_STATETABLE 366 - { 367 - uint8_t thermalProtectType; 368 - uint8_t systemFlags; 369 - uint8_t maxVDDCIndexInPPTable; 370 - uint8_t extraFlags; 371 - uint8_t highSMIO[MAX_NO_VREG_STEPS]; 372 - uint32_t lowSMIO[MAX_NO_VREG_STEPS]; 373 - RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable; 374 - RV770_SMC_SWSTATE initialState; 375 - RV770_SMC_SWSTATE ACPIState; 376 - RV770_SMC_SWSTATE driverState; 377 - RV770_SMC_SWSTATE ULVState; 378 - }; 379 - 380 - typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE; 381 - 382 - struct vddc_table_entry { 383 - u16 vddc; 384 - u8 vddc_index; 385 - u8 high_smio; 386 - u32 low_smio; 387 - }; 388 - 389 - struct rv770_clock_registers { 390 - u32 cg_spll_func_cntl; 391 - u32 cg_spll_func_cntl_2; 392 - u32 cg_spll_func_cntl_3; 393 - u32 cg_spll_spread_spectrum; 394 - u32 cg_spll_spread_spectrum_2; 395 - u32 mpll_ad_func_cntl; 396 - u32 mpll_ad_func_cntl_2; 397 - u32 mpll_dq_func_cntl; 398 - u32 mpll_dq_func_cntl_2; 399 - u32 mclk_pwrmgt_cntl; 400 - u32 dll_cntl; 401 - u32 mpll_ss1; 402 - u32 mpll_ss2; 403 - }; 404 - 405 - struct rv730_clock_registers { 406 - u32 cg_spll_func_cntl; 407 - u32 cg_spll_func_cntl_2; 408 - u32 cg_spll_func_cntl_3; 409 - u32 cg_spll_spread_spectrum; 410 - u32 cg_spll_spread_spectrum_2; 411 - u32 mclk_pwrmgt_cntl; 412 - u32 dll_cntl; 413 - u32 mpll_func_cntl; 414 - u32 mpll_func_cntl2; 415 - u32 mpll_func_cntl3; 416 - u32 mpll_ss; 417 - u32 mpll_ss2; 418 - }; 419 - 420 - union r7xx_clock_registers { 421 - struct rv770_clock_registers rv770; 422 - struct rv730_clock_registers rv730; 423 - }; 424 - 425 319 struct rv7xx_power_info { 426 320 /* flags */ 427 - bool mem_gddr5; 428 - bool pcie_gen2; 429 - bool dynamic_pcie_gen2; 430 - bool acpi_pcie_gen2; 431 - bool boot_in_gen2; 432 321 bool voltage_control; /* vddc */ 433 322 bool mvdd_control; 434 323 bool sclk_ss; 435 324 bool mclk_ss; 436 325 bool dynamic_ss; 437 - bool gfx_clock_gating; 438 - bool mg_clock_gating; 439 - bool mgcgtssm; 440 - bool power_gating; 441 326 bool thermal_protection; 442 - bool display_gap; 443 - bool dcodt; 444 - bool ulps; 445 - /* registers */ 446 - union r7xx_clock_registers clk_regs; 447 - u32 s0_vid_lower_smio_cntl; 448 327 /* voltage */ 449 - u32 vddc_mask_low; 450 - u32 mvdd_mask_low; 451 328 u32 mvdd_split_frequency; 452 - u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES]; 453 329 u16 max_vddc; 454 330 u16 max_vddc_in_table; 455 331 u16 min_vddc_in_table; 456 - struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; 457 - u8 valid_vddc_entries; 458 - /* dc odt */ 459 - u32 mclk_odt_threshold; 460 - u8 odt_value_0[2]; 461 - u8 odt_value_1[2]; 462 332 /* stored values */ 463 - u32 boot_sclk; 464 333 u16 acpi_vddc; 465 334 u32 ref_div; 466 335 u32 active_auto_throttle_sources; ··· 239 582 u32 asi; 240 583 u32 pasi; 241 584 u32 vrc; 242 - u32 restricted_levels; 243 - u32 rlp; 244 - u32 rmp; 245 - u32 lhp; 246 - u32 lmp; 247 - /* smc offsets */ 248 - u16 state_table_start; 249 - u16 soft_regs_start; 250 - u16 sram_end; 251 - /* scratch structs */ 252 - RV770_SMC_STATETABLE smc_statetable; 253 585 }; 254 586 255 587 enum si_pcie_gen { ··· 257 611 enum si_pcie_gen pcie_gen; /* si+ only */ 258 612 }; 259 613 260 - struct rv7xx_ps { 261 - struct rv7xx_pl high; 262 - struct rv7xx_pl medium; 263 - struct rv7xx_pl low; 264 - bool dc_compatible; 265 - }; 266 - 267 614 struct si_ps { 268 615 u16 performance_level_count; 269 616 bool dc_compatible; 270 617 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 271 - }; 272 - 273 - struct ni_mc_reg_table { 274 - u8 last; 275 - u8 num_entries; 276 - u16 valid_flag; 277 - struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 278 - SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 279 - }; 280 - 281 - struct ni_cac_data 282 - { 283 - struct ni_leakage_coeffients leakage_coefficients; 284 - u32 i_leakage; 285 - s32 leakage_minimum_temperature; 286 - u32 pwr_const; 287 - u32 dc_cac_value; 288 - u32 bif_cac_value; 289 - u32 lkge_pwr; 290 - u8 mc_wr_weight; 291 - u8 mc_rd_weight; 292 - u8 allow_ovrflw; 293 - u8 num_win_tdp; 294 - u8 l2num_win_tdp; 295 - u8 lts_truncate_n; 296 618 }; 297 619 298 620 struct evergreen_power_info { ··· 271 657 bool dynamic_ac_timing; 272 658 bool abm; 273 659 bool mcls; 274 - bool light_sleep; 275 - bool memory_transition; 276 660 bool pcie_performance_request; 277 - bool pcie_performance_request_registered; 278 661 bool sclk_deep_sleep; 279 - bool dll_default_on; 280 - bool ls_clock_gating; 281 662 bool smu_uvd_hs; 282 663 bool uvd_enabled; 283 664 /* stored values */ 284 665 u16 acpi_vddci; 285 - u8 mvdd_high_index; 286 - u8 mvdd_low_index; 287 666 u32 mclk_edc_wr_enable_threshold; 288 - struct evergreen_mc_reg_table mc_reg_table; 289 667 struct atom_voltage_table vddc_voltage_table; 290 668 struct atom_voltage_table vddci_voltage_table; 291 - struct evergreen_arb_registers bootup_arb_registers; 292 - struct evergreen_ulv_param ulv; 293 - struct at ats[2]; 294 - /* smc offsets */ 295 - u16 mc_reg_table_start; 296 669 struct amdgpu_ps current_rps; 297 - struct rv7xx_ps current_ps; 298 670 struct amdgpu_ps requested_rps; 299 - struct rv7xx_ps requested_ps; 300 671 }; 301 - 302 - struct PP_NIslands_Dpm2PerfLevel 303 - { 304 - uint8_t MaxPS; 305 - uint8_t TgtAct; 306 - uint8_t MaxPS_StepInc; 307 - uint8_t MaxPS_StepDec; 308 - uint8_t PSST; 309 - uint8_t NearTDPDec; 310 - uint8_t AboveSafeInc; 311 - uint8_t BelowSafeInc; 312 - uint8_t PSDeltaLimit; 313 - uint8_t PSDeltaWin; 314 - uint8_t Reserved[6]; 315 - }; 316 - 317 - typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel; 318 - 319 - struct PP_NIslands_DPM2Parameters 320 - { 321 - uint32_t TDPLimit; 322 - uint32_t NearTDPLimit; 323 - uint32_t SafePowerLimit; 324 - uint32_t PowerBoostLimit; 325 - }; 326 - typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters; 327 - 328 - struct NISLANDS_SMC_SCLK_VALUE 329 - { 330 - uint32_t vCG_SPLL_FUNC_CNTL; 331 - uint32_t vCG_SPLL_FUNC_CNTL_2; 332 - uint32_t vCG_SPLL_FUNC_CNTL_3; 333 - uint32_t vCG_SPLL_FUNC_CNTL_4; 334 - uint32_t vCG_SPLL_SPREAD_SPECTRUM; 335 - uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 336 - uint32_t sclk_value; 337 - }; 338 - 339 - typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE; 340 - 341 - struct NISLANDS_SMC_MCLK_VALUE 342 - { 343 - uint32_t vMPLL_FUNC_CNTL; 344 - uint32_t vMPLL_FUNC_CNTL_1; 345 - uint32_t vMPLL_FUNC_CNTL_2; 346 - uint32_t vMPLL_AD_FUNC_CNTL; 347 - uint32_t vMPLL_AD_FUNC_CNTL_2; 348 - uint32_t vMPLL_DQ_FUNC_CNTL; 349 - uint32_t vMPLL_DQ_FUNC_CNTL_2; 350 - uint32_t vMCLK_PWRMGT_CNTL; 351 - uint32_t vDLL_CNTL; 352 - uint32_t vMPLL_SS; 353 - uint32_t vMPLL_SS2; 354 - uint32_t mclk_value; 355 - }; 356 - 357 - typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE; 358 - 359 - struct NISLANDS_SMC_VOLTAGE_VALUE 360 - { 361 - uint16_t value; 362 - uint8_t index; 363 - uint8_t padding; 364 - }; 365 - 366 - typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE; 367 - 368 - struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL 369 - { 370 - uint8_t arbValue; 371 - uint8_t ACIndex; 372 - uint8_t displayWatermark; 373 - uint8_t gen2PCIE; 374 - uint8_t reserved1; 375 - uint8_t reserved2; 376 - uint8_t strobeMode; 377 - uint8_t mcFlags; 378 - uint32_t aT; 379 - uint32_t bSP; 380 - NISLANDS_SMC_SCLK_VALUE sclk; 381 - NISLANDS_SMC_MCLK_VALUE mclk; 382 - NISLANDS_SMC_VOLTAGE_VALUE vddc; 383 - NISLANDS_SMC_VOLTAGE_VALUE mvdd; 384 - NISLANDS_SMC_VOLTAGE_VALUE vddci; 385 - NISLANDS_SMC_VOLTAGE_VALUE std_vddc; 386 - uint32_t powergate_en; 387 - uint8_t hUp; 388 - uint8_t hDown; 389 - uint8_t stateFlags; 390 - uint8_t arbRefreshState; 391 - uint32_t SQPowerThrottle; 392 - uint32_t SQPowerThrottle_2; 393 - uint32_t reserved[2]; 394 - PP_NIslands_Dpm2PerfLevel dpm2; 395 - }; 396 - 397 - typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL; 398 - 399 - struct NISLANDS_SMC_SWSTATE 400 - { 401 - uint8_t flags; 402 - uint8_t levelCount; 403 - uint8_t padding2; 404 - uint8_t padding3; 405 - NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[]; 406 - }; 407 - 408 - typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE; 409 - 410 - struct NISLANDS_SMC_VOLTAGEMASKTABLE 411 - { 412 - uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 413 - uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 414 - }; 415 - 416 - typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; 417 - 418 - #define NISLANDS_MAX_NO_VREG_STEPS 32 419 - 420 - struct NISLANDS_SMC_STATETABLE 421 - { 422 - uint8_t thermalProtectType; 423 - uint8_t systemFlags; 424 - uint8_t maxVDDCIndexInPPTable; 425 - uint8_t extraFlags; 426 - uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 427 - uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 428 - NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 429 - PP_NIslands_DPM2Parameters dpm2Params; 430 - NISLANDS_SMC_SWSTATE initialState; 431 - NISLANDS_SMC_SWSTATE ACPIState; 432 - NISLANDS_SMC_SWSTATE ULVState; 433 - NISLANDS_SMC_SWSTATE driverState; 434 - NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; 435 - }; 436 - 437 - typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE; 438 672 439 673 struct ni_power_info { 440 674 /* must be first! */ 441 675 struct evergreen_power_info eg; 442 - struct ni_clock_registers clock_registers; 443 - struct ni_mc_reg_table mc_reg_table; 444 676 u32 mclk_rtt_mode_threshold; 445 677 /* flags */ 446 - bool use_power_boost_limit; 447 678 bool support_cac_long_term_average; 448 679 bool cac_enabled; 449 680 bool cac_configuration_required; 450 681 bool driver_calculate_cac_leakage; 451 - bool pc_enabled; 452 682 bool enable_power_containment; 453 683 bool enable_cac; 454 684 bool enable_sq_ramping; 455 - /* smc offsets */ 456 - u16 arb_table_start; 457 - u16 fan_table_start; 458 - u16 cac_table_start; 459 - u16 spll_table_start; 460 - /* CAC stuff */ 461 - struct ni_cac_data cac_data; 462 - u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS]; 463 - const struct ni_cac_weights *cac_weights; 464 - u8 lta_window_size; 465 - u8 lts_truncate; 466 685 struct si_ps current_ps; 467 686 struct si_ps requested_ps; 468 - /* scratch structs */ 469 - SMC_NIslands_MCRegisters smc_mc_reg_table; 470 - NISLANDS_SMC_STATETABLE smc_statetable; 471 687 }; 472 688 473 689 struct si_cac_config_reg ··· 395 951 u16 count; 396 952 struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT]; 397 953 }; 398 - 399 954 400 955 struct si_ulv_param { 401 956 bool supported;

+2 -2

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

··· 139 139 priv->smu_tables.entry[table_id].table_id, 140 140 NULL); 141 141 142 - amdgpu_asic_invalidate_hdp(adev, NULL); 142 + amdgpu_hdp_invalidate(adev, NULL); 143 143 144 144 memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table, 145 145 priv->smu_tables.entry[table_id].size); ··· 164 164 memcpy(priv->smu_tables.entry[table_id].table, table, 165 165 priv->smu_tables.entry[table_id].size); 166 166 167 - amdgpu_asic_flush_hdp(adev, NULL); 167 + amdgpu_hdp_flush(adev, NULL); 168 168 169 169 smum_send_msg_to_smc_with_parameter(hwmgr, 170 170 PPSMC_MSG_SetDriverDramAddrHigh,

+2 -2

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c

··· 60 60 priv->smu_tables.entry[table_id].table_id, 61 61 NULL); 62 62 63 - amdgpu_asic_invalidate_hdp(adev, NULL); 63 + amdgpu_hdp_invalidate(adev, NULL); 64 64 65 65 memcpy(table, priv->smu_tables.entry[table_id].table, 66 66 priv->smu_tables.entry[table_id].size); ··· 90 90 memcpy(priv->smu_tables.entry[table_id].table, table, 91 91 priv->smu_tables.entry[table_id].size); 92 92 93 - amdgpu_asic_flush_hdp(adev, NULL); 93 + amdgpu_hdp_flush(adev, NULL); 94 94 95 95 smum_send_msg_to_smc_with_parameter(hwmgr, 96 96 PPSMC_MSG_SetDriverDramAddrHigh,

+2 -2

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c

··· 68 68 "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", 69 69 return -EINVAL); 70 70 71 - amdgpu_asic_invalidate_hdp(adev, NULL); 71 + amdgpu_hdp_invalidate(adev, NULL); 72 72 73 73 memcpy(table, priv->smu_tables.entry[table_id].table, 74 74 priv->smu_tables.entry[table_id].size); ··· 98 98 memcpy(priv->smu_tables.entry[table_id].table, table, 99 99 priv->smu_tables.entry[table_id].size); 100 100 101 - amdgpu_asic_flush_hdp(adev, NULL); 101 + amdgpu_hdp_flush(adev, NULL); 102 102 103 103 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 104 104 PPSMC_MSG_SetDriverDramAddrHigh,

+4 -4

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

··· 192 192 "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", 193 193 return ret); 194 194 195 - amdgpu_asic_invalidate_hdp(adev, NULL); 195 + amdgpu_hdp_invalidate(adev, NULL); 196 196 197 197 memcpy(table, priv->smu_tables.entry[table_id].table, 198 198 priv->smu_tables.entry[table_id].size); ··· 223 223 memcpy(priv->smu_tables.entry[table_id].table, table, 224 224 priv->smu_tables.entry[table_id].size); 225 225 226 - amdgpu_asic_flush_hdp(adev, NULL); 226 + amdgpu_hdp_flush(adev, NULL); 227 227 228 228 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 229 229 PPSMC_MSG_SetDriverDramAddrHigh, ··· 256 256 memcpy(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table, table, 257 257 priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size); 258 258 259 - amdgpu_asic_flush_hdp(adev, NULL); 259 + amdgpu_hdp_flush(adev, NULL); 260 260 261 261 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 262 262 PPSMC_MSG_SetDriverDramAddrHigh, ··· 306 306 "[GetActivityMonitor] Attempt to Transfer Table From SMU Failed!", 307 307 return ret); 308 308 309 - amdgpu_asic_invalidate_hdp(adev, NULL); 309 + amdgpu_hdp_invalidate(adev, NULL); 310 310 311 311 memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table, 312 312 priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);

+17

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

··· 2054 2054 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2055 2055 return 0; 2056 2056 2057 + /* vangogh s0ix */ 2058 + if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 2059 + amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && 2060 + adev->in_s0ix) 2061 + return 0; 2062 + 2057 2063 /* 2058 2064 * For gpu reset, runpm and hibernation through BACO, 2059 2065 * BACO feature has to be kept enabled. ··· 2802 2796 .rev = 0, 2803 2797 .funcs = &smu_ip_funcs, 2804 2798 }; 2799 + 2800 + const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle) 2801 + { 2802 + struct smu_context *smu = (struct smu_context *)handle; 2803 + const struct ras_smu_drv *tmp = NULL; 2804 + int ret; 2805 + 2806 + ret = smu_get_ras_smu_drv(smu, &tmp); 2807 + 2808 + return ret ? NULL : tmp; 2809 + } 2805 2810 2806 2811 static int smu_load_microcode(void *handle) 2807 2812 {

+7

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

··· 1531 1531 int (*ras_send_msg)(struct smu_context *smu, 1532 1532 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1533 1533 1534 + 1535 + /** 1536 + * @get_ras_smu_drv: Get RAS smu driver interface 1537 + * Return: ras_smu_drv * 1538 + */ 1539 + int (*get_ras_smu_drv)(struct smu_context *smu, const struct ras_smu_drv **ras_smu_drv); 1534 1540 }; 1535 1541 1536 1542 typedef enum { ··· 1801 1795 int level); 1802 1796 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 1803 1797 enum pp_pm_policy p_type, char *sysbuf); 1798 + const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle); 1804 1799 1805 1800 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 1806 1801 uint32_t param, uint32_t *readarg);

+1 -1

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

··· 87 87 /*37*/ FEATURE_DVO = 37, 88 88 /*38*/ FEATURE_XVMINORPSM_CLKSTOP_DS = 38, 89 89 /*39*/ FEATURE_GLOBAL_DPM = 39, 90 - /*40*/ FEATURE_NODE_POWER_MANAGER = 40, 90 + /*40*/ FEATURE_HROM_EN = 40, 91 91 92 92 /*41*/ NUM_FEATURES = 41 93 93 } FEATURE_LIST_e;

+6 -10

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h

··· 105 105 #define PPSMC_MSG_UpdatePccWaitDecMaxStr 0x4C 106 106 #define PPSMC_MSG_ResetSDMA 0x4D 107 107 #define PPSMC_MSG_GetRasTableVersion 0x4E 108 - #define PPSMC_MSG_GetRmaStatus 0x4F 109 - #define PPSMC_MSG_GetErrorCount 0x50 110 - #define PPSMC_MSG_GetBadPageCount 0x51 111 - #define PPSMC_MSG_GetBadPageInfo 0x52 112 - #define PPSMC_MSG_GetBadPagePaAddrLoHi 0x53 113 - #define PPSMC_MSG_SetTimestampLoHi 0x54 114 - #define PPSMC_MSG_GetTimestampLoHi 0x55 115 - #define PPSMC_MSG_GetRasPolicy 0x56 116 - #define PPSMC_MSG_DumpErrorRecord 0x57 108 + #define PPSMC_MSG_GetBadPageCount 0x50 109 + #define PPSMC_MSG_GetBadPageMcaAddress 0x51 110 + #define PPSMC_MSG_SetTimestamp 0x53 111 + #define PPSMC_MSG_SetTimestampHi 0x54 112 + #define PPSMC_MSG_GetTimestamp 0x55 113 + #define PPSMC_MSG_GetBadPageIpIdLoHi 0x57 117 114 #define PPSMC_MSG_EraseRasTable 0x58 118 115 #define PPSMC_MSG_GetStaticMetricsTable 0x59 119 116 #define PPSMC_MSG_ResetVfArbitersByIndex 0x5A 120 - #define PPSMC_MSG_GetBadPageSeverity 0x5B 121 117 #define PPSMC_MSG_GetSystemMetricsTable 0x5C 122 118 #define PPSMC_MSG_GetSystemMetricsVersion 0x5D 123 119 #define PPSMC_MSG_ResetVCN 0x5E

+10 -2

drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h

··· 279 279 __SMU_DUMMY_MAP(ResetSDMA), \ 280 280 __SMU_DUMMY_MAP(ResetVCN), \ 281 281 __SMU_DUMMY_MAP(GetStaticMetricsTable), \ 282 - __SMU_DUMMY_MAP(GetSystemMetricsTable), 282 + __SMU_DUMMY_MAP(GetSystemMetricsTable), \ 283 + __SMU_DUMMY_MAP(GetRASTableVersion), \ 284 + __SMU_DUMMY_MAP(GetBadPageCount), \ 285 + __SMU_DUMMY_MAP(GetBadPageMcaAddr), \ 286 + __SMU_DUMMY_MAP(SetTimestamp), \ 287 + __SMU_DUMMY_MAP(GetTimestamp), \ 288 + __SMU_DUMMY_MAP(GetBadPageIpid), \ 289 + __SMU_DUMMY_MAP(EraseRasTable), 283 290 284 291 #undef __SMU_DUMMY_MAP 285 292 #define __SMU_DUMMY_MAP(type) SMU_MSG_##type ··· 465 458 __SMU_DUMMY_MAP(GFX_EDC_XVMIN), \ 466 459 __SMU_DUMMY_MAP(GFX_DIDT_XVMIN), \ 467 460 __SMU_DUMMY_MAP(FAN_ABNORMAL), \ 468 - __SMU_DUMMY_MAP(PIT), 461 + __SMU_DUMMY_MAP(PIT), \ 462 + __SMU_DUMMY_MAP(HROM_EN), 469 463 470 464 #undef __SMU_DUMMY_MAP 471 465 #define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

··· 2889 2889 dummy_table += 0x1000; 2890 2890 } 2891 2891 2892 - amdgpu_asic_flush_hdp(smu->adev, NULL); 2892 + amdgpu_hdp_flush(smu->adev, NULL); 2893 2893 2894 2894 ret = smu_cmn_send_smc_msg_with_param(smu, 2895 2895 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,

+3

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

··· 2219 2219 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 2220 2220 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2221 2221 2222 + if (adev->in_s0ix) 2223 + return 0; 2224 + 2222 2225 /* allow message will be sent after enable message on Vangogh*/ 2223 2226 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 2224 2227 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

+182 -55

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

··· 34 34 #include "amdgpu_fru_eeprom.h" 35 35 #include <linux/pci.h> 36 36 #include "smu_cmn.h" 37 + #include "amdgpu_ras.h" 37 38 38 39 #undef MP1_Public 39 40 #undef smnMP1_FIRMWARE_FLAGS ··· 59 58 60 59 #define NUM_JPEG_RINGS_FW 10 61 60 #define NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics) \ 62 - (ARRAY_SIZE(gpu_metrics->xcp_stats[0].jpeg_busy) / 4) 61 + (ARRAY_SIZE(gpu_metrics->jpeg_busy) / 4) 63 62 64 63 const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[SMU_FEATURE_COUNT] = { 65 64 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION), ··· 82 81 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK), 83 82 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK), 84 83 SMU_13_0_12_FEA_MAP(SMU_FEATURE_PIT_BIT, FEATURE_PIT), 84 + SMU_13_0_12_FEA_MAP(SMU_FEATURE_HROM_EN_BIT, FEATURE_HROM_EN), 85 85 }; 86 86 87 87 const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = { ··· 141 139 MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0), 142 140 MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), 143 141 MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 1), 142 + MSG_MAP(GetRASTableVersion, PPSMC_MSG_GetRasTableVersion, 0), 143 + MSG_MAP(GetBadPageCount, PPSMC_MSG_GetBadPageCount, 0), 144 + MSG_MAP(GetBadPageMcaAddr, PPSMC_MSG_GetBadPageMcaAddress, 0), 145 + MSG_MAP(SetTimestamp, PPSMC_MSG_SetTimestamp, 0), 146 + MSG_MAP(GetTimestamp, PPSMC_MSG_GetTimestamp, 0), 147 + MSG_MAP(GetBadPageIpid, PPSMC_MSG_GetBadPageIpIdLoHi, 0), 148 + MSG_MAP(EraseRasTable, PPSMC_MSG_EraseRasTable, 0), 144 149 }; 145 150 146 151 int smu_v13_0_12_tables_init(struct smu_context *smu) ··· 458 449 return ret; 459 450 } 460 451 461 - amdgpu_asic_invalidate_hdp(smu->adev, NULL); 452 + amdgpu_hdp_invalidate(smu->adev, NULL); 462 453 smu_table_cache_update_time(sys_table, jiffies); 463 454 memcpy(sys_table->cache.buffer, table->cpu_addr, 464 455 smu_v13_0_12_get_system_metrics_size()); ··· 728 719 ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp *xcp, void *table, void *smu_metrics) 729 720 { 730 721 const u8 num_jpeg_rings = NUM_JPEG_RINGS_FW; 731 - struct amdgpu_partition_metrics_v1_0 *xcp_metrics; 722 + struct smu_v13_0_6_partition_metrics *xcp_metrics; 732 723 struct amdgpu_device *adev = smu->adev; 733 724 MetricsTable_t *metrics; 734 725 int inst, j, k, idx; 735 726 u32 inst_mask; 736 727 737 728 metrics = (MetricsTable_t *)smu_metrics; 738 - xcp_metrics = (struct amdgpu_partition_metrics_v1_0 *) table; 739 - smu_cmn_init_partition_metrics(xcp_metrics, 1, 0); 729 + xcp_metrics = (struct smu_v13_0_6_partition_metrics *)table; 740 730 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 741 731 idx = 0; 742 732 for_each_inst(k, inst_mask) { ··· 780 772 return sizeof(*xcp_metrics); 781 773 } 782 774 783 - ssize_t smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, void *smu_metrics) 775 + void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, 776 + void *smu_metrics, 777 + struct smu_v13_0_6_gpu_metrics *gpu_metrics) 784 778 { 785 - struct smu_table_context *smu_table = &smu->smu_table; 786 - struct gpu_metrics_v1_8 *gpu_metrics = 787 - (struct gpu_metrics_v1_8 *)smu_table->gpu_metrics_table; 788 - int ret = 0, xcc_id, inst, i, j, k, idx; 789 779 struct amdgpu_device *adev = smu->adev; 780 + int ret = 0, xcc_id, inst, i, j; 790 781 u8 num_jpeg_rings_gpu_metrics; 791 782 MetricsTable_t *metrics; 792 - struct amdgpu_xcp *xcp; 793 - u32 inst_mask; 794 783 795 784 metrics = (MetricsTable_t *)smu_metrics; 796 - 797 - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 8); 798 785 799 786 gpu_metrics->temperature_hotspot = 800 787 SMUQ10_ROUND(metrics->MaxSocketTemperature); ··· 880 877 gpu_metrics->xgmi_link_status[j] = ret; 881 878 } 882 879 883 - gpu_metrics->num_partition = adev->xcp_mgr->num_xcps; 884 - 885 880 num_jpeg_rings_gpu_metrics = NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics); 886 - for_each_xcp(adev->xcp_mgr, xcp, i) { 887 - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 888 - idx = 0; 889 - for_each_inst(k, inst_mask) { 890 - /* Both JPEG and VCN has same instances */ 891 - inst = GET_INST(VCN, k); 881 + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 882 + inst = GET_INST(VCN, i); 892 883 893 - for (j = 0; j < num_jpeg_rings_gpu_metrics; ++j) { 894 - gpu_metrics->xcp_stats[i].jpeg_busy 895 - [(idx * num_jpeg_rings_gpu_metrics) + j] = 896 - SMUQ10_ROUND(metrics->JpegBusy 897 - [(inst * NUM_JPEG_RINGS_FW) + j]); 898 - } 899 - gpu_metrics->xcp_stats[i].vcn_busy[idx] = 900 - SMUQ10_ROUND(metrics->VcnBusy[inst]); 901 - idx++; 884 + for (j = 0; j < num_jpeg_rings_gpu_metrics; ++j) { 885 + gpu_metrics->jpeg_busy[(i * num_jpeg_rings_gpu_metrics) + 886 + j] = 887 + SMUQ10_ROUND( 888 + metrics->JpegBusy[(inst * 889 + NUM_JPEG_RINGS_FW) + 890 + j]); 902 891 } 892 + gpu_metrics->vcn_busy[i] = SMUQ10_ROUND(metrics->VcnBusy[inst]); 893 + } 903 894 904 - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 905 - idx = 0; 906 - for_each_inst(k, inst_mask) { 907 - inst = GET_INST(GC, k); 908 - gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] = 909 - SMUQ10_ROUND(metrics->GfxBusy[inst]); 910 - gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] = 911 - SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); 912 - if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) { 913 - gpu_metrics->xcp_stats[i].gfx_below_host_limit_ppt_acc[idx] = 914 - SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]); 915 - gpu_metrics->xcp_stats[i].gfx_below_host_limit_thm_acc[idx] = 916 - SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]); 917 - gpu_metrics->xcp_stats[i].gfx_low_utilization_acc[idx] = 918 - SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]); 919 - gpu_metrics->xcp_stats[i].gfx_below_host_limit_total_acc[idx] = 920 - SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]); 921 - } 922 - idx++; 923 - } 895 + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { 896 + inst = GET_INST(GC, i); 897 + gpu_metrics->gfx_busy_inst[i] = 898 + SMUQ10_ROUND(metrics->GfxBusy[inst]); 899 + gpu_metrics->gfx_busy_acc[i] = 900 + SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); 901 + if (smu_v13_0_6_cap_supported(smu, 902 + SMU_CAP(HST_LIMIT_METRICS))) { 903 + gpu_metrics 904 + ->gfx_below_host_limit_ppt_acc[i] = SMUQ10_ROUND( 905 + metrics->GfxclkBelowHostLimitPptAcc[inst]); 906 + gpu_metrics 907 + ->gfx_below_host_limit_thm_acc[i] = SMUQ10_ROUND( 908 + metrics->GfxclkBelowHostLimitThmAcc[inst]); 909 + gpu_metrics->gfx_low_utilization_acc[i] = SMUQ10_ROUND( 910 + metrics->GfxclkLowUtilizationAcc[inst]); 911 + gpu_metrics->gfx_below_host_limit_total_acc 912 + [i] = SMUQ10_ROUND( 913 + metrics->GfxclkBelowHostLimitTotalAcc[inst]); 914 + }; 924 915 } 925 916 926 917 gpu_metrics->xgmi_link_width = metrics->XgmiWidth; 927 918 gpu_metrics->xgmi_link_speed = metrics->XgmiBitrate; 928 919 929 920 gpu_metrics->firmware_timestamp = metrics->Timestamp; 930 - 931 - *table = (void *)gpu_metrics; 932 - 933 - return sizeof(*gpu_metrics); 934 921 } 935 922 936 923 const struct smu_temp_funcs smu_v13_0_12_temp_funcs = { 937 924 .temp_metrics_is_supported = smu_v13_0_12_is_temp_metrics_supported, 938 925 .get_temp_metrics = smu_v13_0_12_get_temp_metrics, 926 + }; 927 + 928 + static int smu_v13_0_12_get_ras_table_version(struct amdgpu_device *adev, 929 + uint32_t *table_version) 930 + { 931 + struct smu_context *smu = adev->powerplay.pp_handle; 932 + 933 + return smu_cmn_send_smc_msg_with_param(smu, 934 + SMU_MSG_GetRASTableVersion, 0, table_version); 935 + } 936 + 937 + static int smu_v13_0_12_get_badpage_count(struct amdgpu_device *adev, uint32_t *count, 938 + uint32_t timeout) 939 + { 940 + struct smu_context *smu = adev->powerplay.pp_handle; 941 + uint64_t end, now; 942 + int ret = 0; 943 + 944 + now = (uint64_t)ktime_to_ms(ktime_get()); 945 + end = now + timeout; 946 + do { 947 + ret = smu_cmn_send_smc_msg_with_param(smu, 948 + SMU_MSG_GetBadPageCount, 0, count); 949 + /* eeprom is not ready */ 950 + if (ret != -EBUSY) 951 + return ret; 952 + mdelay(10); 953 + now = (uint64_t)ktime_to_ms(ktime_get()); 954 + } while (now < end); 955 + 956 + return ret; 957 + } 958 + 959 + static int smu_v13_0_12_set_timestamp(struct amdgpu_device *adev, uint64_t timestamp) 960 + { 961 + struct smu_context *smu = adev->powerplay.pp_handle; 962 + 963 + return smu_cmn_send_smc_msg_with_param(smu, 964 + SMU_MSG_SetTimestamp, (uint32_t)timestamp, 0); 965 + } 966 + 967 + static int smu_v13_0_12_get_timestamp(struct amdgpu_device *adev, 968 + uint16_t index, uint64_t *timestamp) 969 + { 970 + struct smu_context *smu = adev->powerplay.pp_handle; 971 + uint32_t temp; 972 + int ret; 973 + 974 + ret = smu_cmn_send_smc_msg_with_param(smu, 975 + SMU_MSG_GetTimestamp, index, &temp); 976 + if (!ret) 977 + *timestamp = temp; 978 + 979 + return ret; 980 + } 981 + 982 + static int smu_v13_0_12_get_badpage_ipid(struct amdgpu_device *adev, 983 + uint16_t index, uint64_t *ipid) 984 + { 985 + struct smu_context *smu = adev->powerplay.pp_handle; 986 + uint32_t temp_arg, temp_ipid_lo, temp_ipid_high; 987 + int ret; 988 + 989 + temp_arg = index | (1 << 16); 990 + ret = smu_cmn_send_smc_msg_with_param(smu, 991 + SMU_MSG_GetBadPageIpid, temp_arg, &temp_ipid_lo); 992 + if (ret) 993 + return ret; 994 + 995 + temp_arg = index | (2 << 16); 996 + ret = smu_cmn_send_smc_msg_with_param(smu, 997 + SMU_MSG_GetBadPageIpid, temp_arg, &temp_ipid_high); 998 + if (!ret) 999 + *ipid = (uint64_t)temp_ipid_high << 32 | temp_ipid_lo; 1000 + return ret; 1001 + } 1002 + 1003 + static int smu_v13_0_12_erase_ras_table(struct amdgpu_device *adev, 1004 + uint32_t *result) 1005 + { 1006 + struct smu_context *smu = adev->powerplay.pp_handle; 1007 + 1008 + return smu_cmn_send_smc_msg_with_param(smu, 1009 + SMU_MSG_EraseRasTable, 0, result); 1010 + } 1011 + 1012 + static int smu_v13_0_12_get_badpage_mca_addr(struct amdgpu_device *adev, 1013 + uint16_t index, uint64_t *mca_addr) 1014 + { 1015 + struct smu_context *smu = adev->powerplay.pp_handle; 1016 + uint32_t temp_arg, temp_addr_lo, temp_addr_high; 1017 + int ret; 1018 + 1019 + temp_arg = index | (1 << 16); 1020 + ret = smu_cmn_send_smc_msg_with_param(smu, 1021 + SMU_MSG_GetBadPageMcaAddr, temp_arg, &temp_addr_lo); 1022 + if (ret) 1023 + return ret; 1024 + 1025 + temp_arg = index | (2 << 16); 1026 + ret = smu_cmn_send_smc_msg_with_param(smu, 1027 + SMU_MSG_GetBadPageMcaAddr, temp_arg, &temp_addr_high); 1028 + if (!ret) 1029 + *mca_addr = (uint64_t)temp_addr_high << 32 | temp_addr_lo; 1030 + return ret; 1031 + } 1032 + 1033 + static const struct ras_eeprom_smu_funcs smu_v13_0_12_eeprom_smu_funcs = { 1034 + .get_ras_table_version = smu_v13_0_12_get_ras_table_version, 1035 + .get_badpage_count = smu_v13_0_12_get_badpage_count, 1036 + .get_badpage_mca_addr = smu_v13_0_12_get_badpage_mca_addr, 1037 + .set_timestamp = smu_v13_0_12_set_timestamp, 1038 + .get_timestamp = smu_v13_0_12_get_timestamp, 1039 + .get_badpage_ipid = smu_v13_0_12_get_badpage_ipid, 1040 + .erase_ras_table = smu_v13_0_12_erase_ras_table, 1041 + }; 1042 + 1043 + static void smu_v13_0_12_ras_smu_feature_flags(struct amdgpu_device *adev, uint64_t *flags) 1044 + { 1045 + struct smu_context *smu = adev->powerplay.pp_handle; 1046 + 1047 + if (!flags) 1048 + return; 1049 + 1050 + *flags = 0ULL; 1051 + 1052 + if (smu_v13_0_6_cap_supported(smu, SMU_CAP(RAS_EEPROM))) 1053 + *flags |= RAS_SMU_FEATURE_BIT__RAS_EEPROM; 1054 + 1055 + } 1056 + 1057 + const struct ras_smu_drv smu_v13_0_12_ras_smu_drv = { 1058 + .smu_eeprom_funcs = &smu_v13_0_12_eeprom_smu_funcs, 1059 + .ras_smu_feature_flags = smu_v13_0_12_ras_smu_feature_flags, 939 1060 };

+130 -84

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

··· 549 549 { 550 550 struct smu_table_context *smu_table = &smu->smu_table; 551 551 struct smu_table *tables = smu_table->tables; 552 - void *gpu_metrics_table __free(kfree) = NULL; 552 + struct smu_v13_0_6_gpu_metrics *gpu_metrics; 553 553 void *driver_pptable __free(kfree) = NULL; 554 554 void *metrics_table __free(kfree) = NULL; 555 555 struct amdgpu_device *adev = smu->adev; ··· 579 579 return -ENOMEM; 580 580 smu_table->metrics_time = 0; 581 581 582 - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_8); 583 - gpu_metrics_table = 584 - kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 585 - if (!gpu_metrics_table) 586 - return -ENOMEM; 587 - 588 582 driver_pptable = kzalloc(sizeof(struct PPTable_t), GFP_KERNEL); 589 583 if (!driver_pptable) 590 584 return -ENOMEM; 591 585 586 + ret = smu_table_cache_init(smu, SMU_TABLE_SMU_METRICS, 587 + sizeof(struct smu_v13_0_6_gpu_metrics), 1); 588 + if (ret) 589 + return ret; 590 + 591 + gpu_metrics = (struct smu_v13_0_6_gpu_metrics 592 + *)(tables[SMU_TABLE_SMU_METRICS].cache.buffer); 593 + 594 + smu_v13_0_6_gpu_metrics_init(gpu_metrics, 1, 9); 592 595 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == 593 596 IP_VERSION(13, 0, 12)) { 594 597 ret = smu_v13_0_12_tables_init(smu); 595 - if (ret) 598 + if (ret) { 599 + smu_table_cache_fini(smu, SMU_TABLE_SMU_METRICS); 596 600 return ret; 601 + } 597 602 } 598 603 599 - smu_table->gpu_metrics_table = no_free_ptr(gpu_metrics_table); 600 604 smu_table->metrics_table = no_free_ptr(metrics_table); 601 605 smu_table->driver_pptable = no_free_ptr(driver_pptable); 602 606 ··· 736 732 { 737 733 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) 738 734 smu_v13_0_12_tables_fini(smu); 735 + smu_table_cache_fini(smu, SMU_TABLE_SMU_METRICS); 739 736 return smu_v13_0_fini_smc_tables(smu); 740 737 } 741 738 ··· 771 766 return ret; 772 767 } 773 768 774 - amdgpu_asic_invalidate_hdp(smu->adev, NULL); 769 + amdgpu_hdp_invalidate(smu->adev, NULL); 775 770 memcpy(smu_table->metrics_table, table->cpu_addr, table_size); 776 771 777 772 smu_table->metrics_time = jiffies; ··· 850 845 return ret; 851 846 } 852 847 853 - amdgpu_asic_invalidate_hdp(smu->adev, NULL); 848 + amdgpu_hdp_invalidate(smu->adev, NULL); 854 849 memcpy(smu_table->metrics_table, table->cpu_addr, table_size); 855 850 856 851 return 0; ··· 1399 1394 return -EINVAL; 1400 1395 1401 1396 if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) { 1402 - size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk); 1397 + size += sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk); 1403 1398 for (i = 0; i < clocks.num_levels; i++) 1404 1399 size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i, 1405 1400 clocks.data[i].clocks_in_khz / ··· 1519 1514 1520 1515 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1521 1516 1522 - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1523 - now, "mclk"); 1517 + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1518 + now, "mclk"); 1519 + if (ret < 0) 1520 + return ret; 1524 1521 1522 + size += ret; 1523 + break; 1525 1524 case SMU_SOCCLK: 1526 1525 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK, 1527 1526 &now); ··· 1537 1528 1538 1529 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1539 1530 1540 - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1541 - now, "socclk"); 1531 + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1532 + now, "socclk"); 1533 + if (ret < 0) 1534 + return ret; 1542 1535 1536 + size += ret; 1537 + break; 1543 1538 case SMU_FCLK: 1544 1539 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK, 1545 1540 &now); ··· 1555 1542 1556 1543 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1557 1544 1558 - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1559 - now, "fclk"); 1545 + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1546 + now, "fclk"); 1547 + if (ret < 0) 1548 + return ret; 1560 1549 1550 + size += ret; 1551 + break; 1561 1552 case SMU_VCLK: 1562 1553 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK, 1563 1554 &now); ··· 1573 1556 1574 1557 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1575 1558 1576 - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1577 - now, "vclk"); 1559 + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1560 + now, "vclk"); 1561 + if (ret < 0) 1562 + return ret; 1578 1563 1564 + size += ret; 1565 + break; 1579 1566 case SMU_DCLK: 1580 1567 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK, 1581 1568 &now); ··· 1591 1570 1592 1571 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1593 1572 1594 - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1595 - now, "dclk"); 1573 + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, 1574 + now, "dclk"); 1575 + if (ret < 0) 1576 + return ret; 1596 1577 1578 + size += ret; 1579 + break; 1597 1580 default: 1598 1581 break; 1599 1582 } ··· 1872 1847 if (current_power_limit) 1873 1848 *current_power_limit = power_limit; 1874 1849 if (default_power_limit) 1875 - *default_power_limit = power_limit; 1850 + *default_power_limit = pptable->MaxSocketPowerLimit; 1876 1851 1877 1852 if (max_power_limit) { 1878 1853 *max_power_limit = pptable->MaxSocketPowerLimit; ··· 2410 2385 2411 2386 memcpy(table->cpu_addr, table_data, table_size); 2412 2387 /* Flush hdp cache */ 2413 - amdgpu_asic_flush_hdp(adev, NULL); 2388 + amdgpu_hdp_flush(adev, NULL); 2414 2389 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction, 2415 2390 NULL); 2416 2391 ··· 2654 2629 { 2655 2630 const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; 2656 2631 int version = smu_v13_0_6_get_metrics_version(smu); 2657 - struct amdgpu_partition_metrics_v1_0 *xcp_metrics; 2632 + struct smu_v13_0_6_partition_metrics *xcp_metrics; 2658 2633 MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; 2659 2634 struct amdgpu_device *adev = smu->adev; 2660 2635 int ret, inst, i, j, k, idx; ··· 2674 2649 if (i == adev->xcp_mgr->num_xcps) 2675 2650 return -EINVAL; 2676 2651 2677 - xcp_metrics = (struct amdgpu_partition_metrics_v1_0 *)table; 2678 - smu_cmn_init_partition_metrics(xcp_metrics, 1, 0); 2652 + xcp_metrics = (struct smu_v13_0_6_partition_metrics *)table; 2653 + smu_v13_0_6_partition_metrics_init(xcp_metrics, 1, 1); 2679 2654 2680 2655 metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); 2681 2656 if (!metrics_v0) ··· 2767 2742 static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table) 2768 2743 { 2769 2744 struct smu_table_context *smu_table = &smu->smu_table; 2770 - struct gpu_metrics_v1_8 *gpu_metrics = 2771 - (struct gpu_metrics_v1_8 *)smu_table->gpu_metrics_table; 2745 + struct smu_table *tables = smu_table->tables; 2746 + struct smu_v13_0_6_gpu_metrics *gpu_metrics; 2772 2747 int version = smu_v13_0_6_get_metrics_version(smu); 2773 2748 MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; 2774 - int ret = 0, xcc_id, inst, i, j, k, idx; 2775 2749 struct amdgpu_device *adev = smu->adev; 2750 + int ret = 0, xcc_id, inst, i, j; 2776 2751 MetricsTableV1_t *metrics_v1; 2777 2752 MetricsTableV2_t *metrics_v2; 2778 - struct amdgpu_xcp *xcp; 2779 2753 u16 link_width_level; 2780 2754 u8 num_jpeg_rings; 2781 - u32 inst_mask; 2782 2755 bool per_inst; 2783 2756 2784 2757 metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); ··· 2784 2761 if (ret) 2785 2762 return ret; 2786 2763 2787 - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == 2788 - IP_VERSION(13, 0, 12) && 2789 - smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) 2790 - return smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0); 2764 + metrics_v2 = (MetricsTableV2_t *)metrics_v0; 2765 + gpu_metrics = (struct smu_v13_0_6_gpu_metrics 2766 + *)(tables[SMU_TABLE_SMU_METRICS].cache.buffer); 2767 + 2768 + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) && 2769 + smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) { 2770 + smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0, 2771 + gpu_metrics); 2772 + goto fill; 2773 + } 2791 2774 2792 2775 metrics_v1 = (MetricsTableV1_t *)metrics_v0; 2793 2776 metrics_v2 = (MetricsTableV2_t *)metrics_v0; 2794 - 2795 - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 8); 2796 2777 2797 2778 gpu_metrics->temperature_hotspot = 2798 2779 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)); ··· 2918 2891 gpu_metrics->xgmi_link_status[j] = ret; 2919 2892 } 2920 2893 2921 - gpu_metrics->num_partition = adev->xcp_mgr->num_xcps; 2922 - 2923 2894 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS)); 2924 2895 2925 2896 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; 2926 - for_each_xcp(adev->xcp_mgr, xcp, i) { 2927 - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 2928 - idx = 0; 2929 - for_each_inst(k, inst_mask) { 2930 - /* Both JPEG and VCN has same instances */ 2931 - inst = GET_INST(VCN, k); 2897 + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 2898 + inst = GET_INST(JPEG, i); 2899 + for (j = 0; j < num_jpeg_rings; ++j) 2900 + gpu_metrics->jpeg_busy[(i * num_jpeg_rings) + j] = 2901 + SMUQ10_ROUND(GET_METRIC_FIELD( 2902 + JpegBusy, 2903 + version)[(inst * num_jpeg_rings) + j]); 2904 + } 2905 + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2906 + inst = GET_INST(VCN, i); 2907 + gpu_metrics->vcn_busy[i] = 2908 + SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]); 2909 + } 2932 2910 2933 - for (j = 0; j < num_jpeg_rings; ++j) { 2934 - gpu_metrics->xcp_stats[i].jpeg_busy 2935 - [(idx * num_jpeg_rings) + j] = 2936 - SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version) 2937 - [(inst * num_jpeg_rings) + j]); 2938 - } 2939 - gpu_metrics->xcp_stats[i].vcn_busy[idx] = 2940 - SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]); 2941 - idx++; 2942 - 2943 - } 2944 - 2945 - if (per_inst) { 2946 - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 2947 - idx = 0; 2948 - for_each_inst(k, inst_mask) { 2949 - inst = GET_INST(GC, k); 2950 - gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] = 2951 - SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]); 2952 - gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] = 2953 - SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc, 2954 - version)[inst]); 2955 - if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) { 2956 - gpu_metrics->xcp_stats[i].gfx_below_host_limit_ppt_acc[idx] = 2957 - SMUQ10_ROUND 2958 - (metrics_v0->GfxclkBelowHostLimitPptAcc[inst]); 2959 - gpu_metrics->xcp_stats[i].gfx_below_host_limit_thm_acc[idx] = 2960 - SMUQ10_ROUND 2961 - (metrics_v0->GfxclkBelowHostLimitThmAcc[inst]); 2962 - gpu_metrics->xcp_stats[i].gfx_low_utilization_acc[idx] = 2963 - SMUQ10_ROUND 2964 - (metrics_v0->GfxclkLowUtilizationAcc[inst]); 2965 - gpu_metrics->xcp_stats[i].gfx_below_host_limit_total_acc[idx] = 2966 - SMUQ10_ROUND 2967 - (metrics_v0->GfxclkBelowHostLimitTotalAcc[inst]); 2968 - } 2969 - idx++; 2911 + if (per_inst) { 2912 + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { 2913 + inst = GET_INST(GC, i); 2914 + gpu_metrics->gfx_busy_inst[i] = SMUQ10_ROUND( 2915 + GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]); 2916 + gpu_metrics->gfx_busy_acc[i] = SMUQ10_ROUND( 2917 + GET_GPU_METRIC_FIELD(GfxBusyAcc, 2918 + version)[inst]); 2919 + if (smu_v13_0_6_cap_supported( 2920 + smu, SMU_CAP(HST_LIMIT_METRICS))) { 2921 + gpu_metrics->gfx_below_host_limit_ppt_acc 2922 + [i] = SMUQ10_ROUND( 2923 + metrics_v0->GfxclkBelowHostLimitPptAcc 2924 + [inst]); 2925 + gpu_metrics->gfx_below_host_limit_thm_acc 2926 + [i] = SMUQ10_ROUND( 2927 + metrics_v0->GfxclkBelowHostLimitThmAcc 2928 + [inst]); 2929 + gpu_metrics->gfx_low_utilization_acc 2930 + [i] = SMUQ10_ROUND( 2931 + metrics_v0 2932 + ->GfxclkLowUtilizationAcc[inst]); 2933 + gpu_metrics->gfx_below_host_limit_total_acc 2934 + [i] = SMUQ10_ROUND( 2935 + metrics_v0->GfxclkBelowHostLimitTotalAcc 2936 + [inst]); 2970 2937 } 2971 2938 } 2972 2939 } ··· 2970 2949 2971 2950 gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version); 2972 2951 2973 - *table = (void *)gpu_metrics; 2952 + fill: 2953 + *table = tables[SMU_TABLE_SMU_METRICS].cache.buffer; 2974 2954 2975 2955 return sizeof(*gpu_metrics); 2976 2956 } ··· 3905 3883 == IP_VERSION(13, 0, 12)) ? &smu_v13_0_12_temp_funcs : NULL; 3906 3884 } 3907 3885 3886 + static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras_smu_drv **ras_smu_drv) 3887 + { 3888 + if (!ras_smu_drv) 3889 + return -EINVAL; 3890 + 3891 + if (amdgpu_sriov_vf(smu->adev)) 3892 + return -EOPNOTSUPP; 3893 + 3894 + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_HROM_EN_BIT)) 3895 + smu_v13_0_6_cap_set(smu, SMU_CAP(RAS_EEPROM)); 3896 + 3897 + switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { 3898 + case IP_VERSION(13, 0, 12): 3899 + *ras_smu_drv = &smu_v13_0_12_ras_smu_drv; 3900 + break; 3901 + default: 3902 + *ras_smu_drv = NULL; 3903 + break; 3904 + } 3905 + 3906 + return 0; 3907 + } 3908 + 3908 3909 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { 3909 3910 /* init dpm */ 3910 3911 .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask, ··· 3987 3942 .dpm_reset_vcn = smu_v13_0_6_reset_vcn, 3988 3943 .post_init = smu_v13_0_6_post_init, 3989 3944 .ras_send_msg = smu_v13_0_6_ras_send_msg, 3945 + .get_ras_smu_drv = smu_v13_0_6_get_ras_smu_drv, 3990 3946 }; 3991 3947 3992 3948 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)

+160 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

··· 72 72 SMU_CAP(PLDM_VERSION), 73 73 SMU_CAP(TEMP_METRICS), 74 74 SMU_CAP(NPM_METRICS), 75 + SMU_CAP(RAS_EEPROM), 75 76 SMU_CAP(ALL), 76 77 }; 78 + 79 + #define SMU_13_0_6_NUM_XGMI_LINKS 8 80 + #define SMU_13_0_6_MAX_GFX_CLKS 8 81 + #define SMU_13_0_6_MAX_CLKS 4 82 + #define SMU_13_0_6_MAX_XCC 8 83 + #define SMU_13_0_6_MAX_VCN 4 84 + #define SMU_13_0_6_MAX_JPEG 40 77 85 78 86 extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu); 79 87 bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap); ··· 95 87 int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu); 96 88 int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, 97 89 MetricsMember_t member, uint32_t *value); 98 - ssize_t smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, void *smu_metrics); 99 90 ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, 100 91 struct amdgpu_xcp *xcp, void *table, 101 92 void *smu_metrics); ··· 106 99 extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[]; 107 100 extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[]; 108 101 extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; 102 + extern const struct ras_smu_drv smu_v13_0_12_ras_smu_drv; 103 + 104 + #if defined(SWSMU_CODE_LAYER_L2) 105 + #include "smu_cmn.h" 106 + 107 + /* SMUv 13.0.6 GPU metrics*/ 108 + #define SMU_13_0_6_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ 109 + SMU_SCALAR(SMU_MATTR(TEMPERATURE_HOTSPOT), SMU_MUNIT(TEMP_1), \ 110 + SMU_MTYPE(U16), temperature_hotspot); \ 111 + SMU_SCALAR(SMU_MATTR(TEMPERATURE_MEM), SMU_MUNIT(TEMP_1), \ 112 + SMU_MTYPE(U16), temperature_mem); \ 113 + SMU_SCALAR(SMU_MATTR(TEMPERATURE_VRSOC), SMU_MUNIT(TEMP_1), \ 114 + SMU_MTYPE(U16), temperature_vrsoc); \ 115 + SMU_SCALAR(SMU_MATTR(CURR_SOCKET_POWER), SMU_MUNIT(POWER_1), \ 116 + SMU_MTYPE(U16), curr_socket_power); \ 117 + SMU_SCALAR(SMU_MATTR(AVERAGE_GFX_ACTIVITY), SMU_MUNIT(PERCENT), \ 118 + SMU_MTYPE(U16), average_gfx_activity); \ 119 + SMU_SCALAR(SMU_MATTR(AVERAGE_UMC_ACTIVITY), SMU_MUNIT(PERCENT), \ 120 + SMU_MTYPE(U16), average_umc_activity); \ 121 + SMU_SCALAR(SMU_MATTR(MEM_MAX_BANDWIDTH), SMU_MUNIT(BW_1), \ 122 + SMU_MTYPE(U64), mem_max_bandwidth); \ 123 + SMU_SCALAR(SMU_MATTR(ENERGY_ACCUMULATOR), SMU_MUNIT(NONE), \ 124 + SMU_MTYPE(U64), energy_accumulator); \ 125 + SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1), \ 126 + SMU_MTYPE(U64), system_clock_counter); \ 127 + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ 128 + SMU_MTYPE(U32), accumulation_counter); \ 129 + SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 130 + SMU_MTYPE(U32), prochot_residency_acc); \ 131 + SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 132 + SMU_MTYPE(U32), ppt_residency_acc); \ 133 + SMU_SCALAR(SMU_MATTR(SOCKET_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 134 + SMU_MTYPE(U32), socket_thm_residency_acc); \ 135 + SMU_SCALAR(SMU_MATTR(VR_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 136 + SMU_MTYPE(U32), vr_thm_residency_acc); \ 137 + SMU_SCALAR(SMU_MATTR(HBM_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 138 + SMU_MTYPE(U32), hbm_thm_residency_acc); \ 139 + SMU_SCALAR(SMU_MATTR(GFXCLK_LOCK_STATUS), SMU_MUNIT(NONE), \ 140 + SMU_MTYPE(U32), gfxclk_lock_status); \ 141 + SMU_SCALAR(SMU_MATTR(PCIE_LINK_WIDTH), SMU_MUNIT(NONE), \ 142 + SMU_MTYPE(U16), pcie_link_width); \ 143 + SMU_SCALAR(SMU_MATTR(PCIE_LINK_SPEED), SMU_MUNIT(SPEED_2), \ 144 + SMU_MTYPE(U16), pcie_link_speed); \ 145 + SMU_SCALAR(SMU_MATTR(XGMI_LINK_WIDTH), SMU_MUNIT(NONE), \ 146 + SMU_MTYPE(U16), xgmi_link_width); \ 147 + SMU_SCALAR(SMU_MATTR(XGMI_LINK_SPEED), SMU_MUNIT(SPEED_1), \ 148 + SMU_MTYPE(U16), xgmi_link_speed); \ 149 + SMU_SCALAR(SMU_MATTR(GFX_ACTIVITY_ACC), SMU_MUNIT(PERCENT), \ 150 + SMU_MTYPE(U32), gfx_activity_acc); \ 151 + SMU_SCALAR(SMU_MATTR(MEM_ACTIVITY_ACC), SMU_MUNIT(PERCENT), \ 152 + SMU_MTYPE(U32), mem_activity_acc); \ 153 + SMU_SCALAR(SMU_MATTR(PCIE_BANDWIDTH_ACC), SMU_MUNIT(PERCENT), \ 154 + SMU_MTYPE(U64), pcie_bandwidth_acc); \ 155 + SMU_SCALAR(SMU_MATTR(PCIE_BANDWIDTH_INST), SMU_MUNIT(BW_1), \ 156 + SMU_MTYPE(U64), pcie_bandwidth_inst); \ 157 + SMU_SCALAR(SMU_MATTR(PCIE_L0_TO_RECOV_COUNT_ACC), SMU_MUNIT(NONE), \ 158 + SMU_MTYPE(U64), pcie_l0_to_recov_count_acc); \ 159 + SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_COUNT_ACC), SMU_MUNIT(NONE), \ 160 + SMU_MTYPE(U64), pcie_replay_count_acc); \ 161 + SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_ROVER_COUNT_ACC), SMU_MUNIT(NONE), \ 162 + SMU_MTYPE(U64), pcie_replay_rover_count_acc); \ 163 + SMU_SCALAR(SMU_MATTR(PCIE_NAK_SENT_COUNT_ACC), SMU_MUNIT(NONE), \ 164 + SMU_MTYPE(U32), pcie_nak_sent_count_acc); \ 165 + SMU_SCALAR(SMU_MATTR(PCIE_NAK_RCVD_COUNT_ACC), SMU_MUNIT(NONE), \ 166 + SMU_MTYPE(U32), pcie_nak_rcvd_count_acc); \ 167 + SMU_ARRAY(SMU_MATTR(XGMI_READ_DATA_ACC), SMU_MUNIT(DATA_1), \ 168 + SMU_MTYPE(U64), xgmi_read_data_acc, \ 169 + SMU_13_0_6_NUM_XGMI_LINKS); \ 170 + SMU_ARRAY(SMU_MATTR(XGMI_WRITE_DATA_ACC), SMU_MUNIT(DATA_1), \ 171 + SMU_MTYPE(U64), xgmi_write_data_acc, \ 172 + SMU_13_0_6_NUM_XGMI_LINKS); \ 173 + SMU_ARRAY(SMU_MATTR(XGMI_LINK_STATUS), SMU_MUNIT(NONE), \ 174 + SMU_MTYPE(U16), xgmi_link_status, \ 175 + SMU_13_0_6_NUM_XGMI_LINKS); \ 176 + SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ 177 + SMU_MTYPE(U64), firmware_timestamp); \ 178 + SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ 179 + SMU_MTYPE(U16), current_gfxclk, SMU_13_0_6_MAX_GFX_CLKS); \ 180 + SMU_ARRAY(SMU_MATTR(CURRENT_SOCCLK), SMU_MUNIT(CLOCK_1), \ 181 + SMU_MTYPE(U16), current_socclk, SMU_13_0_6_MAX_CLKS); \ 182 + SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ 183 + SMU_MTYPE(U16), current_vclk0, SMU_13_0_6_MAX_CLKS); \ 184 + SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ 185 + SMU_MTYPE(U16), current_dclk0, SMU_13_0_6_MAX_CLKS); \ 186 + SMU_SCALAR(SMU_MATTR(CURRENT_UCLK), SMU_MUNIT(CLOCK_1), \ 187 + SMU_MTYPE(U16), current_uclk); \ 188 + SMU_SCALAR(SMU_MATTR(PCIE_LC_PERF_OTHER_END_RECOVERY), \ 189 + SMU_MUNIT(NONE), SMU_MTYPE(U32), \ 190 + pcie_lc_perf_other_end_recovery); \ 191 + SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ 192 + SMU_MTYPE(U32), gfx_busy_inst, SMU_13_0_6_MAX_XCC); \ 193 + SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ 194 + jpeg_busy, SMU_13_0_6_MAX_JPEG); \ 195 + SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ 196 + vcn_busy, SMU_13_0_6_MAX_VCN); \ 197 + SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(PERCENT), SMU_MTYPE(U64), \ 198 + gfx_busy_acc, SMU_13_0_6_MAX_XCC); \ 199 + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ 200 + SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ 201 + SMU_13_0_6_MAX_XCC); \ 202 + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ 203 + SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ 204 + SMU_13_0_6_MAX_XCC); \ 205 + SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ 206 + SMU_MTYPE(U64), gfx_low_utilization_acc, \ 207 + SMU_13_0_6_MAX_XCC); \ 208 + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ 209 + SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ 210 + SMU_13_0_6_MAX_XCC); 211 + 212 + DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_gpu_metrics, SMU_13_0_6_METRICS_FIELDS); 213 + void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, 214 + void *smu_metrics, 215 + struct smu_v13_0_6_gpu_metrics *gpu_metrics); 216 + 217 + #define SMU_13_0_6_PARTITION_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ 218 + SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ 219 + SMU_MTYPE(U16), current_gfxclk, SMU_13_0_6_MAX_XCC); \ 220 + SMU_ARRAY(SMU_MATTR(CURRENT_SOCCLK), SMU_MUNIT(CLOCK_1), \ 221 + SMU_MTYPE(U16), current_socclk, SMU_13_0_6_MAX_CLKS); \ 222 + SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ 223 + SMU_MTYPE(U16), current_vclk0, SMU_13_0_6_MAX_CLKS); \ 224 + SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ 225 + SMU_MTYPE(U16), current_dclk0, SMU_13_0_6_MAX_CLKS); \ 226 + SMU_SCALAR(SMU_MATTR(CURRENT_UCLK), SMU_MUNIT(CLOCK_1), \ 227 + SMU_MTYPE(U16), current_uclk); \ 228 + SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ 229 + SMU_MTYPE(U32), gfx_busy_inst, SMU_13_0_6_MAX_XCC); \ 230 + SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ 231 + jpeg_busy, SMU_13_0_6_MAX_JPEG); \ 232 + SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ 233 + vcn_busy, SMU_13_0_6_MAX_VCN); \ 234 + SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(PERCENT), SMU_MTYPE(U64), \ 235 + gfx_busy_acc, SMU_13_0_6_MAX_XCC); \ 236 + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ 237 + SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ 238 + SMU_13_0_6_MAX_XCC); \ 239 + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ 240 + SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ 241 + SMU_13_0_6_MAX_XCC); \ 242 + SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ 243 + SMU_MTYPE(U64), gfx_low_utilization_acc, \ 244 + SMU_13_0_6_MAX_XCC); \ 245 + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ 246 + SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ 247 + SMU_13_0_6_MAX_XCC); 248 + 249 + DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_partition_metrics, 250 + SMU_13_0_6_PARTITION_METRICS_FIELDS); 251 + 252 + #endif /* SWSMU_CODE_LAYER_L2 */ 253 + 109 254 #endif

+2 -2

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

··· 980 980 * Flush hdp cache: to guard the content seen by 981 981 * GPU is consitent with CPU. 982 982 */ 983 - amdgpu_asic_flush_hdp(adev, NULL); 983 + amdgpu_hdp_flush(adev, NULL); 984 984 } 985 985 986 986 ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ? ··· 992 992 return ret; 993 993 994 994 if (!drv2smu) { 995 - amdgpu_asic_invalidate_hdp(adev, NULL); 995 + amdgpu_hdp_invalidate(adev, NULL); 996 996 memcpy(table_data, table->cpu_addr, table_size); 997 997 } 998 998

+67

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

··· 202 202 u32 workload_mask, 203 203 u32 *backend_workload_mask); 204 204 205 + /*SMU gpu metrics */ 206 + 207 + /* Attribute ID mapping */ 208 + #define SMU_MATTR(X) AMDGPU_METRICS_ATTR_ID_##X 209 + /* Type ID mapping */ 210 + #define SMU_MTYPE(X) AMDGPU_METRICS_TYPE_##X 211 + /* Unit ID mapping */ 212 + #define SMU_MUNIT(X) AMDGPU_METRICS_UNIT_##X 213 + 214 + /* Map TYPEID to C type */ 215 + #define SMU_CTYPE(TYPEID) SMU_CTYPE_##TYPEID 216 + 217 + #define SMU_CTYPE_AMDGPU_METRICS_TYPE_U8 u8 218 + #define SMU_CTYPE_AMDGPU_METRICS_TYPE_S8 s8 219 + #define SMU_CTYPE_AMDGPU_METRICS_TYPE_U16 u16 220 + #define SMU_CTYPE_AMDGPU_METRICS_TYPE_S16 s16 221 + #define SMU_CTYPE_AMDGPU_METRICS_TYPE_U32 u32 222 + #define SMU_CTYPE_AMDGPU_METRICS_TYPE_S32 s32 223 + #define SMU_CTYPE_AMDGPU_METRICS_TYPE_U64 u64 224 + #define SMU_CTYPE_AMDGPU_METRICS_TYPE_S64 s64 225 + 226 + /* struct members */ 227 + #define SMU_METRICS_SCALAR(ID, UNIT, TYPEID, NAME) \ 228 + u64 NAME##_ftype; \ 229 + SMU_CTYPE(TYPEID) NAME 230 + 231 + #define SMU_METRICS_ARRAY(ID, UNIT, TYPEID, NAME, SIZE) \ 232 + u64 NAME##_ftype; \ 233 + SMU_CTYPE(TYPEID) NAME[SIZE] 234 + 235 + /* Init functions for scalar/array fields - init to 0xFFs */ 236 + #define SMU_METRICS_INIT_SCALAR(ID, UNIT, TYPEID, NAME) \ 237 + do { \ 238 + obj->NAME##_ftype = \ 239 + AMDGPU_METRICS_ENC_ATTR(UNIT, TYPEID, ID, 1); \ 240 + obj->NAME = (SMU_CTYPE(TYPEID)) ~0; \ 241 + count++; \ 242 + } while (0) 243 + 244 + #define SMU_METRICS_INIT_ARRAY(ID, UNIT, TYPEID, NAME, SIZE) \ 245 + do { \ 246 + obj->NAME##_ftype = \ 247 + AMDGPU_METRICS_ENC_ATTR(UNIT, TYPEID, ID, SIZE); \ 248 + memset(obj->NAME, 0xFF, sizeof(obj->NAME)); \ 249 + count++; \ 250 + } while (0) 251 + 252 + /* Declare Metrics Class and Template object */ 253 + #define DECLARE_SMU_METRICS_CLASS(CLASSNAME, SMU_METRICS_FIELD_LIST) \ 254 + struct __packed CLASSNAME { \ 255 + struct metrics_table_header header; \ 256 + int attr_count; \ 257 + SMU_METRICS_FIELD_LIST(SMU_METRICS_SCALAR, SMU_METRICS_ARRAY); \ 258 + }; \ 259 + static inline void CLASSNAME##_init(struct CLASSNAME *obj, \ 260 + uint8_t frev, uint8_t crev) \ 261 + { \ 262 + int count = 0; \ 263 + memset(obj, 0xFF, sizeof(*obj)); \ 264 + obj->header.format_revision = frev; \ 265 + obj->header.content_revision = crev; \ 266 + obj->header.structure_size = sizeof(*obj); \ 267 + SMU_METRICS_FIELD_LIST(SMU_METRICS_INIT_SCALAR, \ 268 + SMU_METRICS_INIT_ARRAY) \ 269 + obj->attr_count = count; \ 270 + } 271 + 205 272 #endif 206 273 #endif

+1

drivers/gpu/drm/amd/pm/swsmu/smu_internal.h

··· 100 100 #define smu_is_asic_wbrf_supported(smu) smu_ppt_funcs(is_asic_wbrf_supported, false, smu) 101 101 #define smu_enable_uclk_shadow(smu, enable) smu_ppt_funcs(enable_uclk_shadow, 0, smu, enable) 102 102 #define smu_set_wbrf_exclusion_ranges(smu, freq_band_range) smu_ppt_funcs(set_wbrf_exclusion_ranges, -EOPNOTSUPP, smu, freq_band_range) 103 + #define smu_get_ras_smu_drv(smu, ras_smu_drv) smu_ppt_funcs(get_ras_smu_drv, -EOPNOTSUPP, smu, ras_smu_drv) 103 104 104 105 #endif 105 106 #endif

+1

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c

··· 85 85 case IP_VERSION(13, 0, 5): 86 86 case IP_VERSION(13, 0, 6): 87 87 case IP_VERSION(13, 0, 10): 88 + case IP_VERSION(13, 0, 12): 88 89 case IP_VERSION(13, 0, 14): 89 90 control->i2c_address = EEPROM_I2C_MADDR_4; 90 91 return 0;

+47 -10

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c

··· 37 37 #define MAX_XCD_NUM_PER_AID 2 38 38 39 39 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ 40 - #define ESTIMATE_BAD_PAGE_THRESHOLD(size) ((size)/(100 * 1024 * 1024ULL)) 40 + #define TYPICAL_ECC_BAD_PAGE_RATE (100ULL * SZ_1M) 41 41 42 42 #define COUNT_BAD_PAGE_THRESHOLD(size) (((size) >> 21) << 4) 43 43 ··· 129 129 */ 130 130 if (amdgpu_bad_page_threshold == NONSTOP_OVER_THRESHOLD) 131 131 eeprom_cfg->eeprom_record_threshold_count = 132 - ESTIMATE_BAD_PAGE_THRESHOLD(adev->gmc.mc_vram_size); 132 + div64_u64(adev->gmc.mc_vram_size, TYPICAL_ECC_BAD_PAGE_RATE); 133 133 else if (amdgpu_bad_page_threshold == WARN_NONSTOP_OVER_THRESHOLD) 134 134 eeprom_cfg->eeprom_record_threshold_count = 135 135 COUNT_BAD_PAGE_THRESHOLD(RAS_RESERVED_VRAM_SIZE_DEFAULT); ··· 172 172 173 173 switch (config->nbio_ip_version) { 174 174 case IP_VERSION(7, 9, 0): 175 + case IP_VERSION(7, 9, 1): 175 176 nbio_cfg->nbio_sys_fn = &amdgpu_ras_nbio_sys_func_v7_9; 176 177 break; 177 178 default: 178 179 RAS_DEV_ERR(adev, 179 180 "The nbio(0x%x) ras config is not right!\n", 180 - config->mp1_ip_version); 181 + config->nbio_ip_version); 181 182 ret = -EINVAL; 182 183 break; 183 184 } ··· 259 258 init_config.nbio_ip_version = amdgpu_ip_version(adev, NBIO_HWIP, 0); 260 259 init_config.psp_ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0); 261 260 262 - if (init_config.umc_ip_version == IP_VERSION(12, 0, 0)) 261 + if (init_config.umc_ip_version == IP_VERSION(12, 0, 0) || 262 + init_config.umc_ip_version == IP_VERSION(12, 5, 0)) 263 263 init_config.aca_ip_version = IP_VERSION(1, 0, 0); 264 264 265 265 init_config.sys_fn = &amdgpu_ras_sys_fn; ··· 284 282 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 285 283 struct amdgpu_ras_mgr *ras_mgr; 286 284 int ret = 0; 285 + 286 + /* Disabled by default */ 287 + con->uniras_enabled = false; 288 + 289 + /* Enabled only in debug mode */ 290 + if (adev->debug_enable_ras_aca) { 291 + con->uniras_enabled = true; 292 + RAS_DEV_INFO(adev, "Debug amdgpu uniras!"); 293 + } 294 + 295 + if (!con->uniras_enabled) 296 + return 0; 287 297 288 298 ras_mgr = kzalloc(sizeof(*ras_mgr), GFP_KERNEL); 289 299 if (!ras_mgr) ··· 329 315 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 330 316 struct amdgpu_ras_mgr *ras_mgr = (struct amdgpu_ras_mgr *)con->ras_mgr; 331 317 318 + if (!con->uniras_enabled) 319 + return 0; 320 + 332 321 if (!ras_mgr) 333 322 return 0; 334 323 ··· 349 332 static int amdgpu_ras_mgr_hw_init(struct amdgpu_ip_block *ip_block) 350 333 { 351 334 struct amdgpu_device *adev = ip_block->adev; 335 + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 352 336 struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 353 337 int ret; 354 338 355 - /* Currently only debug mode can enable the ras module 356 - */ 357 - if (!adev->debug_enable_ras_aca) 339 + if (!con->uniras_enabled) 358 340 return 0; 359 341 360 342 if (!ras_mgr || !ras_mgr->ras_core) ··· 376 360 static int amdgpu_ras_mgr_hw_fini(struct amdgpu_ip_block *ip_block) 377 361 { 378 362 struct amdgpu_device *adev = ip_block->adev; 363 + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 379 364 struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 380 365 381 - /* Currently only debug mode can enable the ras module 382 - */ 383 - if (!adev->debug_enable_ras_aca) 366 + if (!con->uniras_enabled) 384 367 return 0; 385 368 386 369 if (!ras_mgr || !ras_mgr->ras_core) ··· 623 608 kfree(cmd_ctx); 624 609 625 610 return ret; 611 + } 612 + 613 + int amdgpu_ras_mgr_pre_reset(struct amdgpu_device *adev) 614 + { 615 + if (!amdgpu_ras_mgr_is_ready(adev)) { 616 + RAS_DEV_ERR(adev, "Invalid ras suspend!\n"); 617 + return -EPERM; 618 + } 619 + 620 + amdgpu_ras_process_pre_reset(adev); 621 + return 0; 622 + } 623 + 624 + int amdgpu_ras_mgr_post_reset(struct amdgpu_device *adev) 625 + { 626 + if (!amdgpu_ras_mgr_is_ready(adev)) { 627 + RAS_DEV_ERR(adev, "Invalid ras resume!\n"); 628 + return -EPERM; 629 + } 630 + 631 + amdgpu_ras_process_post_reset(adev); 632 + return 0; 626 633 }

+5

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h

··· 52 52 struct ras_event_manager ras_event_mgr; 53 53 uint64_t last_poison_consumption_seqno; 54 54 bool ras_is_ready; 55 + 56 + bool is_paused; 57 + struct completion ras_event_done; 55 58 }; 56 59 57 60 extern const struct amdgpu_ip_block_version ras_v1_0_ip_block; ··· 78 75 int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev, 79 76 uint32_t cmd_id, void *input, uint32_t input_size, 80 77 void *output, uint32_t out_size); 78 + int amdgpu_ras_mgr_pre_reset(struct amdgpu_device *adev); 79 + int amdgpu_ras_mgr_post_reset(struct amdgpu_device *adev); 81 80 #endif

+64

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c

··· 29 29 #include "amdgpu_ras_process.h" 30 30 31 31 #define RAS_MGR_RETIRE_PAGE_INTERVAL 100 32 + #define RAS_EVENT_PROCESS_TIMEOUT 1200 32 33 33 34 static void ras_process_retire_page_dwork(struct work_struct *work) 34 35 { ··· 58 57 { 59 58 struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 60 59 60 + ras_mgr->is_paused = false; 61 + init_completion(&ras_mgr->ras_event_done); 62 + 61 63 INIT_DELAYED_WORK(&ras_mgr->retire_page_dwork, ras_process_retire_page_dwork); 62 64 63 65 return 0; ··· 70 66 { 71 67 struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 72 68 69 + ras_mgr->is_paused = false; 73 70 /* Save all cached bad pages to eeprom */ 74 71 flush_delayed_work(&ras_mgr->retire_page_dwork); 75 72 cancel_delayed_work_sync(&ras_mgr->retire_page_dwork); ··· 128 123 req.seqno = seqno; 129 124 130 125 return ras_process_add_interrupt_req(ras_mgr->ras_core, &req, false); 126 + } 127 + 128 + int amdgpu_ras_process_begin(struct amdgpu_device *adev) 129 + { 130 + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 131 + 132 + if (ras_mgr->is_paused) 133 + return -EAGAIN; 134 + 135 + reinit_completion(&ras_mgr->ras_event_done); 136 + return 0; 137 + } 138 + 139 + int amdgpu_ras_process_end(struct amdgpu_device *adev) 140 + { 141 + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 142 + 143 + complete(&ras_mgr->ras_event_done); 144 + return 0; 145 + } 146 + 147 + int amdgpu_ras_process_pre_reset(struct amdgpu_device *adev) 148 + { 149 + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 150 + long rc; 151 + 152 + if (!ras_mgr || !ras_mgr->ras_core) 153 + return -EINVAL; 154 + 155 + if (!ras_mgr->ras_core->is_initialized) 156 + return -EPERM; 157 + 158 + ras_mgr->is_paused = true; 159 + 160 + /* Wait for RAS event processing to complete */ 161 + rc = wait_for_completion_interruptible_timeout(&ras_mgr->ras_event_done, 162 + msecs_to_jiffies(RAS_EVENT_PROCESS_TIMEOUT)); 163 + if (rc <= 0) 164 + RAS_DEV_WARN(adev, "Waiting for ras process to complete %s\n", 165 + rc ? "interrupted" : "timeout"); 166 + 167 + flush_delayed_work(&ras_mgr->retire_page_dwork); 168 + return 0; 169 + } 170 + 171 + int amdgpu_ras_process_post_reset(struct amdgpu_device *adev) 172 + { 173 + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); 174 + 175 + if (!ras_mgr || !ras_mgr->ras_core) 176 + return -EINVAL; 177 + 178 + if (!ras_mgr->ras_core->is_initialized) 179 + return -EPERM; 180 + 181 + ras_mgr->is_paused = false; 182 + 183 + schedule_delayed_work(&ras_mgr->retire_page_dwork, 0); 184 + return 0; 131 185 }

+4

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h

··· 34 34 void *data); 35 35 int amdgpu_ras_process_handle_consumption_interrupt(struct amdgpu_device *adev, 36 36 void *data); 37 + int amdgpu_ras_process_begin(struct amdgpu_device *adev); 38 + int amdgpu_ras_process_end(struct amdgpu_device *adev); 39 + int amdgpu_ras_process_pre_reset(struct amdgpu_device *adev); 40 + int amdgpu_ras_process_post_reset(struct amdgpu_device *adev); 37 41 #endif

+6

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c

··· 142 142 case RAS_EVENT_ID__RESET_GPU: 143 143 ret = amdgpu_ras_mgr_reset_gpu(ras_core->dev, *(uint32_t *)data); 144 144 break; 145 + case RAS_EVENT_ID__RAS_EVENT_PROC_BEGIN: 146 + ret = amdgpu_ras_process_begin(ras_core->dev); 147 + break; 148 + case RAS_EVENT_ID__RAS_EVENT_PROC_END: 149 + ret = amdgpu_ras_process_end(ras_core->dev); 150 + break; 145 151 default: 146 152 RAS_DEV_WARN(ras_core->dev, "Invalid ras notify event:%d\n", event_id); 147 153 break;

+2

drivers/gpu/drm/amd/ras/rascore/ras.h

··· 115 115 RAS_EVENT_ID__FATAL_ERROR_DETECTED, 116 116 RAS_EVENT_ID__RESET_GPU, 117 117 RAS_EVENT_ID__RESET_VF, 118 + RAS_EVENT_ID__RAS_EVENT_PROC_BEGIN, 119 + RAS_EVENT_ID__RAS_EVENT_PROC_END, 118 120 }; 119 121 120 122 enum ras_gpu_status {

+12 -7

drivers/gpu/drm/amd/ras/rascore/ras_cper.c

··· 54 54 enum ras_cper_severity sev, struct ras_log_info *trace) 55 55 { 56 56 struct device_system_info dev_info = {0}; 57 - char record_id[16]; 57 + char record_id[32]; 58 58 59 59 hdr->signature[0] = 'C'; 60 60 hdr->signature[1] = 'P'; ··· 62 62 hdr->signature[3] = 'R'; 63 63 hdr->revision = CPER_HDR__REV_1; 64 64 hdr->signature_end = 0xFFFFFFFF; 65 - hdr->error_severity = sev; 65 + hdr->error_severity = (sev == RAS_CPER_SEV_RMA ? RAS_CPER_SEV_FATAL_UE : sev); 66 66 67 67 hdr->valid_bits.platform_id = 1; 68 - hdr->valid_bits.partition_id = 1; 69 68 hdr->valid_bits.timestamp = 1; 70 69 71 70 ras_core_get_device_system_info(ras_core, &dev_info); 72 71 73 72 cper_get_timestamp(ras_core, &hdr->timestamp, trace->timestamp); 74 73 75 - snprintf(record_id, 9, "%d:%llX", dev_info.socket_id, 74 + snprintf(record_id, sizeof(record_id), "%d:%llX", dev_info.socket_id, 76 75 RAS_LOG_SEQNO_TO_BATCH_IDX(trace->seqno)); 77 76 memcpy(hdr->record_id, record_id, 8); 78 77 ··· 115 116 descriptor->sec_length = section_length; 116 117 descriptor->valid_bits.fru_text = 1; 117 118 descriptor->flag_bits.primary = 1; 118 - descriptor->severity = sev; 119 + descriptor->severity = (sev == RAS_CPER_SEV_RMA ? RAS_CPER_SEV_FATAL_UE : sev); 119 120 descriptor->sec_type = sec_type; 120 121 121 122 ras_core_get_device_system_info(ras_core, &dev_info); ··· 146 147 } 147 148 148 149 static int fill_section_runtime(struct ras_core_context *ras_core, 149 - struct cper_section_runtime *runtime, struct ras_log_info *trace) 150 + struct cper_section_runtime *runtime, struct ras_log_info *trace, 151 + enum ras_cper_severity sev) 150 152 { 151 153 runtime->hdr.valid_bits.err_info_cnt = 1; 152 154 runtime->hdr.valid_bits.err_context_cnt = 1; 153 155 154 156 runtime->descriptor.error_type = RUNTIME; 155 157 runtime->descriptor.ms_chk_bits.err_type_valid = 1; 158 + if (sev == RAS_CPER_SEV_RMA) { 159 + runtime->descriptor.valid_bits.ms_chk = 1; 160 + runtime->descriptor.ms_chk_bits.err_type = 1; 161 + runtime->descriptor.ms_chk_bits.pcc = 1; 162 + } 156 163 157 164 runtime->reg.reg_ctx_type = CPER_CTX_TYPE__CRASH; 158 165 runtime->reg.reg_arr_size = sizeof(runtime->reg.reg_dump); ··· 194 189 fill_section_descriptor(ras_core, descriptor, sev, RUNTIME, 195 190 RAS_NONSTD_SEC_OFFSET(hdr->sec_cnt, i), 196 191 sizeof(struct cper_section_runtime)); 197 - fill_section_runtime(ras_core, runtime, trace_arr[i]); 192 + fill_section_runtime(ras_core, runtime, trace_arr[i], sev); 198 193 } 199 194 200 195 return 0;

+8 -1

drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c

··· 226 226 enum ras_log_event event, void *data, struct ras_log_batch_tag *batch_tag) 227 227 { 228 228 struct ras_log_ring *log_ring = &ras_core->ras_log_ring; 229 + struct device_system_info dev_info = {0}; 229 230 struct ras_log_info *log; 231 + uint64_t socket_id; 230 232 void *obj; 231 233 232 234 obj = mempool_alloc_preallocated(log_ring->ras_log_mempool); ··· 254 252 if (data) 255 253 memcpy(&log->aca_reg, data, sizeof(log->aca_reg)); 256 254 257 - if (event == RAS_LOG_EVENT_RMA) 255 + if (event == RAS_LOG_EVENT_RMA) { 258 256 memcpy(&log->aca_reg, ras_rma_aca_reg, sizeof(log->aca_reg)); 257 + ras_core_get_device_system_info(ras_core, &dev_info); 258 + socket_id = dev_info.socket_id; 259 + log->aca_reg.regs[ACA_REG_IDX__IPID] |= ((socket_id / 4) & 0x01); 260 + log->aca_reg.regs[ACA_REG_IDX__IPID] |= (((socket_id % 4) & 0x3) << 44); 261 + } 259 262 260 263 ras_log_ring_add_data(ras_core, log, batch_tag); 261 264 }

+1

drivers/gpu/drm/amd/ras/rascore/ras_nbio.c

··· 31 31 { 32 32 switch (ip_version) { 33 33 case IP_VERSION(7, 9, 0): 34 + case IP_VERSION(7, 9, 1): 34 35 return &ras_nbio_v7_9; 35 36 default: 36 37 RAS_DEV_ERR(ras_core->dev,

+7

drivers/gpu/drm/amd/ras/rascore/ras_process.c

··· 162 162 uint32_t umc_event_count; 163 163 int ret; 164 164 165 + ret = ras_core_event_notify(ras_core, 166 + RAS_EVENT_ID__RAS_EVENT_PROC_BEGIN, NULL); 167 + if (ret) 168 + return ret; 169 + 165 170 ras_aca_clear_fatal_flag(ras_core); 166 171 ras_umc_log_pending_bad_bank(ras_core); 167 172 ··· 190 185 atomic_set(&ras_proc->umc_interrupt_count, 0); 191 186 } 192 187 188 + ras_core_event_notify(ras_core, 189 + RAS_EVENT_ID__RAS_EVENT_PROC_END, NULL); 193 190 return ret; 194 191 } 195 192

+1

drivers/gpu/drm/amd/ras/rascore/ras_umc.c

··· 71 71 { 72 72 switch (ip_version) { 73 73 case IP_VERSION(12, 0, 0): 74 + case IP_VERSION(12, 5, 0): 74 75 return &ras_umc_func_v12_0; 75 76 default: 76 77 RAS_DEV_ERR(ras_core->dev,

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