Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: exynos5-usbdrd: uniform order of register bit macros
Most of the macros are ordered high -> low, but there are some
outliers.
Order them all uniformly from high to low. This will allow adding
additional register (field) definitions in a consistent way.
While at it, also remove some extra empty lines to group register bit
field definitions together with the relevant register. This makes the
registers easier to distinguish visually.
No functional change.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-1-4ccba5afa7cc@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
André Draszik
and committed by
Vinod Koul
2a0dc34b
2f2f5c13
+15
-29
+15
-29
drivers/phy/samsung/phy-exynos5-usbdrd.c
+15
-29
drivers/phy/samsung/phy-exynos5-usbdrd.c
···
35
35
36
36
/* Exynos5: USB 3.0 DRD PHY registers */
37
37
#define EXYNOS5_DRD_LINKSYSTEM 0x04
38
-
38
+
#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
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#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
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#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
41
-
#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
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#define EXYNOS5_DRD_PHYUTMI 0x08
44
-
45
43
#define PHYUTMI_OTGDISABLE BIT(6)
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44
#define PHYUTMI_FORCESUSPEND BIT(1)
47
45
#define PHYUTMI_FORCESLEEP BIT(0)
···
47
49
#define EXYNOS5_DRD_PHYPIPE 0x0c
48
50
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#define EXYNOS5_DRD_PHYCLKRST 0x10
50
-
51
52
#define PHYCLKRST_EN_UTMISUSPEND BIT(31)
52
-
53
53
#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
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#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
55
-
56
55
#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
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#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
58
-
59
57
#define PHYCLKRST_SSC_EN BIT(20)
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#define PHYCLKRST_REF_SSP_EN BIT(19)
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#define PHYCLKRST_REF_CLKDIV2 BIT(18)
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-
63
60
#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
67
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#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
68
65
#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
69
-
70
-
#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
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#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
67
+
#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
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68
#define PHYCLKRST_FSEL(_x) ((_x) << 5)
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#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
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#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
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#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
76
72
#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
77
-
78
73
#define PHYCLKRST_RETENABLEN BIT(4)
79
-
80
74
#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
81
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#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
82
76
#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
83
-
84
77
#define PHYCLKRST_PORTRESET BIT(1)
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78
#define PHYCLKRST_COMMONONN BIT(0)
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79
···
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100
#define PHYREG1_CR_ACK BIT(0)
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101
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102
#define EXYNOS5_DRD_PHYPARAM0 0x1c
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-
93
103
#define PHYPARAM0_REF_USE_PAD BIT(31)
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104
#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
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105
#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
96
106
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107
#define EXYNOS5_DRD_PHYPARAM1 0x20
98
-
99
108
#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
100
109
#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
101
110
102
111
#define EXYNOS5_DRD_PHYTERM 0x24
103
112
104
113
#define EXYNOS5_DRD_PHYTEST 0x28
105
-
106
114
#define PHYTEST_POWERDOWN_SSP BIT(3)
107
115
#define PHYTEST_POWERDOWN_HSP BIT(2)
108
116
109
117
#define EXYNOS5_DRD_PHYADP 0x2c
110
118
111
119
#define EXYNOS5_DRD_PHYUTMICLKSEL 0x30
112
-
113
120
#define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2)
114
121
115
122
#define EXYNOS5_DRD_PHYRESUME 0x34
123
+
116
124
#define EXYNOS5_DRD_LINKPORT 0x44
117
125
118
126
/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
···
133
147
134
148
/* Exynos850: USB DRD PHY registers */
135
149
#define EXYNOS850_DRD_LINKCTRL 0x04
136
-
#define LINKCTRL_BUS_FILTER_BYPASS(_x) ((_x) << 4)
137
150
#define LINKCTRL_FORCE_QACT BIT(8)
151
+
#define LINKCTRL_BUS_FILTER_BYPASS(_x) ((_x) << 4)
138
152
139
153
#define EXYNOS850_DRD_CLKRST 0x20
140
-
#define CLKRST_LINK_SW_RST BIT(0)
141
-
#define CLKRST_PORT_RST BIT(1)
142
154
#define CLKRST_PHY_SW_RST BIT(3)
155
+
#define CLKRST_PORT_RST BIT(1)
156
+
#define CLKRST_LINK_SW_RST BIT(0)
143
157
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158
#define EXYNOS850_DRD_UTMI 0x50
145
-
#define UTMI_FORCE_SLEEP BIT(0)
146
-
#define UTMI_FORCE_SUSPEND BIT(1)
147
-
#define UTMI_DM_PULLDOWN BIT(2)
148
-
#define UTMI_DP_PULLDOWN BIT(3)
149
-
#define UTMI_FORCE_BVALID BIT(4)
150
159
#define UTMI_FORCE_VBUSVALID BIT(5)
160
+
#define UTMI_FORCE_BVALID BIT(4)
161
+
#define UTMI_DP_PULLDOWN BIT(3)
162
+
#define UTMI_DM_PULLDOWN BIT(2)
163
+
#define UTMI_FORCE_SUSPEND BIT(1)
164
+
#define UTMI_FORCE_SLEEP BIT(0)
151
165
152
166
#define EXYNOS850_DRD_HSP 0x54
153
-
#define HSP_COMMONONN BIT(8)
154
-
#define HSP_EN_UTMISUSPEND BIT(9)
155
-
#define HSP_VBUSVLDEXT BIT(12)
156
-
#define HSP_VBUSVLDEXTSEL BIT(13)
157
167
#define HSP_FSV_OUT_EN BIT(24)
168
+
#define HSP_VBUSVLDEXTSEL BIT(13)
169
+
#define HSP_VBUSVLDEXT BIT(12)
170
+
#define HSP_EN_UTMISUSPEND BIT(9)
171
+
#define HSP_COMMONONN BIT(8)
158
172
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173
#define EXYNOS850_DRD_HSP_TEST 0x5c
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174
#define HSP_TEST_SIDDQ BIT(24)