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soundwire: amd: add clock init control function

Add generic SoundWire clock initialization sequence to support
different SoundWire bus clock frequencies for ACP6.3/7.0/7.1/7.2
platforms and remove hard coding initializations for 12Mhz bus
clock frequency.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.dev>
Link: https://patch.msgid.link/20260226065638.1251771-2-Vijendar.Mukunda@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Vijendar Mukunda and committed by
Vinod Koul 2a267a84 4b8fc2b1

+36 -11
+36 -7
drivers/soundwire/amd_manager.c
··· 27 27 28 28 #define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus) 29 29 30 + static int amd_sdw_clk_init_ctrl(struct amd_sdw_manager *amd_manager) 31 + { 32 + struct sdw_bus *bus = &amd_manager->bus; 33 + struct sdw_master_prop *prop = &bus->prop; 34 + u32 divider; 35 + 36 + dev_dbg(amd_manager->dev, "mclk %d max %d row %d col %d frame_rate:%d\n", 37 + prop->mclk_freq, prop->max_clk_freq, prop->default_row, 38 + prop->default_col, prop->default_frame_rate); 39 + 40 + if (!prop->default_frame_rate || !prop->default_row) { 41 + dev_err(amd_manager->dev, "Default frame_rate %d or row %d is invalid\n", 42 + prop->default_frame_rate, prop->default_row); 43 + return -EINVAL; 44 + } 45 + 46 + /* Set clock divider */ 47 + divider = (prop->mclk_freq / bus->params.curr_dr_freq); 48 + writel(divider, amd_manager->mmio + ACP_SW_CLK_FREQUENCY_CTRL); 49 + 50 + /* Set frame shape base on the actual bus frequency. */ 51 + prop->default_col = bus->params.curr_dr_freq / 52 + prop->default_frame_rate / prop->default_row; 53 + amd_manager->cols_index = sdw_find_col_index(prop->default_col); 54 + amd_manager->rows_index = sdw_find_row_index(prop->default_row); 55 + bus->params.col = prop->default_col; 56 + bus->params.row = prop->default_row; 57 + return 0; 58 + } 59 + 30 60 static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager) 31 61 { 32 62 u32 val; ··· 990 960 991 961 prop = &amd_manager->bus.prop; 992 962 if (!prop->hw_disabled) { 963 + ret = amd_sdw_clk_init_ctrl(amd_manager); 964 + if (ret) 965 + return ret; 993 966 ret = amd_init_sdw_manager(amd_manager); 994 967 if (ret) 995 968 return ret; ··· 1017 984 struct resource *res; 1018 985 struct device *dev = &pdev->dev; 1019 986 struct sdw_master_prop *prop; 1020 - struct sdw_bus_params *params; 1021 987 struct amd_sdw_manager *amd_manager; 1022 988 int ret; 1023 989 ··· 1080 1048 return -EINVAL; 1081 1049 } 1082 1050 1083 - params = &amd_manager->bus.params; 1084 - 1085 - params->col = AMD_SDW_DEFAULT_COLUMNS; 1086 - params->row = AMD_SDW_DEFAULT_ROWS; 1087 1051 prop = &amd_manager->bus.prop; 1088 - prop->clk_freq = &amd_sdw_freq_tbl[0]; 1089 1052 prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ; 1090 - prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ; 1091 1053 1092 1054 ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode); 1093 1055 if (ret) { ··· 1373 1347 } 1374 1348 } 1375 1349 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1350 + ret = amd_sdw_clk_init_ctrl(amd_manager); 1351 + if (ret) 1352 + return ret; 1376 1353 amd_init_sdw_manager(amd_manager); 1377 1354 amd_enable_sdw_interrupts(amd_manager); 1378 1355 ret = amd_enable_sdw_manager(amd_manager);
-4
drivers/soundwire/amd_manager.h
··· 203 203 #define AMD_SDW_DEVICE_STATE_D3 3 204 204 #define ACP_PME_EN 0x0001400 205 205 206 - static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = { 207 - AMD_SDW_DEFAULT_CLK_FREQ, 208 - }; 209 - 210 206 struct sdw_manager_dp_reg { 211 207 u32 frame_fmt_reg; 212 208 u32 sample_int_reg;