Merge branch 'bnxt_en-updates-for-net-next'

+4 -1

drivers/net/ethernet/broadcom/bnxt/bnxt.c

··· 142 142 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" }, 143 143 [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" }, 144 144 [NETXTREME_E_P7_VF] = { "Broadcom BCM5760X Virtual Function" }, 145 + [NETXTREME_E_P7_VF_HV] = { "Broadcom BCM5760X Virtual Function for Hyper-V" }, 145 146 }; 146 147 147 148 static const struct pci_device_id bnxt_pci_tbl[] = { ··· 218 217 { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV }, 219 218 { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV }, 220 219 { PCI_VDEVICE(BROADCOM, 0x1819), .driver_data = NETXTREME_E_P7_VF }, 220 + { PCI_VDEVICE(BROADCOM, 0x181b), .driver_data = NETXTREME_E_P7_VF_HV }, 221 221 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF }, 222 222 #endif 223 223 { 0 } ··· 317 315 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF || 318 316 idx == NETXTREME_S_VF || idx == NETXTREME_C_VF_HV || 319 317 idx == NETXTREME_E_VF_HV || idx == NETXTREME_E_P5_VF || 320 - idx == NETXTREME_E_P5_VF_HV || idx == NETXTREME_E_P7_VF); 318 + idx == NETXTREME_E_P5_VF_HV || idx == NETXTREME_E_P7_VF || 319 + idx == NETXTREME_E_P7_VF_HV); 321 320 } 322 321 323 322 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)

+2

drivers/net/ethernet/broadcom/bnxt/bnxt.h

··· 2130 2130 NETXTREME_E_P5_VF, 2131 2131 NETXTREME_E_P5_VF_HV, 2132 2132 NETXTREME_E_P7_VF, 2133 + NETXTREME_E_P7_VF_HV, 2133 2134 }; 2134 2135 2135 2136 #define BNXT_TRACE_BUF_MAGIC_BYTE ((u8)0xbc) ··· 2544 2543 u16 fw_rx_stats_ext_size; 2545 2544 u16 fw_tx_stats_ext_size; 2546 2545 u16 hw_ring_stats_size; 2546 + u16 pcie_stat_len; 2547 2547 u8 pri2cos_idx[8]; 2548 2548 u8 pri2cos_valid; 2549 2549

+58 -26

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

··· 2061 2061 static int bnxt_get_regs_len(struct net_device *dev) 2062 2062 { 2063 2063 struct bnxt *bp = netdev_priv(dev); 2064 - int reg_len; 2065 2064 2066 2065 if (!BNXT_PF(bp)) 2067 2066 return -EOPNOTSUPP; 2068 2067 2069 - reg_len = BNXT_PXP_REG_LEN; 2068 + return BNXT_PXP_REG_LEN + bp->pcie_stat_len; 2069 + } 2070 2070 2071 - if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 2072 - reg_len += sizeof(struct pcie_ctx_hw_stats); 2071 + static void * 2072 + __bnxt_hwrm_pcie_qstats(struct bnxt *bp, struct hwrm_pcie_qstats_input *req) 2073 + { 2074 + struct pcie_ctx_hw_stats_v2 *hw_pcie_stats; 2075 + dma_addr_t hw_pcie_stats_addr; 2076 + int rc; 2073 2077 2074 - return reg_len; 2078 + hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2079 + &hw_pcie_stats_addr); 2080 + if (!hw_pcie_stats) 2081 + return NULL; 2082 + 2083 + req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2084 + req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2085 + rc = hwrm_req_send(bp, req); 2086 + 2087 + return rc ? NULL : hw_pcie_stats; 2075 2088 } 2076 2089 2077 2090 #define BNXT_PCIE_32B_ENTRY(start, end) \ 2078 - { offsetof(struct pcie_ctx_hw_stats, start), \ 2079 - offsetof(struct pcie_ctx_hw_stats, end) } 2091 + { offsetof(struct pcie_ctx_hw_stats_v2, start),\ 2092 + offsetof(struct pcie_ctx_hw_stats_v2, end) } 2080 2093 2081 2094 static const struct { 2082 2095 u16 start; 2083 2096 u16 end; 2084 2097 } bnxt_pcie_32b_entries[] = { 2085 2098 BNXT_PCIE_32B_ENTRY(pcie_ltssm_histogram[0], pcie_ltssm_histogram[3]), 2099 + BNXT_PCIE_32B_ENTRY(pcie_tl_credit_nph_histogram[0], unused_1), 2100 + BNXT_PCIE_32B_ENTRY(pcie_rd_latency_histogram[0], unused_2), 2086 2101 }; 2087 2102 2088 2103 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2089 2104 void *_p) 2090 2105 { 2091 - struct pcie_ctx_hw_stats *hw_pcie_stats; 2106 + struct hwrm_pcie_qstats_output *resp; 2092 2107 struct hwrm_pcie_qstats_input *req; 2093 2108 struct bnxt *bp = netdev_priv(dev); 2094 - dma_addr_t hw_pcie_stats_addr; 2095 - int rc; 2109 + u8 *src; 2096 2110 2097 2111 regs->version = 0; 2098 2112 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED)) ··· 2118 2104 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 2119 2105 return; 2120 2106 2121 - hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 2122 - &hw_pcie_stats_addr); 2123 - if (!hw_pcie_stats) { 2124 - hwrm_req_drop(bp, req); 2125 - return; 2126 - } 2127 - 2128 - regs->version = 1; 2129 - hwrm_req_hold(bp, req); /* hold on to slice */ 2130 - req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 2131 - req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 2132 - rc = hwrm_req_send(bp, req); 2133 - if (!rc) { 2107 + resp = hwrm_req_hold(bp, req); 2108 + src = __bnxt_hwrm_pcie_qstats(bp, req); 2109 + if (src) { 2134 2110 u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN); 2135 - u8 *src = (u8 *)hw_pcie_stats; 2136 - int i, j; 2111 + int i, j, len; 2137 2112 2138 - for (i = 0, j = 0; i < sizeof(*hw_pcie_stats); ) { 2113 + len = min(bp->pcie_stat_len, le16_to_cpu(resp->pcie_stat_size)); 2114 + if (len <= sizeof(struct pcie_ctx_hw_stats)) 2115 + regs->version = 1; 2116 + else if (len < sizeof(struct pcie_ctx_hw_stats_v2)) 2117 + regs->version = 2; 2118 + else 2119 + regs->version = 3; 2120 + 2121 + for (i = 0, j = 0; i < len; ) { 2139 2122 if (i >= bnxt_pcie_32b_entries[j].start && 2140 2123 i <= bnxt_pcie_32b_entries[j].end) { 2141 2124 u32 *dst32 = (u32 *)(dst + i); ··· 5277 5266 return 0; 5278 5267 } 5279 5268 5269 + static void bnxt_hwrm_pcie_qstats(struct bnxt *bp) 5270 + { 5271 + struct hwrm_pcie_qstats_output *resp; 5272 + struct hwrm_pcie_qstats_input *req; 5273 + 5274 + bp->pcie_stat_len = 0; 5275 + if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 5276 + return; 5277 + 5278 + if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 5279 + return; 5280 + 5281 + resp = hwrm_req_hold(bp, req); 5282 + if (__bnxt_hwrm_pcie_qstats(bp, req)) 5283 + bp->pcie_stat_len = min_t(u16, 5284 + le16_to_cpu(resp->pcie_stat_size), 5285 + sizeof(struct pcie_ctx_hw_stats_v2)); 5286 + hwrm_req_drop(bp, req); 5287 + } 5288 + 5280 5289 void bnxt_ethtool_init(struct bnxt *bp) 5281 5290 { 5282 5291 struct hwrm_selftest_qlist_output *resp; ··· 5305 5274 struct net_device *dev = bp->dev; 5306 5275 int i, rc; 5307 5276 5277 + bnxt_hwrm_pcie_qstats(bp); 5308 5278 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 5309 5279 bnxt_get_pkgver(dev); 5310 5280

+253 -62

include/linux/bnxt/hsi.h

··· 276 276 #define HWRM_REG_POWER_QUERY 0xe1UL 277 277 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 278 278 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 279 + #define HWRM_MONITOR_PAX_HISTOGRAM_START 0xe4UL 280 + #define HWRM_MONITOR_PAX_HISTOGRAM_COLLECT 0xe5UL 281 + #define HWRM_STAT_QUERY_ROCE_STATS 0xe6UL 282 + #define HWRM_STAT_QUERY_ROCE_STATS_EXT 0xe7UL 279 283 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 280 284 #define HWRM_WOL_FILTER_FREE 0xf1UL 281 285 #define HWRM_WOL_FILTER_QCFG 0xf2UL ··· 411 407 #define HWRM_FUNC_LAG_UPDATE 0x1b1UL 412 408 #define HWRM_FUNC_LAG_FREE 0x1b2UL 413 409 #define HWRM_FUNC_LAG_QCFG 0x1b3UL 414 - #define HWRM_FUNC_TIMEDTX_PACING_RATE_ADD 0x1c2UL 415 - #define HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE 0x1c3UL 416 - #define HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY 0x1c4UL 410 + #define HWRM_FUNC_TTX_PACING_RATE_PROF_QUERY 0x1c3UL 411 + #define HWRM_FUNC_TTX_PACING_RATE_QUERY 0x1c4UL 417 412 #define HWRM_SELFTEST_QLIST 0x200UL 418 413 #define HWRM_SELFTEST_EXEC 0x201UL 419 414 #define HWRM_SELFTEST_IRQ 0x202UL ··· 444 441 #define HWRM_MFG_WRITE_CERT_NVM 0x21cUL 445 442 #define HWRM_PORT_POE_CFG 0x230UL 446 443 #define HWRM_PORT_POE_QCFG 0x231UL 444 + #define HWRM_PORT_PHY_FDRSTAT 0x232UL 447 445 #define HWRM_UDCC_QCAPS 0x258UL 448 446 #define HWRM_UDCC_CFG 0x259UL 449 447 #define HWRM_UDCC_QCFG 0x25aUL ··· 457 453 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS 0x261UL 458 454 #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG 0x262UL 459 455 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG 0x263UL 456 + #define HWRM_QUEUE_ADPTV_QOS_RX_QCFG 0x264UL 457 + #define HWRM_QUEUE_ADPTV_QOS_TX_QCFG 0x265UL 460 458 #define HWRM_TF 0x2bcUL 461 459 #define HWRM_TF_VERSION_GET 0x2bdUL 462 460 #define HWRM_TF_SESSION_OPEN 0x2c6UL ··· 557 551 #define HWRM_DBG_COREDUMP_CAPTURE 0xff2cUL 558 552 #define HWRM_DBG_PTRACE 0xff2dUL 559 553 #define HWRM_DBG_SIM_CABLE_STATE 0xff2eUL 554 + #define HWRM_DBG_TOKEN_QUERY_AUTH_IDS 0xff2fUL 555 + #define HWRM_DBG_TOKEN_CFG 0xff30UL 560 556 #define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL 561 557 #define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL 562 558 #define HWRM_NVM_DEFRAG 0xffecUL ··· 640 632 #define HWRM_VERSION_MAJOR 1 641 633 #define HWRM_VERSION_MINOR 10 642 634 #define HWRM_VERSION_UPDATE 3 643 - #define HWRM_VERSION_RSVD 97 644 - #define HWRM_VERSION_STR "1.10.3.97" 635 + #define HWRM_VERSION_RSVD 133 636 + #define HWRM_VERSION_STR "1.10.3.133" 645 637 646 638 /* hwrm_ver_get_input (size:192b/24B) */ 647 639 struct hwrm_ver_get_input { ··· 696 688 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 697 689 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 698 690 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_SOC_CAPABLE 0x10000UL 691 + #define VER_GET_RESP_DEV_CAPS_CFG_DEBUG_TOKEN_SUPPORTED 0x20000UL 699 692 u8 roce_fw_maj_8b; 700 693 u8 roce_fw_min_8b; 701 694 u8 roce_fw_bld_8b; ··· 881 872 #define ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE 0x4eUL 882 873 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE 0x4fUL 883 874 #define ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP 0x50UL 884 - #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x51UL 875 + #define ASYNC_EVENT_CMPL_EVENT_ID_ADPTV_QOS 0x51UL 876 + #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x52UL 885 877 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 886 878 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 887 879 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR ··· 1354 1344 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE 0x9UL 1355 1345 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE 0xaUL 1356 1346 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE 0xbUL 1357 - #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE 1347 + #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ERR_QPC_TRACE 0xcUL 1348 + #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ERR_QPC_TRACE 1358 1349 }; 1359 1350 1360 1351 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ ··· 1412 1401 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1413 1402 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1414 1403 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1415 - #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1404 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUP_UDCC_SES 0x7UL 1405 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DB_DROP 0x8UL 1406 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MD_TEMP 0x9UL 1407 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 0xaUL 1408 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 1416 1409 }; 1417 1410 1418 1411 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ ··· 1929 1914 #define FUNC_QCAPS_RESP_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED 0x8UL 1930 1915 #define FUNC_QCAPS_RESP_FLAGS_EXT3_BIDI_OPT_SUPPORTED 0x10UL 1931 1916 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MIRROR_ON_ROCE_SUPPORTED 0x20UL 1917 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_VF_DYN_ALLOC_SUPPORT 0x40UL 1918 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_CHANGE_UDP_SRCPORT_SUPPORT 0x80UL 1919 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_COMPLIANCE_SUPPORTED 0x100UL 1920 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_MULTI_L2_DB_SUPPORTED 0x200UL 1921 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_SECURE_ATS_SUPPORTED 0x400UL 1922 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_MBUF_STATS_SUPPORTED 0x800UL 1932 1923 __le16 max_roce_vfs; 1933 1924 __le16 max_crypto_rx_flow_filters; 1934 1925 u8 unused_3[3]; ··· 1952 1931 u8 unused_0[6]; 1953 1932 }; 1954 1933 1955 - /* hwrm_func_qcfg_output (size:1344b/168B) */ 1934 + /* hwrm_func_qcfg_output (size:1408b/176B) */ 1956 1935 struct hwrm_func_qcfg_output { 1957 1936 __le16 error_code; 1958 1937 __le16 req_type; ··· 2145 2124 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL 2146 2125 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL 2147 2126 __le16 mirror_vnic_id; 2148 - u8 unused_7[7]; 2127 + u8 max_link_width; 2128 + #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_UNKNOWN 0x0UL 2129 + #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X1 0x1UL 2130 + #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X2 0x2UL 2131 + #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X4 0x4UL 2132 + #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X8 0x8UL 2133 + #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X16 0x10UL 2134 + #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_LAST FUNC_QCFG_RESP_MAX_LINK_WIDTH_X16 2135 + u8 max_link_speed; 2136 + #define FUNC_QCFG_RESP_MAX_LINK_SPEED_UNKNOWN 0x0UL 2137 + #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G1 0x1UL 2138 + #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G2 0x2UL 2139 + #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G3 0x3UL 2140 + #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G4 0x4UL 2141 + #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G5 0x5UL 2142 + #define FUNC_QCFG_RESP_MAX_LINK_SPEED_LAST FUNC_QCFG_RESP_MAX_LINK_SPEED_G5 2143 + u8 negotiated_link_width; 2144 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_UNKNOWN 0x0UL 2145 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X1 0x1UL 2146 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X2 0x2UL 2147 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X4 0x4UL 2148 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X8 0x8UL 2149 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X16 0x10UL 2150 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_LAST FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X16 2151 + u8 negotiated_link_speed; 2152 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_UNKNOWN 0x0UL 2153 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G1 0x1UL 2154 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G2 0x2UL 2155 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G3 0x3UL 2156 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G4 0x4UL 2157 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G5 0x5UL 2158 + #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_LAST FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G5 2159 + u8 unused_7[2]; 2160 + u8 pcie_compliance; 2161 + u8 unused_8; 2162 + __le16 l2_db_multi_page_size_kb; 2163 + u8 unused_9[5]; 2149 2164 u8 valid; 2150 2165 }; 2151 2166 ··· 2379 2322 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL 2380 2323 #define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL 2381 2324 #define FUNC_CFG_REQ_ENABLES2_PHYSICAL_SLOT_NUMBER 0x800UL 2325 + #define FUNC_CFG_REQ_ENABLES2_PCIE_COMPLIANCE 0x1000UL 2382 2326 u8 port_kdnet_mode; 2383 2327 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2384 2328 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL ··· 2411 2353 __le16 xid_partition_cfg; 2412 2354 #define FUNC_CFG_REQ_XID_PARTITION_CFG_TX_CK 0x1UL 2413 2355 #define FUNC_CFG_REQ_XID_PARTITION_CFG_RX_CK 0x2UL 2414 - __le16 unused_2; 2356 + u8 pcie_compliance; 2357 + u8 unused_2; 2415 2358 }; 2416 2359 2417 2360 /* hwrm_func_cfg_output (size:128b/16B) */ ··· 2429 2370 struct hwrm_func_cfg_cmd_err { 2430 2371 u8 code; 2431 2372 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2432 - #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 2433 - #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 2434 - #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 2435 - #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 2436 - #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 2373 + #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_OUT_OF_RANGE 0x1UL 2374 + #define FUNC_CFG_CMD_ERR_CODE_NPAR_PARTITION_DOWN_FAILED 0x2UL 2375 + #define FUNC_CFG_CMD_ERR_CODE_TPID_SET_DFLT_VLAN_NOT_SET 0x3UL 2376 + #define FUNC_CFG_CMD_ERR_CODE_RES_ARRAY_ALLOC_FAILED 0x4UL 2377 + #define FUNC_CFG_CMD_ERR_CODE_TX_RING_ASSET_TEST_FAILED 0x5UL 2378 + #define FUNC_CFG_CMD_ERR_CODE_TX_RING_RES_UPDATE_FAILED 0x6UL 2379 + #define FUNC_CFG_CMD_ERR_CODE_APPLY_MAX_BW_FAILED 0x7UL 2380 + #define FUNC_CFG_CMD_ERR_CODE_ENABLE_EVB_FAILED 0x8UL 2381 + #define FUNC_CFG_CMD_ERR_CODE_RSS_CTXT_ASSET_TEST_FAILED 0x9UL 2382 + #define FUNC_CFG_CMD_ERR_CODE_RSS_CTXT_RES_UPDATE_FAILED 0xaUL 2383 + #define FUNC_CFG_CMD_ERR_CODE_CMPL_RING_ASSET_TEST_FAILED 0xbUL 2384 + #define FUNC_CFG_CMD_ERR_CODE_CMPL_RING_RES_UPDATE_FAILED 0xcUL 2385 + #define FUNC_CFG_CMD_ERR_CODE_NQ_ASSET_TEST_FAILED 0xdUL 2386 + #define FUNC_CFG_CMD_ERR_CODE_NQ_RES_UPDATE_FAILED 0xeUL 2387 + #define FUNC_CFG_CMD_ERR_CODE_RX_RING_ASSET_TEST_FAILED 0xfUL 2388 + #define FUNC_CFG_CMD_ERR_CODE_RX_RING_RES_UPDATE_FAILED 0x10UL 2389 + #define FUNC_CFG_CMD_ERR_CODE_VNIC_ASSET_TEST_FAILED 0x11UL 2390 + #define FUNC_CFG_CMD_ERR_CODE_VNIC_RES_UPDATE_FAILED 0x12UL 2391 + #define FUNC_CFG_CMD_ERR_CODE_FAILED_TO_START_STATS_THREAD 0x13UL 2392 + #define FUNC_CFG_CMD_ERR_CODE_RDMA_SRIOV_DISABLED 0x14UL 2393 + #define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_DISABLED 0x15UL 2394 + #define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_ASSET_TEST_FAILED 0x16UL 2395 + #define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_RES_UPDATE_FAILED 0x17UL 2396 + #define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_DISABLED 0x18UL 2397 + #define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_ASSET_TEST_FAILED 0x19UL 2398 + #define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_RES_UPDATE_FAILED 0x1aUL 2399 + #define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_DISABLED 0x1bUL 2400 + #define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_ASSET_TEST_FAILED 0x1cUL 2401 + #define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_RES_UPDATE_FAILED 0x1dUL 2402 + #define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_DISABLED 0x1eUL 2403 + #define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_ASSET_TEST_FAILED 0x1fUL 2404 + #define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_RES_UPDATE_FAILED 0x20UL 2405 + #define FUNC_CFG_CMD_ERR_CODE_INVALID_KDNET_MODE 0x21UL 2406 + #define FUNC_CFG_CMD_ERR_CODE_SCHQ_CFG_FAIL 0x22UL 2407 + #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_SCHQ_CFG_FAIL 2437 2408 u8 unused_0[7]; 2438 2409 }; 2439 2410 ··· 3869 3780 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3870 3781 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3871 3782 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 3783 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL 3872 3784 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3873 3785 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3874 3786 __le16 instance; ··· 3955 3865 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3956 3866 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3957 3867 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 3868 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL 3958 3869 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3959 3870 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3960 3871 __le16 instance; ··· 3995 3904 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA1_TRACE 0x27UL 3996 3905 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA2_TRACE 0x28UL 3997 3906 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 3907 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ERR_QPC_TRACE 0x2aUL 3998 3908 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3999 3909 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 4000 3910 __le16 instance; ··· 4119 4027 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE 0x28UL 4120 4028 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 4121 4029 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 4030 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL 4122 4031 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 4123 4032 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 4124 4033 u8 rsvd[6]; ··· 4163 4070 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA2_TRACE 0x28UL 4164 4071 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 4165 4072 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 4073 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ERR_QPC_TRACE 0x2bUL 4166 4074 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 4167 4075 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 4168 4076 __le16 entry_size; ··· 4310 4216 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 4311 4217 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 4312 4218 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 4219 + #define PORT_PHY_CFG_REQ_FLAGS_LINK_TRAINING_ENABLE 0x800000UL 4220 + #define PORT_PHY_CFG_REQ_FLAGS_LINK_TRAINING_DISABLE 0x1000000UL 4221 + #define PORT_PHY_CFG_REQ_FLAGS_PRECODING_ENABLE 0x2000000UL 4222 + #define PORT_PHY_CFG_REQ_FLAGS_PRECODING_DISABLE 0x4000000UL 4313 4223 __le32 enables; 4314 4224 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 4315 4225 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL ··· 4801 4703 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 4802 4704 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 4803 4705 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL 4706 + #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_LINK_TRAINING 0x8UL 4707 + #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_PRECODING 0x10UL 4804 4708 char phy_vendor_name[16]; 4805 4709 char phy_vendor_partnumber[16]; 4806 4710 __le16 support_pam4_speeds; ··· 4825 4725 u8 link_down_reason; 4826 4726 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL 4827 4727 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION 0x2UL 4728 + #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_CABLE_REMOVED 0x4UL 4729 + #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_MODULE_FAULT 0x8UL 4730 + #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_BMC_REQUEST 0x10UL 4731 + #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_TX_LASER_DISABLED 0x20UL 4828 4732 __le16 support_speeds2; 4829 4733 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL 4830 4734 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL ··· 5986 5882 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5987 5883 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5988 5884 __le16 led0_color_caps; 5989 - #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5990 - #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5991 - #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5885 + #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5886 + #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5887 + #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5888 + #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 5992 5889 u8 led1_id; 5993 5890 u8 led1_type; 5994 5891 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL ··· 6005 5900 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6006 5901 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6007 5902 __le16 led1_color_caps; 6008 - #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 6009 - #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6010 - #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5903 + #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 5904 + #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5905 + #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5906 + #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6011 5907 u8 led2_id; 6012 5908 u8 led2_type; 6013 5909 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL ··· 6024 5918 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6025 5919 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6026 5920 __le16 led2_color_caps; 6027 - #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 6028 - #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6029 - #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5921 + #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 5922 + #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5923 + #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5924 + #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6030 5925 u8 led3_id; 6031 5926 u8 led3_type; 6032 5927 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL ··· 6043 5936 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6044 5937 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6045 5938 __le16 led3_color_caps; 6046 - #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 6047 - #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6048 - #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5939 + #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 5940 + #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5941 + #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5942 + #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6049 5943 u8 unused_4[3]; 6050 5944 u8 valid; 6051 5945 }; ··· 7144 7036 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 7145 7037 struct hwrm_vnic_rss_cfg_cmd_err { 7146 7038 u8 code; 7147 - #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 7148 - #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 7149 - #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 7039 + #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 7040 + #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 7041 + #define VNIC_RSS_CFG_CMD_ERR_CODE_UNABLE_TO_GET_RSS_CFG 0x2UL 7042 + #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_TYPE_UNSUPPORTED 0x3UL 7043 + #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_TYPE_ERR 0x4UL 7044 + #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_MODE_FAIL 0x5UL 7045 + #define VNIC_RSS_CFG_CMD_ERR_CODE_RING_GRP_TABLE_ALLOC_ERR 0x6UL 7046 + #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_KEY_ALLOC_ERR 0x7UL 7047 + #define VNIC_RSS_CFG_CMD_ERR_CODE_DMA_FAILED 0x8UL 7048 + #define VNIC_RSS_CFG_CMD_ERR_CODE_RX_RING_ALLOC_ERR 0x9UL 7049 + #define VNIC_RSS_CFG_CMD_ERR_CODE_CMPL_RING_ALLOC_ERR 0xaUL 7050 + #define VNIC_RSS_CFG_CMD_ERR_CODE_HW_SET_RSS_FAILED 0xbUL 7051 + #define VNIC_RSS_CFG_CMD_ERR_CODE_CTX_INVALID 0xcUL 7052 + #define VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_INVALID 0xdUL 7053 + #define VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_RING_TABLE_PAIR_INVALID 0xeUL 7054 + #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_RING_TABLE_PAIR_INVALID 7150 7055 u8 unused_0[7]; 7151 7056 }; 7152 7057 ··· 7298 7177 u8 valid; 7299 7178 }; 7300 7179 7301 - /* hwrm_ring_alloc_input (size:704b/88B) */ 7180 + /* hwrm_ring_alloc_input (size:768b/96B) */ 7302 7181 struct hwrm_ring_alloc_input { 7303 7182 __le16 req_type; 7304 7183 __le16 cmpl_ring; ··· 7316 7195 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 7317 7196 #define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL 7318 7197 #define RING_ALLOC_REQ_ENABLES_RX_RATE_PROFILE_VALID 0x1000UL 7198 + #define RING_ALLOC_REQ_ENABLES_DPI_VALID 0x2000UL 7319 7199 u8 ring_type; 7320 7200 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 7321 7201 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL ··· 7409 7287 #define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_LAST RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE 7410 7288 u8 unused_4; 7411 7289 __le64 cq_handle; 7290 + __le16 dpi; 7291 + __le16 unused_5[3]; 7412 7292 }; 7413 7293 7414 7294 /* hwrm_ring_alloc_output (size:128b/16B) */ ··· 7900 7776 u8 code; 7901 7777 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 7902 7778 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 7903 - #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 7779 + #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_MAX_VLAN_TAGS 0x2UL 7780 + #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_VNIC_ID 0x3UL 7781 + #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_ACTION 0x4UL 7782 + #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_ACTION 7904 7783 u8 unused_0[7]; 7905 7784 }; 7906 7785 ··· 8236 8109 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 8237 8110 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 8238 8111 u8 code; 8239 - #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8240 - #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 8241 - #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 8112 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8113 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ZERO_MAC 0x65UL 8114 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_BC_MC_MAC 0x66UL 8115 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_VNIC 0x67UL 8116 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_PF_FID 0x68UL 8117 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_L2_CTXT_ID 0x69UL 8118 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_NULL_L2_CTXT_CFG 0x6aUL 8119 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_NULL_L2_DATA_FLD 0x6bUL 8120 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_CFA_LAYOUT 0x6cUL 8121 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_CTXT_ALLOC_FAIL 0x6dUL 8122 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ROCE_FLOW_ERR 0x6eUL 8123 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_OWNER_FID 0x6fUL 8124 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ZERO_REF_CNT 0x70UL 8125 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_FLOW_TYPE 0x71UL 8126 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_IVLAN 0x72UL 8127 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_MAX_VLAN_ID 0x73UL 8128 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_TNL_REQ 0x74UL 8129 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_ADDR 0x75UL 8130 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_IVLAN 0x76UL 8131 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L3_ADDR 0x77UL 8132 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L3_ADDR_TYPE 0x78UL 8133 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_T_L3_ADDR_TYPE 0x79UL 8134 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_DST_VNIC_ID 0x7aUL 8135 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VNI 0x7bUL 8136 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_DST_ID 0x7cUL 8137 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_FAIL_ROCE_L2_FLOW 0x7dUL 8138 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_NPAR_VLAN 0x7eUL 8139 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ATSP_ADD 0x7fUL 8140 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_DFLT_VLAN_FAIL 0x80UL 8141 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_L3_TYPE 0x81UL 8142 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VAL_FAIL_TNL_FLOW 0x82UL 8143 + #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VAL_FAIL_TNL_FLOW 8242 8144 u8 unused_0[7]; 8243 8145 }; 8244 8146 ··· 9337 9181 __le64 pcie_recovery_histogram; 9338 9182 }; 9339 9183 9340 - /* pcie_ctx_hw_stats_v2 (size:4096b/512B) */ 9184 + /* pcie_ctx_hw_stats_v2 (size:4544b/568B) */ 9341 9185 struct pcie_ctx_hw_stats_v2 { 9342 9186 __le64 pcie_pl_signal_integrity; 9343 9187 __le64 pcie_dl_signal_integrity; ··· 9368 9212 __le64 pcie_other_packet_count; 9369 9213 __le64 pcie_blocked_packet_count; 9370 9214 __le64 pcie_cmpl_packet_count; 9215 + __le32 pcie_rd_latency_histogram[12]; 9216 + __le32 pcie_rd_latency_all_normal_count; 9217 + __le32 unused_2; 9371 9218 }; 9372 9219 9373 9220 /* hwrm_stat_generic_qstats_input (size:256b/32B) */ ··· 9565 9406 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 9566 9407 #define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_COUNT 0x12cUL 9567 9408 #define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND 0x12dUL 9568 - #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND 9409 + #define STRUCT_HDR_STRUCT_ID_DBG_TOKEN_CLAIMS 0x190UL 9410 + #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_DBG_TOKEN_CLAIMS 9569 9411 __le16 len; 9570 9412 u8 version; 9571 9413 #define STRUCT_HDR_VERSION_0 0x0UL ··· 9619 9459 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 9620 9460 struct hwrm_fw_set_structured_data_cmd_err { 9621 9461 u8 code; 9622 - #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9623 - #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 9624 - #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 9625 - #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9626 - #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9462 + #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9463 + #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 9464 + #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 9465 + #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9466 + #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_ALREADY_ADDED 0x4UL 9467 + #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_INST_IN_PROG 0x5UL 9468 + #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_INST_IN_PROG 9627 9469 u8 unused_0[7]; 9628 9470 }; 9629 9471 ··· 9649 9487 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 9650 9488 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 9651 9489 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 9652 - #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 9490 + #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_SUPPORTED 0x320UL 9491 + #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_ACTIVE 0x321UL 9492 + #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_ACTIVE 9653 9493 u8 count; 9654 9494 u8 unused_0; 9655 9495 }; ··· 10336 10172 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA2_TRACE 0x9UL 10337 10173 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP1_TRACE 0xaUL 10338 10174 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE 0xbUL 10339 - #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_LAST DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE 10175 + #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ERR_QPC_TRACE 0xcUL 10176 + #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_LAST DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ERR_QPC_TRACE 10340 10177 u8 unused_1[2]; 10341 10178 __le32 flags; 10342 10179 #define DBG_LOG_BUFFER_FLUSH_REQ_FLAGS_FLUSH_ALL_BUFFERS 0x1UL ··· 10460 10295 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 10461 10296 struct hwrm_nvm_write_cmd_err { 10462 10297 u8 code; 10463 - #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 10464 - #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10465 - #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 10466 - #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 10298 + #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 10299 + #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10300 + #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 10301 + #define NVM_WRITE_CMD_ERR_CODE_WRITE_FAILED 0x3UL 10302 + #define NVM_WRITE_CMD_ERR_CODE_REQD_ERASE_FAILED 0x4UL 10303 + #define NVM_WRITE_CMD_ERR_CODE_VERIFY_FAILED 0x5UL 10304 + #define NVM_WRITE_CMD_ERR_CODE_INVALID_HEADER 0x6UL 10305 + #define NVM_WRITE_CMD_ERR_CODE_UPDATE_DIGEST_FAILED 0x7UL 10306 + #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_UPDATE_DIGEST_FAILED 10467 10307 u8 unused_0[7]; 10468 10308 }; 10469 10309 ··· 10608 10438 __le16 srt2_fw_minor; 10609 10439 __le16 srt2_fw_build; 10610 10440 __le16 srt2_fw_patch; 10611 - u8 unused_0[7]; 10441 + u8 security_soc_fw_major; 10442 + u8 security_soc_fw_minor; 10443 + u8 security_soc_fw_build; 10444 + u8 security_soc_fw_patch; 10445 + u8 unused_0[3]; 10612 10446 u8 valid; 10613 10447 }; 10614 10448 ··· 10742 10568 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 10743 10569 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 10744 10570 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL 10745 - #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 10571 + #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_DEFRAG_FAILED 0x5UL 10572 + #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN_DIR_ERR 0x6UL 10573 + #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN_DIR_ERR 10746 10574 u8 unused_0[7]; 10747 10575 }; 10748 10576 ··· 10767 10591 __le16 index_2; 10768 10592 __le16 index_3; 10769 10593 u8 flags; 10770 - #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 10594 + #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 10595 + #define NVM_GET_VARIABLE_REQ_FLAGS_VALIDATE_OPT_VALUE 0x2UL 10771 10596 u8 unused_0; 10772 10597 }; 10773 10598 ··· 10783 10606 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 10784 10607 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 10785 10608 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 10786 - u8 unused_0[3]; 10609 + u8 flags; 10610 + #define NVM_GET_VARIABLE_RESP_FLAGS_VALIDATE_OPT_VALUE 0x1UL 10611 + u8 unused_0[2]; 10787 10612 u8 valid; 10788 10613 }; 10789 10614 10790 10615 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 10791 10616 struct hwrm_nvm_get_variable_cmd_err { 10792 10617 u8 code; 10793 - #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10794 - #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10795 - #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10796 - #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10797 - #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 10618 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10619 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10620 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10621 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10622 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_INDEX_INVALID 0x4UL 10623 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_ACCESS_DENIED 0x5UL 10624 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_CB_FAILED 0x6UL 10625 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x7UL 10626 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x8UL 10627 + #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_NO_MEM 10798 10628 u8 unused_0[7]; 10799 10629 }; 10800 10630 ··· 10851 10667 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 10852 10668 struct hwrm_nvm_set_variable_cmd_err { 10853 10669 u8 code; 10854 - #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10855 - #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10856 - #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10857 - #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 10670 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10671 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10672 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10673 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10674 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_ACTION_NOT_SUPPORTED 0x4UL 10675 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_INDEX_INVALID 0x5UL 10676 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_ACCESS_DENIED 0x6UL 10677 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_CB_FAILED 0x7UL 10678 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x8UL 10679 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x9UL 10680 + #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 10858 10681 u8 unused_0[7]; 10859 10682 }; 10860 10683

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