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phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC

UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init
sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
reusing the G4 init sequence of SM8350.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-13-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul 2a397a23 8d0fb02c

+8
+8
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
··· 768 768 .serdes = sm8350_ufsphy_hs_b_serdes, 769 769 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 770 770 }, 771 + .tbls_hs_g4 = { 772 + .tx = sm8350_ufsphy_g4_tx, 773 + .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 774 + .rx = sm8350_ufsphy_g4_rx, 775 + .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 776 + .pcs = sm8350_ufsphy_g4_pcs, 777 + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 778 + }, 771 779 .clk_list = sdm845_ufs_phy_clk_l, 772 780 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 773 781 .vreg_list = qmp_phy_vreg_l,