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x86/resctrl: Implement resctrl_arch_reset_cntr() and resctrl_arch_cntr_read()

System software reads resctrl event data for a particular resource by writing
the RMID and Event Identifier (EvtID) to the QM_EVTSEL register and then
reading the event data from the QM_CTR register.

In ABMC mode, the event data of a specific counter ID is read by setting the
following fields: QM_EVTSEL.ExtendedEvtID = 1, QM_EVTSEL.EvtID = L3CacheABMC
(=1) and setting QM_EVTSEL.RMID to the desired counter ID. Reading the QM_CTR
then returns the contents of the specified counter ID. RMID_VAL_ERROR bit is
set if the counter configuration is invalid, or if an invalid counter ID is
set in the QM_EVTSEL.RMID field. RMID_VAL_UNAVAIL bit is set if the counter
data is unavailable.

Introduce resctrl_arch_reset_cntr() and resctrl_arch_cntr_read() to reset and
read event data for a specific counter.

Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com

authored by

Babu Moger and committed by
Borislav Petkov (AMD) 2a65b72c 7c9ac605

+75
+6
arch/x86/kernel/cpu/resctrl/internal.h
··· 40 40 /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ 41 41 #define ABMC_ENABLE_BIT 0 42 42 43 + /* 44 + * Qos Event Identifiers. 45 + */ 46 + #define ABMC_EXTENDED_EVT_ID BIT(31) 47 + #define ABMC_EVT_ID BIT(0) 48 + 43 49 /** 44 50 * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs that share 45 51 * a resource for a control function
+69
arch/x86/kernel/cpu/resctrl/monitor.c
··· 259 259 return 0; 260 260 } 261 261 262 + static int __cntr_id_read(u32 cntr_id, u64 *val) 263 + { 264 + u64 msr_val; 265 + 266 + /* 267 + * QM_EVTSEL Register definition: 268 + * ======================================================= 269 + * Bits Mnemonic Description 270 + * ======================================================= 271 + * 63:44 -- Reserved 272 + * 43:32 RMID RMID or counter ID in ABMC mode 273 + * when reading an MBM event 274 + * 31 ExtendedEvtID Extended Event Identifier 275 + * 30:8 -- Reserved 276 + * 7:0 EvtID Event Identifier 277 + * ======================================================= 278 + * The contents of a specific counter can be read by setting the 279 + * following fields in QM_EVTSEL.ExtendedEvtID(=1) and 280 + * QM_EVTSEL.EvtID = L3CacheABMC (=1) and setting QM_EVTSEL.RMID 281 + * to the desired counter ID. Reading the QM_CTR then returns the 282 + * contents of the specified counter. The RMID_VAL_ERROR bit is set 283 + * if the counter configuration is invalid, or if an invalid counter 284 + * ID is set in the QM_EVTSEL.RMID field. The RMID_VAL_UNAVAIL bit 285 + * is set if the counter data is unavailable. 286 + */ 287 + wrmsr(MSR_IA32_QM_EVTSEL, ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, cntr_id); 288 + rdmsrl(MSR_IA32_QM_CTR, msr_val); 289 + 290 + if (msr_val & RMID_VAL_ERROR) 291 + return -EIO; 292 + if (msr_val & RMID_VAL_UNAVAIL) 293 + return -EINVAL; 294 + 295 + *val = msr_val; 296 + return 0; 297 + } 298 + 299 + void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_mon_domain *d, 300 + u32 unused, u32 rmid, int cntr_id, 301 + enum resctrl_event_id eventid) 302 + { 303 + struct rdt_hw_mon_domain *hw_dom = resctrl_to_arch_mon_dom(d); 304 + struct arch_mbm_state *am; 305 + 306 + am = get_arch_mbm_state(hw_dom, rmid, eventid); 307 + if (am) { 308 + memset(am, 0, sizeof(*am)); 309 + 310 + /* Record any initial, non-zero count value. */ 311 + __cntr_id_read(cntr_id, &am->prev_msr); 312 + } 313 + } 314 + 315 + int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_mon_domain *d, 316 + u32 unused, u32 rmid, int cntr_id, 317 + enum resctrl_event_id eventid, u64 *val) 318 + { 319 + u64 msr_val; 320 + int ret; 321 + 322 + ret = __cntr_id_read(cntr_id, &msr_val); 323 + if (ret) 324 + return ret; 325 + 326 + *val = get_corrected_val(r, d, rmid, eventid, msr_val); 327 + 328 + return 0; 329 + } 330 + 262 331 /* 263 332 * The power-on reset value of MSR_RMID_SNC_CONFIG is 0x1 264 333 * which indicates that RMIDs are configured in legacy mode.