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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
clk: mediatek: Add MT8196 mdpsys clock support
Add support for the MT8196 mdpsys clock controller, which provides clock
gate control for MDP.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> # CLK_OPS_PARENT_ENABLE removal
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Laura Nao
and committed by
Stephen Boyd
2a827a7a
d4ecae56
+194
+7
drivers/clk/mediatek/Kconfig
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drivers/clk/mediatek/Kconfig
···
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help
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This driver supports MediaTek MT8196 mcusys clocks.
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config COMMON_CLK_MT8196_MDPSYS
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tristate "Clock driver for MediaTek MT8196 mdpsys"
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depends on COMMON_CLK_MT8196
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default COMMON_CLK_MT8196
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help
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This driver supports MediaTek MT8196 mdpsys clocks.
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config COMMON_CLK_MT8196_PEXTPSYS
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tristate "Clock driver for MediaTek MT8196 pextpsys"
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depends on COMMON_CLK_MT8196
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drivers/clk/mediatek/Makefile
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drivers/clk/mediatek/Makefile
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clk-mt8196-peri_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
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obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
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obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
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drivers/clk/mediatek/clk-mt8196-mdpsys.c
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drivers/clk/mediatek/clk-mt8196-mdpsys.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs mdp0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mdp1_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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static const struct mtk_gate_regs mdp2_cg_regs = {
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.set_ofs = 0x124,
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.clr_ofs = 0x128,
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.sta_ofs = 0x120,
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};
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#define GATE_MDP0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mdp0_cg_regs, \
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.shift = _shift, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_MDP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mdp1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_MDP2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mdp2_cg_regs, \
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.shift = _shift, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate mdp1_clks[] = {
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/* MDP1-0 */
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GATE_MDP0(CLK_MDP1_MDP_MUTEX0, "mdp1_mdp_mutex0", "mdp", 0),
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GATE_MDP0(CLK_MDP1_SMI0, "mdp1_smi0", "mdp", 1),
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GATE_MDP0(CLK_MDP1_APB_BUS, "mdp1_apb_bus", "mdp", 2),
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GATE_MDP0(CLK_MDP1_MDP_RDMA0, "mdp1_mdp_rdma0", "mdp", 3),
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GATE_MDP0(CLK_MDP1_MDP_RDMA1, "mdp1_mdp_rdma1", "mdp", 4),
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GATE_MDP0(CLK_MDP1_MDP_RDMA2, "mdp1_mdp_rdma2", "mdp", 5),
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GATE_MDP0(CLK_MDP1_MDP_BIRSZ0, "mdp1_mdp_birsz0", "mdp", 6),
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GATE_MDP0(CLK_MDP1_MDP_HDR0, "mdp1_mdp_hdr0", "mdp", 7),
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GATE_MDP0(CLK_MDP1_MDP_AAL0, "mdp1_mdp_aal0", "mdp", 8),
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GATE_MDP0(CLK_MDP1_MDP_RSZ0, "mdp1_mdp_rsz0", "mdp", 9),
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GATE_MDP0(CLK_MDP1_MDP_RSZ2, "mdp1_mdp_rsz2", "mdp", 10),
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GATE_MDP0(CLK_MDP1_MDP_TDSHP0, "mdp1_mdp_tdshp0", "mdp", 11),
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GATE_MDP0(CLK_MDP1_MDP_COLOR0, "mdp1_mdp_color0", "mdp", 12),
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GATE_MDP0(CLK_MDP1_MDP_WROT0, "mdp1_mdp_wrot0", "mdp", 13),
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GATE_MDP0(CLK_MDP1_MDP_WROT1, "mdp1_mdp_wrot1", "mdp", 14),
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GATE_MDP0(CLK_MDP1_MDP_WROT2, "mdp1_mdp_wrot2", "mdp", 15),
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GATE_MDP0(CLK_MDP1_MDP_FAKE_ENG0, "mdp1_mdp_fake_eng0", "mdp", 16),
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GATE_MDP0(CLK_MDP1_APB_DB, "mdp1_apb_db", "mdp", 17),
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GATE_MDP0(CLK_MDP1_MDP_DLI_ASYNC0, "mdp1_mdp_dli_async0", "mdp", 18),
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GATE_MDP0(CLK_MDP1_MDP_DLI_ASYNC1, "mdp1_mdp_dli_async1", "mdp", 19),
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GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC0, "mdp1_mdp_dlo_async0", "mdp", 20),
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GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC1, "mdp1_mdp_dlo_async1", "mdp", 21),
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GATE_MDP0(CLK_MDP1_MDP_DLI_ASYNC2, "mdp1_mdp_dli_async2", "mdp", 22),
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GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC2, "mdp1_mdp_dlo_async2", "mdp", 23),
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GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC3, "mdp1_mdp_dlo_async3", "mdp", 24),
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GATE_MDP0(CLK_MDP1_IMG_DL_ASYNC0, "mdp1_img_dl_async0", "mdp", 25),
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GATE_MDP0(CLK_MDP1_MDP_RROT0, "mdp1_mdp_rrot0", "mdp", 26),
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GATE_MDP0(CLK_MDP1_MDP_MERGE0, "mdp1_mdp_merge0", "mdp", 27),
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GATE_MDP0(CLK_MDP1_MDP_C3D0, "mdp1_mdp_c3d0", "mdp", 28),
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GATE_MDP0(CLK_MDP1_MDP_FG0, "mdp1_mdp_fg0", "mdp", 29),
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GATE_MDP0(CLK_MDP1_MDP_CLA2, "mdp1_mdp_cla2", "mdp", 30),
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GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC4, "mdp1_mdp_dlo_async4", "mdp", 31),
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/* MDP1-1 */
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GATE_MDP1(CLK_MDP1_VPP_RSZ0, "mdp1_vpp_rsz0", "mdp", 0),
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GATE_MDP1(CLK_MDP1_VPP_RSZ1, "mdp1_vpp_rsz1", "mdp", 1),
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GATE_MDP1(CLK_MDP1_MDP_DLO_ASYNC5, "mdp1_mdp_dlo_async5", "mdp", 2),
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GATE_MDP1(CLK_MDP1_IMG0, "mdp1_img0", "mdp", 3),
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GATE_MDP1(CLK_MDP1_F26M, "mdp1_f26m", "clk26m", 27),
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/* MDP1-2 */
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GATE_MDP2(CLK_MDP1_IMG_DL_RELAY0, "mdp1_img_dl_relay0", "mdp", 0),
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GATE_MDP2(CLK_MDP1_IMG_DL_RELAY1, "mdp1_img_dl_relay1", "mdp", 8),
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};
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static const struct mtk_clk_desc mdp1_mcd = {
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.clks = mdp1_clks,
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.num_clks = ARRAY_SIZE(mdp1_clks),
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.need_runtime_pm = true,
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};
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static const struct mtk_gate mdp_clks[] = {
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/* MDP0 */
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GATE_MDP0(CLK_MDP_MDP_MUTEX0, "mdp_mdp_mutex0", "mdp", 0),
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GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp", 1),
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GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp", 2),
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GATE_MDP0(CLK_MDP_MDP_RDMA0, "mdp_mdp_rdma0", "mdp", 3),
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GATE_MDP0(CLK_MDP_MDP_RDMA1, "mdp_mdp_rdma1", "mdp", 4),
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GATE_MDP0(CLK_MDP_MDP_RDMA2, "mdp_mdp_rdma2", "mdp", 5),
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GATE_MDP0(CLK_MDP_MDP_BIRSZ0, "mdp_mdp_birsz0", "mdp", 6),
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GATE_MDP0(CLK_MDP_MDP_HDR0, "mdp_mdp_hdr0", "mdp", 7),
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GATE_MDP0(CLK_MDP_MDP_AAL0, "mdp_mdp_aal0", "mdp", 8),
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GATE_MDP0(CLK_MDP_MDP_RSZ0, "mdp_mdp_rsz0", "mdp", 9),
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GATE_MDP0(CLK_MDP_MDP_RSZ2, "mdp_mdp_rsz2", "mdp", 10),
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GATE_MDP0(CLK_MDP_MDP_TDSHP0, "mdp_mdp_tdshp0", "mdp", 11),
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GATE_MDP0(CLK_MDP_MDP_COLOR0, "mdp_mdp_color0", "mdp", 12),
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GATE_MDP0(CLK_MDP_MDP_WROT0, "mdp_mdp_wrot0", "mdp", 13),
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GATE_MDP0(CLK_MDP_MDP_WROT1, "mdp_mdp_wrot1", "mdp", 14),
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GATE_MDP0(CLK_MDP_MDP_WROT2, "mdp_mdp_wrot2", "mdp", 15),
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GATE_MDP0(CLK_MDP_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0", "mdp", 16),
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GATE_MDP0(CLK_MDP_APB_DB, "mdp_apb_db", "mdp", 17),
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GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC0, "mdp_mdp_dli_async0", "mdp", 18),
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GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC1, "mdp_mdp_dli_async1", "mdp", 19),
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GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC0, "mdp_mdp_dlo_async0", "mdp", 20),
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GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC1, "mdp_mdp_dlo_async1", "mdp", 21),
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GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC2, "mdp_mdp_dli_async2", "mdp", 22),
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GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC2, "mdp_mdp_dlo_async2", "mdp", 23),
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GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC3, "mdp_mdp_dlo_async3", "mdp", 24),
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GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "mdp", 25),
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GATE_MDP0(CLK_MDP_MDP_RROT0, "mdp_mdp_rrot0", "mdp", 26),
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GATE_MDP0(CLK_MDP_MDP_MERGE0, "mdp_mdp_merge0", "mdp", 27),
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GATE_MDP0(CLK_MDP_MDP_C3D0, "mdp_mdp_c3d0", "mdp", 28),
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GATE_MDP0(CLK_MDP_MDP_FG0, "mdp_mdp_fg0", "mdp", 29),
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GATE_MDP0(CLK_MDP_MDP_CLA2, "mdp_mdp_cla2", "mdp", 30),
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GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC4, "mdp_mdp_dlo_async4", "mdp", 31),
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/* MDP1 */
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GATE_MDP1(CLK_MDP_VPP_RSZ0, "mdp_vpp_rsz0", "mdp", 0),
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GATE_MDP1(CLK_MDP_VPP_RSZ1, "mdp_vpp_rsz1", "mdp", 1),
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GATE_MDP1(CLK_MDP_MDP_DLO_ASYNC5, "mdp_mdp_dlo_async5", "mdp", 2),
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GATE_MDP1(CLK_MDP_IMG0, "mdp_img0", "mdp", 3),
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GATE_MDP1(CLK_MDP_F26M, "mdp_f26m", "clk26m", 27),
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/* MDP2 */
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GATE_MDP2(CLK_MDP_IMG_DL_RELAY0, "mdp_img_dl_relay0", "mdp", 0),
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GATE_MDP2(CLK_MDP_IMG_DL_RELAY1, "mdp_img_dl_relay1", "mdp", 8),
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};
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static const struct mtk_clk_desc mdp_mcd = {
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.clks = mdp_clks,
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.num_clks = ARRAY_SIZE(mdp_clks),
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.need_runtime_pm = true,
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};
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static const struct of_device_id of_match_clk_mt8196_mdpsys[] = {
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{ .compatible = "mediatek,mt8196-mdpsys0", .data = &mdp_mcd },
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{ .compatible = "mediatek,mt8196-mdpsys1", .data = &mdp1_mcd },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mdpsys);
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static struct platform_driver clk_mt8196_mdpsys_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8196-mdpsys",
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.of_match_table = of_match_clk_mt8196_mdpsys,
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},
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};
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module_platform_driver(clk_mt8196_mdpsys_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 Multimedia Data Path clocks driver");
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MODULE_LICENSE("GPL");