tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk driver fixes from Stephen Boyd:

- Fix qcom mux logic to look at the proper parent table member. Luckily
this clk type isn't very common.

- Don't kill clks on qcom systems that use Trion PLLs that are enabled
out of the bootloader. We will simply skip programming the PLL rate
if it's already done.

- Use the proper clk_ops for the qcom sm6125 ICE clks.

- Use module_platform_driver() in i.MX as it can be a module.

- Fix a UAF in the versatile clk driver on an error path.

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: versatile: clk-icst: use after free on error path
clk: qcom: sm6125-gcc: Swap ops of ice and apps on sdcc1
clk: imx: use module_platform_driver
clk: qcom: clk-alpha-pll: Don't reconfigure running Trion
clk: qcom: regmap-mux: fix parent clock lookup

Linus Torvalds 2acdaf59 a84e0b31

+29 -6
+1 -1
drivers/clk/imx/clk-imx8qxp-lpcg.c
··· 370 370 .probe = imx8qxp_lpcg_clk_probe, 371 371 }; 372 372 373 - builtin_platform_driver(imx8qxp_lpcg_clk_driver); 373 + module_platform_driver(imx8qxp_lpcg_clk_driver); 374 374 375 375 MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>"); 376 376 MODULE_DESCRIPTION("NXP i.MX8QXP LPCG clock driver");
+1 -1
drivers/clk/imx/clk-imx8qxp.c
··· 308 308 }, 309 309 .probe = imx8qxp_clk_probe, 310 310 }; 311 - builtin_platform_driver(imx8qxp_clk_driver); 311 + module_platform_driver(imx8qxp_clk_driver); 312 312 313 313 MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>"); 314 314 MODULE_DESCRIPTION("NXP i.MX8QXP clock driver");
+9
drivers/clk/qcom/clk-alpha-pll.c
··· 1429 1429 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1430 1430 const struct alpha_pll_config *config) 1431 1431 { 1432 + /* 1433 + * If the bootloader left the PLL enabled it's likely that there are 1434 + * RCGs that will lock up if we disable the PLL below. 1435 + */ 1436 + if (trion_pll_is_enabled(pll, regmap)) { 1437 + pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1438 + return; 1439 + } 1440 + 1432 1441 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1433 1442 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1434 1443 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
+1 -1
drivers/clk/qcom/clk-regmap-mux.c
··· 28 28 val &= mask; 29 29 30 30 if (mux->parent_map) 31 - return qcom_find_src_index(hw, mux->parent_map, val); 31 + return qcom_find_cfg_index(hw, mux->parent_map, val); 32 32 33 33 return val; 34 34 }
+12
drivers/clk/qcom/common.c
··· 69 69 } 70 70 EXPORT_SYMBOL_GPL(qcom_find_src_index); 71 71 72 + int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg) 73 + { 74 + int i, num_parents = clk_hw_get_num_parents(hw); 75 + 76 + for (i = 0; i < num_parents; i++) 77 + if (cfg == map[i].cfg) 78 + return i; 79 + 80 + return -ENOENT; 81 + } 82 + EXPORT_SYMBOL_GPL(qcom_find_cfg_index); 83 + 72 84 struct regmap * 73 85 qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc) 74 86 {
+2
drivers/clk/qcom/common.h
··· 49 49 qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count); 50 50 extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, 51 51 u8 src); 52 + extern int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, 53 + u8 cfg); 52 54 53 55 extern int qcom_cc_register_board_clk(struct device *dev, const char *path, 54 56 const char *name, unsigned long rate);
+2 -2
drivers/clk/qcom/gcc-sm6125.c
··· 1121 1121 .name = "gcc_sdcc1_apps_clk_src", 1122 1122 .parent_data = gcc_parent_data_1, 1123 1123 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1124 - .ops = &clk_rcg2_ops, 1124 + .ops = &clk_rcg2_floor_ops, 1125 1125 }, 1126 1126 }; 1127 1127 ··· 1143 1143 .name = "gcc_sdcc1_ice_core_clk_src", 1144 1144 .parent_data = gcc_parent_data_0, 1145 1145 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1146 - .ops = &clk_rcg2_floor_ops, 1146 + .ops = &clk_rcg2_ops, 1147 1147 }, 1148 1148 }; 1149 1149
+1 -1
drivers/clk/versatile/clk-icst.c
··· 543 543 544 544 regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype); 545 545 if (IS_ERR(regclk)) { 546 - kfree(name); 547 546 pr_err("error setting up syscon ICST clock %s\n", name); 547 + kfree(name); 548 548 return; 549 549 } 550 550 of_clk_add_provider(np, of_clk_src_simple_get, regclk);