Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'v5.14-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers
Yaml conversion of grf, pmu and power-domain bindings,
Power-domains for rk3568 + necessary plumbing,
Fixes for the usbphy bindings.
* tag 'v5.14-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
dt-bindings: soc: rockchip: drop unnecessary #phy-cells from grf.yaml
dt-bindings: soc: rockchip: grf: add compatible for RK3308 USB grf
dt-bindings: phy: rename phy nodename in phy-rockchip-inno-usb2.yaml
dt-bindings: soc: rockchip: convert grf.txt to YAML
soc: rockchip: power-domain: add rk3568 powerdomains
dt-bindings: power: rockchip: Add bindings for RK3568 Soc
dt-bindings: power: rockchip: Convert to json-schema
dt-bindings: arm: rockchip: add more compatible strings to pmu.yaml
dt-bindings: arm: rockchip: convert pmu.txt to YAML
soc: rockchip: power-domain: Add a meaningful power domain name
dt-bindings: add power-domain header for RK3568 SoCs
Link: https://lore.kernel.org/r/4647955.GXAFRqVoOG@phil
Signed-off-by: Olof Johansson <olof@lixom.net>
+744
-328
-16
Documentation/devicetree/bindings/arm/rockchip/pmu.txt
-16
Documentation/devicetree/bindings/arm/rockchip/pmu.txt
···
1
-
Rockchip power-management-unit:
2
-
-------------------------------
3
-
4
-
The pmu is used to turn off and on different power domains of the SoCs
5
-
This includes the power to the CPU cores.
6
-
7
-
Required node properties:
8
-
- compatible value : = "rockchip,rk3066-pmu";
9
-
- reg : physical base address and the size of the registers window
10
-
11
-
Example:
12
-
13
-
pmu@20004000 {
14
-
compatible = "rockchip,rk3066-pmu";
15
-
reg = <0x20004000 0x100>;
16
-
};
+55
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
+55
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip Power Management Unit (PMU)
8
+
9
+
maintainers:
10
+
- Elaine Zhang <zhangqing@rock-chips.com>
11
+
- Heiko Stuebner <heiko@sntech.de>
12
+
13
+
description: |
14
+
The PMU is used to turn on and off different power domains of the SoCs.
15
+
This includes the power to the CPU cores.
16
+
17
+
select:
18
+
properties:
19
+
compatible:
20
+
contains:
21
+
enum:
22
+
- rockchip,px30-pmu
23
+
- rockchip,rk3066-pmu
24
+
- rockchip,rk3288-pmu
25
+
- rockchip,rk3399-pmu
26
+
27
+
required:
28
+
- compatible
29
+
30
+
properties:
31
+
compatible:
32
+
items:
33
+
- enum:
34
+
- rockchip,px30-pmu
35
+
- rockchip,rk3066-pmu
36
+
- rockchip,rk3288-pmu
37
+
- rockchip,rk3399-pmu
38
+
- const: syscon
39
+
- const: simple-mfd
40
+
41
+
reg:
42
+
maxItems: 1
43
+
44
+
required:
45
+
- compatible
46
+
- reg
47
+
48
+
additionalProperties: true
49
+
50
+
examples:
51
+
- |
52
+
pmu@20004000 {
53
+
compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
54
+
reg = <0x20004000 0x100>;
55
+
};
+3
-8
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
+3
-8
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
···
29
29
"#clock-cells":
30
30
const: 0
31
31
32
-
"#phy-cells":
33
-
const: 0
34
-
35
32
clocks:
36
33
maxItems: 1
37
34
···
116
119
- reg
117
120
- clock-output-names
118
121
- "#clock-cells"
119
-
- "#phy-cells"
120
122
- host-port
121
123
- otg-port
122
124
···
126
130
#include <dt-bindings/clock/rk3399-cru.h>
127
131
#include <dt-bindings/interrupt-controller/arm-gic.h>
128
132
#include <dt-bindings/interrupt-controller/irq.h>
129
-
u2phy0: usb2-phy@e450 {
133
+
u2phy0: usb2phy@e450 {
130
134
compatible = "rockchip,rk3399-usb2phy";
131
135
reg = <0xe450 0x10>;
132
136
clocks = <&cru SCLK_USB2PHY0_REF>;
133
137
clock-names = "phyclk";
134
138
clock-output-names = "clk_usbphy0_480m";
135
139
#clock-cells = <0>;
136
-
#phy-cells = <0>;
137
140
138
141
u2phy0_host: host-port {
139
-
#phy-cells = <0>;
140
142
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
141
143
interrupt-names = "linestate";
144
+
#phy-cells = <0>;
142
145
};
143
146
144
147
u2phy0_otg: otg-port {
145
-
#phy-cells = <0>;
146
148
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
147
149
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
148
150
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
149
151
interrupt-names = "otg-bvalid", "otg-id", "linestate";
152
+
#phy-cells = <0>;
150
153
};
151
154
};
+248
Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
+248
Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip Power Domains
8
+
9
+
maintainers:
10
+
- Elaine Zhang <zhangqing@rock-chips.com>
11
+
- Heiko Stuebner <heiko@sntech.de>
12
+
13
+
description: |
14
+
Rockchip processors include support for multiple power domains
15
+
which can be powered up/down by software based on different
16
+
application scenarios to save power.
17
+
18
+
Power domains contained within power-controller node are
19
+
generic power domain providers documented in
20
+
Documentation/devicetree/bindings/power/power-domain.yaml.
21
+
22
+
IP cores belonging to a power domain should contain a
23
+
"power-domains" property that is a phandle for the
24
+
power domain node representing the domain.
25
+
26
+
properties:
27
+
$nodename:
28
+
const: power-controller
29
+
30
+
compatible:
31
+
enum:
32
+
- rockchip,px30-power-controller
33
+
- rockchip,rk3036-power-controller
34
+
- rockchip,rk3066-power-controller
35
+
- rockchip,rk3128-power-controller
36
+
- rockchip,rk3188-power-controller
37
+
- rockchip,rk3228-power-controller
38
+
- rockchip,rk3288-power-controller
39
+
- rockchip,rk3328-power-controller
40
+
- rockchip,rk3366-power-controller
41
+
- rockchip,rk3368-power-controller
42
+
- rockchip,rk3399-power-controller
43
+
- rockchip,rk3568-power-controller
44
+
45
+
"#power-domain-cells":
46
+
const: 1
47
+
48
+
"#address-cells":
49
+
const: 1
50
+
51
+
"#size-cells":
52
+
const: 0
53
+
54
+
required:
55
+
- compatible
56
+
- "#power-domain-cells"
57
+
58
+
additionalProperties: false
59
+
60
+
patternProperties:
61
+
"^power-domain@[0-9a-f]+$":
62
+
63
+
$ref: "#/$defs/pd-node"
64
+
65
+
unevaluatedProperties: false
66
+
67
+
properties:
68
+
"#address-cells":
69
+
const: 1
70
+
71
+
"#size-cells":
72
+
const: 0
73
+
74
+
patternProperties:
75
+
"^power-domain@[0-9a-f]+$":
76
+
77
+
$ref: "#/$defs/pd-node"
78
+
79
+
unevaluatedProperties: false
80
+
81
+
properties:
82
+
"#address-cells":
83
+
const: 1
84
+
85
+
"#size-cells":
86
+
const: 0
87
+
88
+
patternProperties:
89
+
"^power-domain@[0-9a-f]+$":
90
+
91
+
$ref: "#/$defs/pd-node"
92
+
93
+
unevaluatedProperties: false
94
+
95
+
properties:
96
+
"#power-domain-cells":
97
+
const: 0
98
+
99
+
$defs:
100
+
pd-node:
101
+
type: object
102
+
description: |
103
+
Represents the power domains within the power controller node.
104
+
105
+
properties:
106
+
reg:
107
+
maxItems: 1
108
+
description: |
109
+
Power domain index. Valid values are defined in
110
+
"include/dt-bindings/power/px30-power.h"
111
+
"include/dt-bindings/power/rk3036-power.h"
112
+
"include/dt-bindings/power/rk3066-power.h"
113
+
"include/dt-bindings/power/rk3128-power.h"
114
+
"include/dt-bindings/power/rk3188-power.h"
115
+
"include/dt-bindings/power/rk3228-power.h"
116
+
"include/dt-bindings/power/rk3288-power.h"
117
+
"include/dt-bindings/power/rk3328-power.h"
118
+
"include/dt-bindings/power/rk3366-power.h"
119
+
"include/dt-bindings/power/rk3368-power.h"
120
+
"include/dt-bindings/power/rk3399-power.h"
121
+
"include/dt-bindings/power/rk3568-power.h"
122
+
123
+
clocks:
124
+
minItems: 1
125
+
maxItems: 30
126
+
description: |
127
+
A number of phandles to clocks that need to be enabled
128
+
while power domain switches state.
129
+
130
+
pm_qos:
131
+
$ref: /schemas/types.yaml#/definitions/phandle-array
132
+
description: |
133
+
A number of phandles to qos blocks which need to be saved and restored
134
+
while power domain switches state.
135
+
136
+
"#power-domain-cells":
137
+
enum: [0, 1]
138
+
description:
139
+
Must be 0 for nodes representing a single PM domain and 1 for nodes
140
+
providing multiple PM domains.
141
+
142
+
required:
143
+
- reg
144
+
- "#power-domain-cells"
145
+
146
+
examples:
147
+
- |
148
+
#include <dt-bindings/clock/rk3399-cru.h>
149
+
#include <dt-bindings/power/rk3399-power.h>
150
+
151
+
soc {
152
+
#address-cells = <2>;
153
+
#size-cells = <2>;
154
+
155
+
qos_hdcp: qos@ffa90000 {
156
+
compatible = "rockchip,rk3399-qos", "syscon";
157
+
reg = <0x0 0xffa90000 0x0 0x20>;
158
+
};
159
+
160
+
qos_iep: qos@ffa98000 {
161
+
compatible = "rockchip,rk3399-qos", "syscon";
162
+
reg = <0x0 0xffa98000 0x0 0x20>;
163
+
};
164
+
165
+
qos_rga_r: qos@ffab0000 {
166
+
compatible = "rockchip,rk3399-qos", "syscon";
167
+
reg = <0x0 0xffab0000 0x0 0x20>;
168
+
};
169
+
170
+
qos_rga_w: qos@ffab0080 {
171
+
compatible = "rockchip,rk3399-qos", "syscon";
172
+
reg = <0x0 0xffab0080 0x0 0x20>;
173
+
};
174
+
175
+
qos_video_m0: qos@ffab8000 {
176
+
compatible = "rockchip,rk3399-qos", "syscon";
177
+
reg = <0x0 0xffab8000 0x0 0x20>;
178
+
};
179
+
180
+
qos_video_m1_r: qos@ffac0000 {
181
+
compatible = "rockchip,rk3399-qos", "syscon";
182
+
reg = <0x0 0xffac0000 0x0 0x20>;
183
+
};
184
+
185
+
qos_video_m1_w: qos@ffac0080 {
186
+
compatible = "rockchip,rk3399-qos", "syscon";
187
+
reg = <0x0 0xffac0080 0x0 0x20>;
188
+
};
189
+
190
+
power-management@ff310000 {
191
+
compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
192
+
reg = <0x0 0xff310000 0x0 0x1000>;
193
+
194
+
power-controller {
195
+
compatible = "rockchip,rk3399-power-controller";
196
+
#power-domain-cells = <1>;
197
+
#address-cells = <1>;
198
+
#size-cells = <0>;
199
+
200
+
/* These power domains are grouped by VD_CENTER */
201
+
power-domain@RK3399_PD_IEP {
202
+
reg = <RK3399_PD_IEP>;
203
+
clocks = <&cru ACLK_IEP>,
204
+
<&cru HCLK_IEP>;
205
+
pm_qos = <&qos_iep>;
206
+
#power-domain-cells = <0>;
207
+
};
208
+
power-domain@RK3399_PD_RGA {
209
+
reg = <RK3399_PD_RGA>;
210
+
clocks = <&cru ACLK_RGA>,
211
+
<&cru HCLK_RGA>;
212
+
pm_qos = <&qos_rga_r>,
213
+
<&qos_rga_w>;
214
+
#power-domain-cells = <0>;
215
+
};
216
+
power-domain@RK3399_PD_VCODEC {
217
+
reg = <RK3399_PD_VCODEC>;
218
+
clocks = <&cru ACLK_VCODEC>,
219
+
<&cru HCLK_VCODEC>;
220
+
pm_qos = <&qos_video_m0>;
221
+
#power-domain-cells = <0>;
222
+
};
223
+
power-domain@RK3399_PD_VDU {
224
+
reg = <RK3399_PD_VDU>;
225
+
clocks = <&cru ACLK_VDU>,
226
+
<&cru HCLK_VDU>;
227
+
pm_qos = <&qos_video_m1_r>,
228
+
<&qos_video_m1_w>;
229
+
#power-domain-cells = <0>;
230
+
};
231
+
power-domain@RK3399_PD_VIO {
232
+
reg = <RK3399_PD_VIO>;
233
+
#power-domain-cells = <1>;
234
+
#address-cells = <1>;
235
+
#size-cells = <0>;
236
+
237
+
power-domain@RK3399_PD_HDCP {
238
+
reg = <RK3399_PD_HDCP>;
239
+
clocks = <&cru ACLK_HDCP>,
240
+
<&cru HCLK_HDCP>,
241
+
<&cru PCLK_HDCP>;
242
+
pm_qos = <&qos_hdcp>;
243
+
#power-domain-cells = <0>;
244
+
};
245
+
};
246
+
};
247
+
};
248
+
};
-61
Documentation/devicetree/bindings/soc/rockchip/grf.txt
-61
Documentation/devicetree/bindings/soc/rockchip/grf.txt
···
1
-
* Rockchip General Register Files (GRF)
2
-
3
-
The general register file will be used to do static set by software, which
4
-
is composed of many registers for system control.
5
-
6
-
From RK3368 SoCs, the GRF is divided into two sections,
7
-
- GRF, used for general non-secure system,
8
-
- SGRF, used for general secure system,
9
-
- PMUGRF, used for always on system
10
-
11
-
On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
12
-
13
-
ON RK3308 SoC, the GRF is divided into four sections:
14
-
- GRF, used for general non-secure system,
15
-
- SGRF, used for general secure system,
16
-
- DETECTGRF, used for audio codec system,
17
-
- COREGRF, used for pvtm,
18
-
19
-
Required Properties:
20
-
21
-
- compatible: GRF should be one of the following:
22
-
- "rockchip,px30-grf", "syscon": for px30
23
-
- "rockchip,rk3036-grf", "syscon": for rk3036
24
-
- "rockchip,rk3066-grf", "syscon": for rk3066
25
-
- "rockchip,rk3188-grf", "syscon": for rk3188
26
-
- "rockchip,rk3228-grf", "syscon": for rk3228
27
-
- "rockchip,rk3288-grf", "syscon": for rk3288
28
-
- "rockchip,rk3308-grf", "syscon": for rk3308
29
-
- "rockchip,rk3328-grf", "syscon": for rk3328
30
-
- "rockchip,rk3368-grf", "syscon": for rk3368
31
-
- "rockchip,rk3399-grf", "syscon": for rk3399
32
-
- "rockchip,rv1108-grf", "syscon": for rv1108
33
-
- compatible: DETECTGRF should be one of the following:
34
-
- "rockchip,rk3308-detect-grf", "syscon": for rk3308
35
-
- compatilbe: COREGRF should be one of the following:
36
-
- "rockchip,rk3308-core-grf", "syscon": for rk3308
37
-
- compatible: PMUGRF should be one of the following:
38
-
- "rockchip,px30-pmugrf", "syscon": for px30
39
-
- "rockchip,rk3368-pmugrf", "syscon": for rk3368
40
-
- "rockchip,rk3399-pmugrf", "syscon": for rk3399
41
-
- compatible: SGRF should be one of the following:
42
-
- "rockchip,rk3288-sgrf", "syscon": for rk3288
43
-
- compatible: USB2PHYGRF should be one of the following:
44
-
- "rockchip,px30-usb2phy-grf", "syscon": for px30
45
-
- "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
46
-
- compatible: USBGRF should be one of the following:
47
-
- "rockchip,rv1108-usbgrf", "syscon": for rv1108
48
-
- reg: physical base address of the controller and length of memory mapped
49
-
region.
50
-
51
-
Example: GRF and PMUGRF of RK3399 SoCs
52
-
53
-
pmugrf: syscon@ff320000 {
54
-
compatible = "rockchip,rk3399-pmugrf", "syscon";
55
-
reg = <0x0 0xff320000 0x0 0x1000>;
56
-
};
57
-
58
-
grf: syscon@ff770000 {
59
-
compatible = "rockchip,rk3399-grf", "syscon";
60
-
reg = <0x0 0xff770000 0x0 0x10000>;
61
-
};
+261
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+261
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip General Register Files (GRF)
8
+
9
+
maintainers:
10
+
- Heiko Stuebner <heiko@sntech.de>
11
+
12
+
properties:
13
+
compatible:
14
+
oneOf:
15
+
- items:
16
+
- enum:
17
+
- rockchip,rk3288-sgrf
18
+
- rockchip,rv1108-pmugrf
19
+
- rockchip,rv1108-usbgrf
20
+
- const: syscon
21
+
- items:
22
+
- enum:
23
+
- rockchip,px30-grf
24
+
- rockchip,px30-pmugrf
25
+
- rockchip,px30-usb2phy-grf
26
+
- rockchip,rk3036-grf
27
+
- rockchip,rk3066-grf
28
+
- rockchip,rk3188-grf
29
+
- rockchip,rk3228-grf
30
+
- rockchip,rk3288-grf
31
+
- rockchip,rk3308-core-grf
32
+
- rockchip,rk3308-detect-grf
33
+
- rockchip,rk3308-grf
34
+
- rockchip,rk3308-usb2phy-grf
35
+
- rockchip,rk3328-grf
36
+
- rockchip,rk3328-usb2phy-grf
37
+
- rockchip,rk3368-grf
38
+
- rockchip,rk3368-pmugrf
39
+
- rockchip,rk3399-grf
40
+
- rockchip,rk3399-pmugrf
41
+
- rockchip,rk3568-grf
42
+
- rockchip,rk3568-pmugrf
43
+
- rockchip,rv1108-grf
44
+
- const: syscon
45
+
- const: simple-mfd
46
+
47
+
reg:
48
+
maxItems: 1
49
+
50
+
"#address-cells":
51
+
const: 1
52
+
53
+
"#size-cells":
54
+
const: 1
55
+
56
+
required:
57
+
- compatible
58
+
- reg
59
+
60
+
additionalProperties:
61
+
type: object
62
+
63
+
allOf:
64
+
- if:
65
+
properties:
66
+
compatible:
67
+
contains:
68
+
const: rockchip,px30-grf
69
+
70
+
then:
71
+
properties:
72
+
lvds:
73
+
description:
74
+
Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
75
+
76
+
- if:
77
+
properties:
78
+
compatible:
79
+
contains:
80
+
const: rockchip,rk3288-grf
81
+
82
+
then:
83
+
properties:
84
+
edp-phy:
85
+
description:
86
+
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
87
+
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
contains:
92
+
enum:
93
+
- rockchip,rk3066-grf
94
+
- rockchip,rk3188-grf
95
+
- rockchip,rk3288-grf
96
+
97
+
then:
98
+
properties:
99
+
usbphy:
100
+
type: object
101
+
102
+
$ref: "/schemas/phy/rockchip-usb-phy.yaml#"
103
+
104
+
unevaluatedProperties: false
105
+
106
+
- if:
107
+
properties:
108
+
compatible:
109
+
contains:
110
+
const: rockchip,rk3328-grf
111
+
112
+
then:
113
+
properties:
114
+
gpio:
115
+
type: object
116
+
117
+
$ref: "/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#"
118
+
119
+
unevaluatedProperties: false
120
+
121
+
power-controller:
122
+
type: object
123
+
124
+
$ref: "/schemas/power/rockchip,power-controller.yaml#"
125
+
126
+
unevaluatedProperties: false
127
+
128
+
- if:
129
+
properties:
130
+
compatible:
131
+
contains:
132
+
const: rockchip,rk3399-grf
133
+
134
+
then:
135
+
properties:
136
+
mipi-dphy-rx0:
137
+
type: object
138
+
139
+
$ref: "/schemas/phy/rockchip-mipi-dphy-rx0.yaml#"
140
+
141
+
unevaluatedProperties: false
142
+
143
+
pcie-phy:
144
+
description:
145
+
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
146
+
147
+
patternProperties:
148
+
"phy@[0-9a-f]+$":
149
+
description:
150
+
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
151
+
152
+
- if:
153
+
properties:
154
+
compatible:
155
+
contains:
156
+
enum:
157
+
- rockchip,px30-pmugrf
158
+
- rockchip,rk3036-grf
159
+
- rockchip,rk3308-grf
160
+
- rockchip,rk3368-pmugrf
161
+
162
+
then:
163
+
properties:
164
+
reboot-mode:
165
+
type: object
166
+
167
+
$ref: "/schemas/power/reset/syscon-reboot-mode.yaml#"
168
+
169
+
unevaluatedProperties: false
170
+
171
+
- if:
172
+
properties:
173
+
compatible:
174
+
contains:
175
+
enum:
176
+
- rockchip,px30-usb2phy-grf
177
+
- rockchip,rk3228-grf
178
+
- rockchip,rk3308-usb2phy-grf
179
+
- rockchip,rk3328-usb2phy-grf
180
+
- rockchip,rk3399-grf
181
+
- rockchip,rv1108-grf
182
+
183
+
then:
184
+
required:
185
+
- "#address-cells"
186
+
- "#size-cells"
187
+
188
+
patternProperties:
189
+
"usb2phy@[0-9a-f]+$":
190
+
type: object
191
+
192
+
$ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#"
193
+
194
+
unevaluatedProperties: false
195
+
196
+
- if:
197
+
properties:
198
+
compatible:
199
+
contains:
200
+
enum:
201
+
- rockchip,px30-pmugrf
202
+
- rockchip,px30-grf
203
+
- rockchip,rk3228-grf
204
+
- rockchip,rk3288-grf
205
+
- rockchip,rk3328-grf
206
+
- rockchip,rk3368-pmugrf
207
+
- rockchip,rk3368-grf
208
+
- rockchip,rk3399-pmugrf
209
+
- rockchip,rk3399-grf
210
+
211
+
then:
212
+
properties:
213
+
io-domains:
214
+
description:
215
+
Documentation/devicetree/bindings/power/rockchip-io-domain.txt
216
+
217
+
examples:
218
+
- |
219
+
#include <dt-bindings/clock/rk3399-cru.h>
220
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
221
+
#include <dt-bindings/power/rk3399-power.h>
222
+
grf: syscon@ff770000 {
223
+
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
224
+
reg = <0xff770000 0x10000>;
225
+
#address-cells = <1>;
226
+
#size-cells = <1>;
227
+
228
+
mipi_dphy_rx0: mipi-dphy-rx0 {
229
+
compatible = "rockchip,rk3399-mipi-dphy-rx0";
230
+
clocks = <&cru SCLK_MIPIDPHY_REF>,
231
+
<&cru SCLK_DPHY_RX0_CFG>,
232
+
<&cru PCLK_VIO_GRF>;
233
+
clock-names = "dphy-ref", "dphy-cfg", "grf";
234
+
power-domains = <&power RK3399_PD_VIO>;
235
+
#phy-cells = <0>;
236
+
};
237
+
238
+
u2phy0: usb2phy@e450 {
239
+
compatible = "rockchip,rk3399-usb2phy";
240
+
reg = <0xe450 0x10>;
241
+
clocks = <&cru SCLK_USB2PHY0_REF>;
242
+
clock-names = "phyclk";
243
+
#clock-cells = <0>;
244
+
clock-output-names = "clk_usbphy0_480m";
245
+
246
+
u2phy0_host: host-port {
247
+
#phy-cells = <0>;
248
+
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
249
+
interrupt-names = "linestate";
250
+
};
251
+
252
+
u2phy0_otg: otg-port {
253
+
#phy-cells = <0>;
254
+
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
255
+
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
256
+
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
257
+
interrupt-names = "otg-bvalid", "otg-id",
258
+
"linestate";
259
+
};
260
+
};
261
+
};
-136
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
-136
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
···
1
-
* Rockchip Power Domains
2
-
3
-
Rockchip processors include support for multiple power domains which can be
4
-
powered up/down by software based on different application scenes to save power.
5
-
6
-
Required properties for power domain controller:
7
-
- compatible: Should be one of the following.
8
-
"rockchip,px30-power-controller" - for PX30 SoCs.
9
-
"rockchip,rk3036-power-controller" - for RK3036 SoCs.
10
-
"rockchip,rk3066-power-controller" - for RK3066 SoCs.
11
-
"rockchip,rk3128-power-controller" - for RK3128 SoCs.
12
-
"rockchip,rk3188-power-controller" - for RK3188 SoCs.
13
-
"rockchip,rk3228-power-controller" - for RK3228 SoCs.
14
-
"rockchip,rk3288-power-controller" - for RK3288 SoCs.
15
-
"rockchip,rk3328-power-controller" - for RK3328 SoCs.
16
-
"rockchip,rk3366-power-controller" - for RK3366 SoCs.
17
-
"rockchip,rk3368-power-controller" - for RK3368 SoCs.
18
-
"rockchip,rk3399-power-controller" - for RK3399 SoCs.
19
-
- #power-domain-cells: Number of cells in a power-domain specifier.
20
-
Should be 1 for multiple PM domains.
21
-
- #address-cells: Should be 1.
22
-
- #size-cells: Should be 0.
23
-
24
-
Required properties for power domain sub nodes:
25
-
- reg: index of the power domain, should use macros in:
26
-
"include/dt-bindings/power/px30-power.h" - for PX30 type power domain.
27
-
"include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain.
28
-
"include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain.
29
-
"include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain.
30
-
"include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain.
31
-
"include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain.
32
-
"include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
33
-
"include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain.
34
-
"include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain.
35
-
"include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain.
36
-
"include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain.
37
-
- clocks (optional): phandles to clocks which need to be enabled while power domain
38
-
switches state.
39
-
- pm_qos (optional): phandles to qos blocks which need to be saved and restored
40
-
while power domain switches state.
41
-
42
-
Qos Example:
43
-
44
-
qos_gpu: qos_gpu@ffaf0000 {
45
-
compatible ="syscon";
46
-
reg = <0x0 0xffaf0000 0x0 0x20>;
47
-
};
48
-
49
-
Example:
50
-
51
-
power: power-controller {
52
-
compatible = "rockchip,rk3288-power-controller";
53
-
#power-domain-cells = <1>;
54
-
#address-cells = <1>;
55
-
#size-cells = <0>;
56
-
57
-
pd_gpu {
58
-
reg = <RK3288_PD_GPU>;
59
-
clocks = <&cru ACLK_GPU>;
60
-
pm_qos = <&qos_gpu>;
61
-
};
62
-
};
63
-
64
-
power: power-controller {
65
-
compatible = "rockchip,rk3368-power-controller";
66
-
#power-domain-cells = <1>;
67
-
#address-cells = <1>;
68
-
#size-cells = <0>;
69
-
70
-
pd_gpu_1 {
71
-
reg = <RK3368_PD_GPU_1>;
72
-
clocks = <&cru ACLK_GPU_CFG>;
73
-
};
74
-
};
75
-
76
-
Example 2:
77
-
power: power-controller {
78
-
compatible = "rockchip,rk3399-power-controller";
79
-
#power-domain-cells = <1>;
80
-
#address-cells = <1>;
81
-
#size-cells = <0>;
82
-
83
-
pd_vio {
84
-
#address-cells = <1>;
85
-
#size-cells = <0>;
86
-
reg = <RK3399_PD_VIO>;
87
-
88
-
pd_vo {
89
-
#address-cells = <1>;
90
-
#size-cells = <0>;
91
-
reg = <RK3399_PD_VO>;
92
-
93
-
pd_vopb {
94
-
reg = <RK3399_PD_VOPB>;
95
-
};
96
-
97
-
pd_vopl {
98
-
reg = <RK3399_PD_VOPL>;
99
-
};
100
-
};
101
-
};
102
-
};
103
-
104
-
Node of a device using power domains must have a power-domains property,
105
-
containing a phandle to the power device node and an index specifying which
106
-
power domain to use.
107
-
The index should use macros in:
108
-
"include/dt-bindings/power/px30-power.h" - for px30 type power domain.
109
-
"include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain.
110
-
"include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain.
111
-
"include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain.
112
-
"include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
113
-
"include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain.
114
-
"include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain.
115
-
"include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain.
116
-
"include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain.
117
-
118
-
Example of the node using power domain:
119
-
120
-
node {
121
-
/* ... */
122
-
power-domains = <&power RK3288_PD_GPU>;
123
-
/* ... */
124
-
};
125
-
126
-
node {
127
-
/* ... */
128
-
power-domains = <&power RK3368_PD_GPU_1>;
129
-
/* ... */
130
-
};
131
-
132
-
node {
133
-
/* ... */
134
-
power-domains = <&power RK3399_PD_VOPB>;
135
-
/* ... */
136
-
};
+145
-107
drivers/soc/rockchip/pm_domains.c
+145
-107
drivers/soc/rockchip/pm_domains.c
···
27
27
#include <dt-bindings/power/rk3366-power.h>
28
28
#include <dt-bindings/power/rk3368-power.h>
29
29
#include <dt-bindings/power/rk3399-power.h>
30
+
#include <dt-bindings/power/rk3568-power.h>
30
31
31
32
struct rockchip_domain_info {
33
+
const char *name;
32
34
int pwr_mask;
33
35
int status_mask;
34
36
int req_mask;
···
87
85
88
86
#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
89
87
90
-
#define DOMAIN(pwr, status, req, idle, ack, wakeup) \
88
+
#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
91
89
{ \
90
+
.name = _name, \
92
91
.pwr_mask = (pwr), \
93
92
.status_mask = (status), \
94
93
.req_mask = (req), \
···
98
95
.active_wakeup = (wakeup), \
99
96
}
100
97
101
-
#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \
98
+
#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
102
99
{ \
100
+
.name = _name, \
103
101
.pwr_w_mask = (pwr) << 16, \
104
102
.pwr_mask = (pwr), \
105
103
.status_mask = (status), \
···
111
107
.active_wakeup = wakeup, \
112
108
}
113
109
114
-
#define DOMAIN_RK3036(req, ack, idle, wakeup) \
110
+
#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
115
111
{ \
112
+
.name = _name, \
116
113
.req_mask = (req), \
117
114
.req_w_mask = (req) << 16, \
118
115
.ack_mask = (ack), \
···
121
116
.active_wakeup = wakeup, \
122
117
}
123
118
124
-
#define DOMAIN_PX30(pwr, status, req, wakeup) \
125
-
DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup)
119
+
#define DOMAIN_PX30(name, pwr, status, req, wakeup) \
120
+
DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
126
121
127
-
#define DOMAIN_RK3288(pwr, status, req, wakeup) \
128
-
DOMAIN(pwr, status, req, req, (req) << 16, wakeup)
122
+
#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
123
+
DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
129
124
130
-
#define DOMAIN_RK3328(pwr, status, req, wakeup) \
131
-
DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup)
125
+
#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
126
+
DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
132
127
133
-
#define DOMAIN_RK3368(pwr, status, req, wakeup) \
134
-
DOMAIN(pwr, status, req, (req) << 16, req, wakeup)
128
+
#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
129
+
DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
135
130
136
-
#define DOMAIN_RK3399(pwr, status, req, wakeup) \
137
-
DOMAIN(pwr, status, req, req, req, wakeup)
131
+
#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
132
+
DOMAIN(name, pwr, status, req, req, req, wakeup)
133
+
134
+
#define DOMAIN_RK3568(name, pwr, req, wakeup) \
135
+
DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
138
136
139
137
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
140
138
{
···
498
490
goto err_unprepare_clocks;
499
491
}
500
492
501
-
pd->genpd.name = node->name;
493
+
if (pd->info->name)
494
+
pd->genpd.name = pd->info->name;
495
+
else
496
+
pd->genpd.name = kbasename(node->full_name);
502
497
pd->genpd.power_off = rockchip_pd_power_off;
503
498
pd->genpd.power_on = rockchip_pd_power_on;
504
499
pd->genpd.attach_dev = rockchip_pd_attach_dev;
···
727
716
}
728
717
729
718
static const struct rockchip_domain_info px30_pm_domains[] = {
730
-
[PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false),
731
-
[PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false),
732
-
[PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false),
733
-
[PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false),
734
-
[PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false),
735
-
[PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false),
736
-
[PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false),
737
-
[PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false),
719
+
[PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
720
+
[PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
721
+
[PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
722
+
[PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
723
+
[PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
724
+
[PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
725
+
[PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
726
+
[PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
738
727
};
739
728
740
729
static const struct rockchip_domain_info rk3036_pm_domains[] = {
741
-
[RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true),
742
-
[RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false),
743
-
[RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false),
744
-
[RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false),
745
-
[RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false),
746
-
[RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false),
747
-
[RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false),
730
+
[RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
731
+
[RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
732
+
[RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
733
+
[RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
734
+
[RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
735
+
[RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
736
+
[RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
748
737
};
749
738
750
739
static const struct rockchip_domain_info rk3066_pm_domains[] = {
751
-
[RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
752
-
[RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
753
-
[RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
754
-
[RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
755
-
[RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false),
740
+
[RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
741
+
[RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
742
+
[RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
743
+
[RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
744
+
[RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
756
745
};
757
746
758
747
static const struct rockchip_domain_info rk3128_pm_domains[] = {
759
-
[RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false),
760
-
[RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true),
761
-
[RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false),
762
-
[RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false),
763
-
[RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false),
748
+
[RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
749
+
[RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
750
+
[RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
751
+
[RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
752
+
[RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
764
753
};
765
754
766
755
static const struct rockchip_domain_info rk3188_pm_domains[] = {
767
-
[RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
768
-
[RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
769
-
[RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
770
-
[RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
771
-
[RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
756
+
[RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
757
+
[RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
758
+
[RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
759
+
[RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
760
+
[RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
772
761
};
773
762
774
763
static const struct rockchip_domain_info rk3228_pm_domains[] = {
775
-
[RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true),
776
-
[RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true),
777
-
[RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true),
778
-
[RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true),
779
-
[RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false),
780
-
[RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false),
781
-
[RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false),
782
-
[RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false),
783
-
[RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false),
784
-
[RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true),
785
-
[RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false),
764
+
[RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
765
+
[RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
766
+
[RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
767
+
[RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
768
+
[RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
769
+
[RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
770
+
[RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
771
+
[RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
772
+
[RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
773
+
[RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
774
+
[RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
786
775
};
787
776
788
777
static const struct rockchip_domain_info rk3288_pm_domains[] = {
789
-
[RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false),
790
-
[RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false),
791
-
[RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false),
792
-
[RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false),
778
+
[RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
779
+
[RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
780
+
[RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
781
+
[RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
793
782
};
794
783
795
784
static const struct rockchip_domain_info rk3328_pm_domains[] = {
796
-
[RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false),
797
-
[RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false),
798
-
[RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true),
799
-
[RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true),
800
-
[RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true),
801
-
[RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false),
802
-
[RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false),
803
-
[RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false),
804
-
[RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false),
785
+
[RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
786
+
[RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
787
+
[RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
788
+
[RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
789
+
[RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
790
+
[RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
791
+
[RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
792
+
[RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
793
+
[RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
805
794
};
806
795
807
796
static const struct rockchip_domain_info rk3366_pm_domains[] = {
808
-
[RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true),
809
-
[RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false),
810
-
[RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false),
811
-
[RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false),
812
-
[RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false),
813
-
[RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false),
814
-
[RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false),
797
+
[RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
798
+
[RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
799
+
[RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
800
+
[RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
801
+
[RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
802
+
[RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
803
+
[RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
815
804
};
816
805
817
806
static const struct rockchip_domain_info rk3368_pm_domains[] = {
818
-
[RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true),
819
-
[RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false),
820
-
[RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false),
821
-
[RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false),
822
-
[RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false),
807
+
[RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
808
+
[RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
809
+
[RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
810
+
[RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
811
+
[RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
823
812
};
824
813
825
814
static const struct rockchip_domain_info rk3399_pm_domains[] = {
826
-
[RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false),
827
-
[RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false),
828
-
[RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true),
829
-
[RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true),
830
-
[RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true),
831
-
[RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true),
832
-
[RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true),
833
-
[RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true),
834
-
[RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false),
835
-
[RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false),
836
-
[RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false),
837
-
[RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false),
838
-
[RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false),
839
-
[RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false),
840
-
[RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false),
841
-
[RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false),
842
-
[RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false),
843
-
[RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false),
844
-
[RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false),
845
-
[RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false),
846
-
[RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true),
847
-
[RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true),
848
-
[RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true),
849
-
[RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false),
850
-
[RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true),
851
-
[RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true),
852
-
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true),
815
+
[RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
816
+
[RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
817
+
[RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
818
+
[RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
819
+
[RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
820
+
[RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
821
+
[RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
822
+
[RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
823
+
[RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
824
+
[RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
825
+
[RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
826
+
[RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
827
+
[RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
828
+
[RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
829
+
[RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
830
+
[RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
831
+
[RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
832
+
[RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
833
+
[RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
834
+
[RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
835
+
[RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
836
+
[RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
837
+
[RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
838
+
[RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
839
+
[RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
840
+
[RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
841
+
[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
842
+
};
843
+
844
+
static const struct rockchip_domain_info rk3568_pm_domains[] = {
845
+
[RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
846
+
[RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
847
+
[RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
848
+
[RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
849
+
[RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
850
+
[RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
851
+
[RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
852
+
[RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
853
+
[RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
853
854
};
854
855
855
856
static const struct rockchip_pmu_info px30_pmu = {
···
999
976
.domain_info = rk3399_pm_domains,
1000
977
};
1001
978
979
+
static const struct rockchip_pmu_info rk3568_pmu = {
980
+
.pwr_offset = 0xa0,
981
+
.status_offset = 0x98,
982
+
.req_offset = 0x50,
983
+
.idle_offset = 0x68,
984
+
.ack_offset = 0x60,
985
+
986
+
.num_domains = ARRAY_SIZE(rk3568_pm_domains),
987
+
.domain_info = rk3568_pm_domains,
988
+
};
989
+
1002
990
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1003
991
{
1004
992
.compatible = "rockchip,px30-power-controller",
···
1054
1020
{
1055
1021
.compatible = "rockchip,rk3399-power-controller",
1056
1022
.data = (void *)&rk3399_pmu,
1023
+
},
1024
+
{
1025
+
.compatible = "rockchip,rk3568-power-controller",
1026
+
.data = (void *)&rk3568_pmu,
1057
1027
},
1058
1028
{ /* sentinel */ },
1059
1029
};
+32
include/dt-bindings/power/rk3568-power.h
+32
include/dt-bindings/power/rk3568-power.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
3
+
#define __DT_BINDINGS_POWER_RK3568_POWER_H__
4
+
5
+
/* VD_CORE */
6
+
#define RK3568_PD_CPU_0 0
7
+
#define RK3568_PD_CPU_1 1
8
+
#define RK3568_PD_CPU_2 2
9
+
#define RK3568_PD_CPU_3 3
10
+
#define RK3568_PD_CORE_ALIVE 4
11
+
12
+
/* VD_PMU */
13
+
#define RK3568_PD_PMU 5
14
+
15
+
/* VD_NPU */
16
+
#define RK3568_PD_NPU 6
17
+
18
+
/* VD_GPU */
19
+
#define RK3568_PD_GPU 7
20
+
21
+
/* VD_LOGIC */
22
+
#define RK3568_PD_VI 8
23
+
#define RK3568_PD_VO 9
24
+
#define RK3568_PD_RGA 10
25
+
#define RK3568_PD_VPU 11
26
+
#define RK3568_PD_CENTER 12
27
+
#define RK3568_PD_RKVDEC 13
28
+
#define RK3568_PD_RKVENC 14
29
+
#define RK3568_PD_PIPE 15
30
+
#define RK3568_PD_LOGIC_ALIVE 16
31
+
32
+
#endif