drm/amdgpu: Enable devcoredump for JPEG4_0_5

Add register list and enable devcoredump for JPEG4_0_5

V2: (Lijo)
- remove version specific callbacks and use simplified helper functions

V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Sathishkumar S and committed by

Alex Deucher 1 year ago 2b0ccf39 c3dddd60

+24 -1

1 changed file

expand all

drivers

gpu

drm

amd

amdgpu

jpeg_v4_0_5.c

+24 -1

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

··· 46 46 #define regJPEG_CGC_GATE_INTERNAL_OFFSET 0x4160 47 47 #define regUVD_NO_OP_INTERNAL_OFFSET 0x0029 48 48 49 + static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0_5[] = { 50 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), 51 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), 52 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR), 53 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR), 54 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL), 55 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE), 56 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS), 57 + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), 58 + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), 59 + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), 60 + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), 61 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), 62 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), 63 + }; 64 + 49 65 static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev); 50 66 static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); 51 67 static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block, 52 68 enum amd_powergating_state state); 53 - 54 69 static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring); 55 70 56 71 static int amdgpu_ih_clientid_jpeg[] = { 57 72 SOC15_IH_CLIENTID_VCN, 58 73 SOC15_IH_CLIENTID_VCN1 59 74 }; 75 + 76 + 60 77 61 78 /** 62 79 * jpeg_v4_0_5_early_init - set function pointers ··· 169 152 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 170 153 adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH); 171 154 } 155 + 156 + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_5, ARRAY_SIZE(jpeg_reg_list_4_0_5)); 157 + if (r) 158 + return r; 172 159 173 160 /* TODO: Add queue reset mask when FW fully supports it */ 174 161 adev->jpeg.supported_reset = ··· 780 759 .wait_for_idle = jpeg_v4_0_5_wait_for_idle, 781 760 .set_clockgating_state = jpeg_v4_0_5_set_clockgating_state, 782 761 .set_powergating_state = jpeg_v4_0_5_set_powergating_state, 762 + .dump_ip_state = amdgpu_jpeg_dump_ip_state, 763 + .print_ip_state = amdgpu_jpeg_print_ip_state, 783 764 }; 784 765 785 766 static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {

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