net/mlx5: LAG, use xa_alloc to manage LAG device indices

+192 -52

drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c

··· 288 288 289 289 kref_init(&ldev->ref); 290 290 mutex_init(&ldev->lock); 291 - xa_init(&ldev->pfs); 291 + xa_init_flags(&ldev->pfs, XA_FLAGS_ALLOC); 292 292 INIT_DELAYED_WORK(&ldev->bond_work, mlx5_do_bond_work); 293 293 INIT_WORK(&ldev->speed_update_work, mlx5_mpesw_speed_update_work); 294 294 ··· 326 326 return -ENOENT; 327 327 } 328 328 329 - int mlx5_lag_get_dev_index_by_seq(struct mlx5_lag *ldev, int seq) 329 + static int mlx5_lag_get_master_idx(struct mlx5_lag *ldev) 330 330 { 331 - int i, num = 0; 331 + unsigned long idx = 0; 332 + void *entry; 332 333 333 334 if (!ldev) 334 335 return -ENOENT; 335 336 337 + entry = xa_find(&ldev->pfs, &idx, U8_MAX, MLX5_LAG_XA_MARK_MASTER); 338 + if (!entry) 339 + return -ENOENT; 340 + 341 + return (int)idx; 342 + } 343 + 344 + int mlx5_lag_get_dev_index_by_seq(struct mlx5_lag *ldev, int seq) 345 + { 346 + int master_idx, i, num = 0; 347 + 348 + if (!ldev) 349 + return -ENOENT; 350 + 351 + master_idx = mlx5_lag_get_master_idx(ldev); 352 + 353 + /* If seq 0 is requested and there's a primary PF, return it */ 354 + if (master_idx >= 0) { 355 + if (seq == 0) 356 + return master_idx; 357 + num++; 358 + } 359 + 336 360 mlx5_ldev_for_each(i, 0, ldev) { 361 + /* Skip the primary PF in the loop */ 362 + if (i == master_idx) 363 + continue; 364 + 337 365 if (num == seq) 338 366 return i; 339 367 num++; 340 368 } 341 369 return -ENOENT; 370 + } 371 + 372 + /* Devcom events for LAG master marking */ 373 + #define LAG_DEVCOM_PAIR (0) 374 + #define LAG_DEVCOM_UNPAIR (1) 375 + 376 + static void mlx5_lag_mark_master(struct mlx5_lag *ldev) 377 + { 378 + int lowest_dev_idx = INT_MAX; 379 + struct lag_func *pf; 380 + int master_xa_idx = -1; 381 + int dev_idx; 382 + int i; 383 + 384 + mlx5_ldev_for_each(i, 0, ldev) { 385 + pf = mlx5_lag_pf(ldev, i); 386 + dev_idx = mlx5_get_dev_index(pf->dev); 387 + if (dev_idx < lowest_dev_idx) { 388 + lowest_dev_idx = dev_idx; 389 + master_xa_idx = i; 390 + } 391 + } 392 + 393 + if (master_xa_idx >= 0) 394 + xa_set_mark(&ldev->pfs, master_xa_idx, MLX5_LAG_XA_MARK_MASTER); 395 + } 396 + 397 + static void mlx5_lag_clear_master(struct mlx5_lag *ldev) 398 + { 399 + unsigned long idx = 0; 400 + void *entry; 401 + 402 + entry = xa_find(&ldev->pfs, &idx, U8_MAX, MLX5_LAG_XA_MARK_MASTER); 403 + if (!entry) 404 + return; 405 + 406 + xa_clear_mark(&ldev->pfs, idx, MLX5_LAG_XA_MARK_MASTER); 407 + } 408 + 409 + /* Devcom event handler to manage LAG master marking */ 410 + static int mlx5_lag_devcom_event(int event, void *my_data, void *event_data) 411 + { 412 + struct mlx5_core_dev *dev = my_data; 413 + struct mlx5_lag *ldev; 414 + int idx; 415 + 416 + ldev = mlx5_lag_dev(dev); 417 + if (!ldev) 418 + return 0; 419 + 420 + mutex_lock(&ldev->lock); 421 + switch (event) { 422 + case LAG_DEVCOM_PAIR: 423 + /* No need to mark more than once */ 424 + idx = mlx5_lag_get_master_idx(ldev); 425 + if (idx >= 0) 426 + break; 427 + /* Check if all LAG ports are now registered */ 428 + if (mlx5_lag_num_devs(ldev) == ldev->ports) 429 + mlx5_lag_mark_master(ldev); 430 + break; 431 + 432 + case LAG_DEVCOM_UNPAIR: 433 + /* Clear master mark when a device is removed */ 434 + mlx5_lag_clear_master(ldev); 435 + break; 436 + } 437 + mutex_unlock(&ldev->lock); 438 + return 0; 342 439 } 343 440 344 441 int mlx5_lag_num_devs(struct mlx5_lag *ldev) ··· 508 411 509 412 /* Use native mapping by default where each port's buckets 510 413 * point the native port: 1 1 1 .. 1 2 2 2 ... 2 3 3 3 ... 3 etc 414 + * ports[] values are 1-indexed device indices for FW. 511 415 */ 512 416 mlx5_ldev_for_each(i, 0, ldev) { 513 417 for (j = 0; j < buckets; j++) { 514 418 idx = i * buckets + j; 515 - ports[idx] = i + 1; 419 + ports[idx] = mlx5_lag_xa_to_dev_idx(ldev, i) + 1; 516 420 } 517 421 } 518 422 ··· 525 427 /* Go over the disabled ports and for each assign a random active port */ 526 428 for (i = 0; i < disabled_ports_num; i++) { 527 429 for (j = 0; j < buckets; j++) { 430 + int rand_xa_idx; 431 + 528 432 get_random_bytes(&rand, 4); 529 - ports[disabled[i] * buckets + j] = enabled[rand % enabled_ports_num] + 1; 433 + rand_xa_idx = enabled[rand % enabled_ports_num]; 434 + ports[disabled[i] * buckets + j] = 435 + mlx5_lag_xa_to_dev_idx(ldev, rand_xa_idx) + 1; 530 436 } 531 437 } 532 438 } ··· 785 683 786 684 static int mlx5_lag_create_single_fdb(struct mlx5_lag *ldev) 787 685 { 788 - int first_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 686 + int master_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 789 687 struct mlx5_eswitch *master_esw; 790 688 struct mlx5_core_dev *dev0; 791 689 int i, j; 792 690 int err; 793 691 794 - if (first_idx < 0) 692 + if (master_idx < 0) 795 693 return -EINVAL; 796 694 797 - dev0 = mlx5_lag_pf(ldev, first_idx)->dev; 695 + dev0 = mlx5_lag_pf(ldev, master_idx)->dev; 798 696 master_esw = dev0->priv.eswitch; 799 - mlx5_ldev_for_each(i, first_idx + 1, ldev) { 697 + mlx5_ldev_for_each(i, 0, ldev) { 800 698 struct mlx5_eswitch *slave_esw; 699 + 700 + if (i == master_idx) 701 + continue; 801 702 802 703 slave_esw = mlx5_lag_pf(ldev, i)->dev->priv.eswitch; 803 704 ··· 811 706 } 812 707 return 0; 813 708 err: 814 - mlx5_ldev_for_each_reverse(j, i, first_idx + 1, ldev) 709 + mlx5_ldev_for_each_reverse(j, i, 0, ldev) { 710 + if (j == master_idx) 711 + continue; 815 712 mlx5_eswitch_offloads_single_fdb_del_one(master_esw, 816 713 mlx5_lag_pf(ldev, j)->dev->priv.eswitch); 714 + } 817 715 return err; 818 716 } 819 717 ··· 825 717 enum mlx5_lag_mode mode, 826 718 unsigned long flags) 827 719 { 828 - bool shared_fdb = test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &flags); 829 720 int first_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 721 + bool shared_fdb = test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &flags); 830 722 u32 in[MLX5_ST_SZ_DW(destroy_lag_in)] = {}; 831 723 struct mlx5_core_dev *dev0; 832 724 int err; ··· 872 764 enum mlx5_lag_mode mode, 873 765 bool shared_fdb) 874 766 { 875 - int first_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 876 767 bool roce_lag = mode == MLX5_LAG_MODE_ROCE; 877 768 struct mlx5_core_dev *dev0; 878 769 unsigned long flags = 0; 770 + int master_idx; 879 771 int err; 880 772 881 - if (first_idx < 0) 773 + master_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 774 + if (master_idx < 0) 882 775 return -EINVAL; 883 776 884 - dev0 = mlx5_lag_pf(ldev, first_idx)->dev; 777 + dev0 = mlx5_lag_pf(ldev, master_idx)->dev; 885 778 err = mlx5_lag_set_flags(ldev, mode, tracker, shared_fdb, &flags); 886 779 if (err) 887 780 return err; ··· 926 817 927 818 int mlx5_deactivate_lag(struct mlx5_lag *ldev) 928 819 { 929 - int first_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 820 + int master_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 930 821 u32 in[MLX5_ST_SZ_DW(destroy_lag_in)] = {}; 931 822 bool roce_lag = __mlx5_lag_is_roce(ldev); 932 823 unsigned long flags = ldev->mode_flags; ··· 935 826 int err; 936 827 int i; 937 828 938 - if (first_idx < 0) 829 + if (master_idx < 0) 939 830 return -EINVAL; 940 831 941 - dev0 = mlx5_lag_pf(ldev, first_idx)->dev; 832 + dev0 = mlx5_lag_pf(ldev, master_idx)->dev; 942 833 master_esw = dev0->priv.eswitch; 943 834 ldev->mode = MLX5_LAG_MODE_NONE; 944 835 ldev->mode_flags = 0; 945 836 mlx5_lag_mp_reset(ldev); 946 837 947 838 if (test_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &flags)) { 948 - mlx5_ldev_for_each(i, first_idx + 1, ldev) 839 + mlx5_ldev_for_each(i, 0, ldev) { 840 + if (i == master_idx) 841 + continue; 949 842 mlx5_eswitch_offloads_single_fdb_del_one(master_esw, 950 843 mlx5_lag_pf(ldev, i)->dev->priv.eswitch); 844 + } 951 845 clear_bit(MLX5_LAG_MODE_FLAG_SHARED_FDB, &flags); 952 846 } 953 847 ··· 980 868 981 869 bool mlx5_lag_check_prereq(struct mlx5_lag *ldev) 982 870 { 983 - int first_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 871 + int master_idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 984 872 #ifdef CONFIG_MLX5_ESWITCH 985 873 struct mlx5_core_dev *dev; 986 874 u8 mode; ··· 989 877 bool roce_support; 990 878 int i; 991 879 992 - if (first_idx < 0 || mlx5_lag_num_devs(ldev) != ldev->ports) 880 + if (master_idx < 0 || mlx5_lag_num_devs(ldev) != ldev->ports) 993 881 return false; 994 882 995 883 #ifdef CONFIG_MLX5_ESWITCH ··· 1000 888 return false; 1001 889 } 1002 890 1003 - pf = mlx5_lag_pf(ldev, first_idx); 891 + pf = mlx5_lag_pf(ldev, master_idx); 1004 892 dev = pf->dev; 1005 893 mode = mlx5_eswitch_mode(dev); 1006 894 mlx5_ldev_for_each(i, 0, ldev) { ··· 1016 904 return false; 1017 905 } 1018 906 #endif 1019 - pf = mlx5_lag_pf(ldev, first_idx); 907 + pf = mlx5_lag_pf(ldev, master_idx); 1020 908 roce_support = mlx5_get_roce_state(pf->dev); 1021 - mlx5_ldev_for_each(i, first_idx + 1, ldev) { 909 + mlx5_ldev_for_each(i, 0, ldev) { 910 + if (i == master_idx) 911 + continue; 1022 912 pf = mlx5_lag_pf(ldev, i); 1023 913 if (mlx5_get_roce_state(pf->dev) != roce_support) 1024 914 return false; ··· 1081 967 dev0->priv.flags |= MLX5_PRIV_FLAGS_DISABLE_IB_ADEV; 1082 968 mlx5_rescan_drivers_locked(dev0); 1083 969 } 1084 - mlx5_ldev_for_each(i, idx + 1, ldev) 970 + mlx5_ldev_for_each(i, 0, ldev) { 971 + if (i == idx) 972 + continue; 1085 973 mlx5_nic_vport_disable_roce(mlx5_lag_pf(ldev, i)->dev); 974 + } 1086 975 } 1087 976 1088 977 err = mlx5_deactivate_lag(ldev); ··· 1103 986 1104 987 bool mlx5_lag_shared_fdb_supported(struct mlx5_lag *ldev) 1105 988 { 1106 - int idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 1107 989 struct mlx5_core_dev *dev; 990 + bool ret = false; 991 + int idx; 1108 992 int i; 1109 993 994 + idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 1110 995 if (idx < 0) 1111 996 return false; 1112 997 1113 - mlx5_ldev_for_each(i, idx + 1, ldev) { 998 + mlx5_ldev_for_each(i, 0, ldev) { 999 + if (i == idx) 1000 + continue; 1114 1001 dev = mlx5_lag_pf(ldev, i)->dev; 1115 1002 if (is_mdev_switchdev_mode(dev) && 1116 1003 mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch) && ··· 1132 1011 mlx5_esw_offloads_devcom_is_ready(dev->priv.eswitch) && 1133 1012 MLX5_CAP_ESW(dev, esw_shared_ingress_acl) && 1134 1013 mlx5_eswitch_get_npeers(dev->priv.eswitch) == MLX5_CAP_GEN(dev, num_lag_ports) - 1) 1135 - return true; 1014 + ret = true; 1136 1015 1137 - return false; 1016 + return ret; 1138 1017 } 1139 1018 1140 1019 static bool mlx5_lag_is_roce_lag(struct mlx5_lag *ldev) ··· 1360 1239 } 1361 1240 1362 1241 return; 1363 - } else if (roce_lag) { 1242 + } 1243 + 1244 + if (roce_lag) { 1364 1245 struct mlx5_core_dev *dev; 1365 1246 1366 1247 dev0->priv.flags &= ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV; 1367 1248 mlx5_rescan_drivers_locked(dev0); 1368 - mlx5_ldev_for_each(i, idx + 1, ldev) { 1249 + mlx5_ldev_for_each(i, 0, ldev) { 1250 + if (i == idx) 1251 + continue; 1369 1252 dev = mlx5_lag_pf(ldev, i)->dev; 1370 1253 if (mlx5_get_roce_state(dev)) 1371 1254 mlx5_nic_vport_enable_roce(dev); ··· 1723 1598 struct mlx5_core_dev *dev, 1724 1599 struct net_device *netdev) 1725 1600 { 1726 - unsigned int fn = mlx5_get_dev_index(dev); 1727 1601 struct lag_func *pf; 1728 1602 unsigned long flags; 1603 + int i; 1729 1604 1730 1605 spin_lock_irqsave(&lag_lock, flags); 1731 - pf = mlx5_lag_pf(ldev, fn); 1732 - pf->netdev = netdev; 1733 - ldev->tracker.netdev_state[fn].link_up = 0; 1734 - ldev->tracker.netdev_state[fn].tx_enabled = 0; 1606 + /* Find pf entry by matching dev pointer */ 1607 + mlx5_ldev_for_each(i, 0, ldev) { 1608 + pf = mlx5_lag_pf(ldev, i); 1609 + if (pf->dev == dev) { 1610 + pf->netdev = netdev; 1611 + ldev->tracker.netdev_state[i].link_up = 0; 1612 + ldev->tracker.netdev_state[i].tx_enabled = 0; 1613 + break; 1614 + } 1615 + } 1735 1616 spin_unlock_irqrestore(&lag_lock, flags); 1736 1617 } 1737 1618 ··· 1762 1631 static int mlx5_ldev_add_mdev(struct mlx5_lag *ldev, 1763 1632 struct mlx5_core_dev *dev) 1764 1633 { 1765 - unsigned int fn = mlx5_get_dev_index(dev); 1766 1634 struct lag_func *pf; 1635 + u32 idx; 1767 1636 int err; 1768 1637 1769 - pf = xa_load(&ldev->pfs, fn); 1770 - if (!pf) { 1771 - pf = kzalloc_obj(*pf); 1772 - if (!pf) 1773 - return -ENOMEM; 1638 + pf = kzalloc_obj(*pf); 1639 + if (!pf) 1640 + return -ENOMEM; 1774 1641 1775 - err = xa_err(xa_store(&ldev->pfs, fn, pf, GFP_KERNEL)); 1776 - if (err) { 1777 - kfree(pf); 1778 - return err; 1779 - } 1642 + err = xa_alloc(&ldev->pfs, &idx, pf, XA_LIMIT(0, MLX5_MAX_PORTS - 1), 1643 + GFP_KERNEL); 1644 + if (err) { 1645 + kfree(pf); 1646 + return err; 1780 1647 } 1781 1648 1649 + pf->idx = idx; 1782 1650 pf->dev = dev; 1783 1651 dev->priv.lag = ldev; 1784 1652 ··· 1792 1662 struct mlx5_core_dev *dev) 1793 1663 { 1794 1664 struct lag_func *pf; 1795 - int fn; 1665 + int i; 1796 1666 1797 - fn = mlx5_get_dev_index(dev); 1798 - pf = xa_load(&ldev->pfs, fn); 1799 - if (!pf || pf->dev != dev) 1667 + mlx5_ldev_for_each(i, 0, ldev) { 1668 + pf = mlx5_lag_pf(ldev, i); 1669 + if (pf->dev == dev) 1670 + break; 1671 + } 1672 + if (i >= MLX5_MAX_PORTS) 1800 1673 return; 1801 1674 1802 1675 if (pf->port_change_nb.nb.notifier_call) ··· 1807 1674 1808 1675 pf->dev = NULL; 1809 1676 dev->priv.lag = NULL; 1810 - xa_erase(&ldev->pfs, fn); 1677 + xa_erase(&ldev->pfs, pf->idx); 1811 1678 kfree(pf); 1812 1679 } 1813 1680 ··· 1877 1744 dev->priv.hca_devcom_comp = 1878 1745 mlx5_devcom_register_component(dev->priv.devc, 1879 1746 MLX5_DEVCOM_HCA_PORTS, 1880 - &attr, NULL, dev); 1747 + &attr, mlx5_lag_devcom_event, 1748 + dev); 1881 1749 if (!dev->priv.hca_devcom_comp) { 1882 1750 mlx5_core_err(dev, 1883 1751 "Failed to register devcom HCA component."); ··· 1909 1775 } 1910 1776 mlx5_ldev_remove_mdev(ldev, dev); 1911 1777 mutex_unlock(&ldev->lock); 1778 + /* Send devcom event to notify peers that a device is being removed */ 1779 + mlx5_devcom_send_event(dev->priv.hca_devcom_comp, 1780 + LAG_DEVCOM_UNPAIR, LAG_DEVCOM_UNPAIR, dev); 1912 1781 mlx5_lag_unregister_hca_devcom_comp(dev); 1913 1782 mlx5_ldev_put(ldev); 1914 1783 } ··· 1935 1798 msleep(100); 1936 1799 goto recheck; 1937 1800 } 1801 + /* Send devcom event to notify peers that a device was added */ 1802 + mlx5_devcom_send_event(dev->priv.hca_devcom_comp, 1803 + LAG_DEVCOM_PAIR, LAG_DEVCOM_UNPAIR, dev); 1938 1804 mlx5_ldev_add_debugfs(dev); 1939 1805 } 1940 1806

+29

drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h

··· 7 7 #include <linux/debugfs.h> 8 8 9 9 #define MLX5_LAG_MAX_HASH_BUCKETS 16 10 + /* XArray mark for the LAG master device 11 + * (device with lowest mlx5_get_dev_index). 12 + * Note: XA_MARK_0 is reserved by XA_FLAGS_ALLOC for free-slot tracking. 13 + */ 14 + #define MLX5_LAG_XA_MARK_MASTER XA_MARK_1 15 + 10 16 #include "mlx5_core.h" 11 17 #include "mp.h" 12 18 #include "port_sel.h" ··· 45 39 struct mlx5_core_dev *dev; 46 40 struct net_device *netdev; 47 41 bool has_drop; 42 + unsigned int idx; /* xarray index assigned by LAG */ 48 43 struct mlx5_nb port_change_nb; 49 44 }; 50 45 ··· 95 88 mlx5_lag_pf(struct mlx5_lag *ldev, unsigned int idx) 96 89 { 97 90 return xa_load(&ldev->pfs, idx); 91 + } 92 + 93 + /* Get device index (mlx5_get_dev_index) from xarray index */ 94 + static inline int mlx5_lag_xa_to_dev_idx(struct mlx5_lag *ldev, int xa_idx) 95 + { 96 + struct lag_func *pf = mlx5_lag_pf(ldev, xa_idx); 97 + 98 + return pf ? mlx5_get_dev_index(pf->dev) : -ENOENT; 99 + } 100 + 101 + /* Find lag_func by device index (reverse lookup from mlx5_get_dev_index) */ 102 + static inline struct lag_func * 103 + mlx5_lag_pf_by_dev_idx(struct mlx5_lag *ldev, int dev_idx) 104 + { 105 + struct lag_func *pf; 106 + unsigned long idx; 107 + 108 + xa_for_each(&ldev->pfs, idx, pf) { 109 + if (mlx5_get_dev_index(pf->dev) == dev_idx) 110 + return pf; 111 + } 112 + return NULL; 98 113 } 99 114 100 115 static inline bool

+1 -2

drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c

··· 67 67 68 68 static int mlx5_lag_enable_mpesw(struct mlx5_lag *ldev) 69 69 { 70 + int idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 70 71 struct mlx5_core_dev *dev0; 71 72 int err; 72 - int idx; 73 73 int i; 74 74 75 75 if (ldev->mode == MLX5_LAG_MODE_MPESW) ··· 78 78 if (ldev->mode != MLX5_LAG_MODE_NONE) 79 79 return -EINVAL; 80 80 81 - idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); 82 81 if (idx < 0) 83 82 return -EINVAL; 84 83

+9 -3

drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c

··· 84 84 idx = i * ldev->buckets + j; 85 85 affinity = ports[idx]; 86 86 87 + /* affinity is 1-indexed device index, 88 + * use reverse lookup. 89 + */ 87 90 dest.vport.vhca_id = 88 - MLX5_CAP_GEN(mlx5_lag_pf(ldev, affinity - 1)->dev, 91 + MLX5_CAP_GEN(mlx5_lag_pf_by_dev_idx(ldev, affinity - 1)->dev, 89 92 vhca_id); 90 93 lag_definer->rules[idx] = mlx5_add_flow_rules(lag_definer->ft, 91 94 NULL, &flow_act, ··· 361 358 return; 362 359 363 360 dev = mlx5_lag_pf(ldev, first_idx)->dev; 364 - mlx5_ldev_for_each(i, first_idx, ldev) { 361 + mlx5_ldev_for_each(i, 0, ldev) { 365 362 for (j = 0; j < ldev->buckets; j++) { 366 363 idx = i * ldev->buckets + j; 367 364 mlx5_del_flow_rules(lag_definer->rules[idx]); ··· 598 595 if (ldev->v2p_map[idx] == ports[idx]) 599 596 continue; 600 597 598 + /* ports[] contains 1-indexed device indices, 599 + * use reverse lookup. 600 + */ 601 601 dest.vport.vhca_id = 602 - MLX5_CAP_GEN(mlx5_lag_pf(ldev, ports[idx] - 1)->dev, 602 + MLX5_CAP_GEN(mlx5_lag_pf_by_dev_idx(ldev, ports[idx] - 1)->dev, 603 603 vhca_id); 604 604 err = mlx5_modify_rule_destination(def->rules[idx], &dest, NULL); 605 605 if (err)

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