Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

+1 -1

drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c

··· 1009 1009 } 1010 1010 1011 1011 if (outp == 8) 1012 - return false; 1012 + return conf; 1013 1013 1014 1014 data = exec_lookup(priv, head, outp, ctrl, dcb, &ver, &hdr, &cnt, &len, &info1); 1015 1015 if (data == 0x0000)

+1

drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c

··· 40 40 case 0x00: return 2; 41 41 case 0x19: return 1; 42 42 case 0x1c: return 0; 43 + case 0x1e: return 2; 43 44 default: 44 45 break; 45 46 }

+4 -2

drivers/gpu/drm/radeon/radeon.h

··· 1642 1642 unsigned fb_version; 1643 1643 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1644 1644 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1645 + unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1645 1646 struct delayed_work idle_work; 1646 1647 }; 1647 1648 ··· 1656 1655 uint32_t handle, struct radeon_fence **fence); 1657 1656 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1658 1657 void radeon_vce_note_usage(struct radeon_device *rdev); 1659 - int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi); 1658 + int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1660 1659 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1661 1660 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1662 1661 struct radeon_ring *ring, ··· 2641 2640 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2642 2641 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2643 2642 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2644 - #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI)) 2643 + #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2644 + (rdev->family == CHIP_MULLINS)) 2645 2645 2646 2646 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2647 2647 (rdev->ddev->pdev->device == 0x6850) || \

+14

drivers/gpu/drm/radeon/radeon_bios.c

··· 196 196 } 197 197 } 198 198 199 + if (!found) { 200 + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 201 + dhandle = ACPI_HANDLE(&pdev->dev); 202 + if (!dhandle) 203 + continue; 204 + 205 + status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 206 + if (!ACPI_FAILURE(status)) { 207 + found = true; 208 + break; 209 + } 210 + } 211 + } 212 + 199 213 if (!found) 200 214 return false; 201 215

+1 -1

drivers/gpu/drm/radeon/radeon_display.c

··· 999 999 1000 1000 /* avoid high jitter with small fractional dividers */ 1001 1001 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1002 - fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60); 1002 + fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1003 1003 if (fb_div < fb_div_min) { 1004 1004 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1005 1005 fb_div *= tmp;

+31 -28

drivers/gpu/drm/radeon/radeon_kms.c

··· 577 577 return r; 578 578 } 579 579 580 - r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 581 - if (r) { 582 - radeon_vm_fini(rdev, &fpriv->vm); 583 - kfree(fpriv); 584 - return r; 580 + if (rdev->accel_working) { 581 + r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 582 + if (r) { 583 + radeon_vm_fini(rdev, &fpriv->vm); 584 + kfree(fpriv); 585 + return r; 586 + } 587 + 588 + /* map the ib pool buffer read only into 589 + * virtual address space */ 590 + bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, 591 + rdev->ring_tmp_bo.bo); 592 + r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 593 + RADEON_VM_PAGE_READABLE | 594 + RADEON_VM_PAGE_SNOOPED); 595 + 596 + radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 597 + if (r) { 598 + radeon_vm_fini(rdev, &fpriv->vm); 599 + kfree(fpriv); 600 + return r; 601 + } 585 602 } 586 - 587 - /* map the ib pool buffer read only into 588 - * virtual address space */ 589 - bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, 590 - rdev->ring_tmp_bo.bo); 591 - r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 592 - RADEON_VM_PAGE_READABLE | 593 - RADEON_VM_PAGE_SNOOPED); 594 - 595 - radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 596 - if (r) { 597 - radeon_vm_fini(rdev, &fpriv->vm); 598 - kfree(fpriv); 599 - return r; 600 - } 601 - 602 603 file_priv->driver_priv = fpriv; 603 604 } 604 605 ··· 627 626 struct radeon_bo_va *bo_va; 628 627 int r; 629 628 630 - r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 631 - if (!r) { 632 - bo_va = radeon_vm_bo_find(&fpriv->vm, 633 - rdev->ring_tmp_bo.bo); 634 - if (bo_va) 635 - radeon_vm_bo_rmv(rdev, bo_va); 636 - radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 629 + if (rdev->accel_working) { 630 + r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 631 + if (!r) { 632 + bo_va = radeon_vm_bo_find(&fpriv->vm, 633 + rdev->ring_tmp_bo.bo); 634 + if (bo_va) 635 + radeon_vm_bo_rmv(rdev, bo_va); 636 + radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 637 + } 637 638 } 638 639 639 640 radeon_vm_fini(rdev, &fpriv->vm);

+24 -16

drivers/gpu/drm/radeon/radeon_object.c

··· 458 458 * into account. We don't want to disallow buffer moves 459 459 * completely. 460 460 */ 461 - if (current_domain != RADEON_GEM_DOMAIN_CPU && 461 + if ((lobj->alt_domain & current_domain) != 0 && 462 462 (domain & current_domain) == 0 && /* will be moved */ 463 463 bytes_moved > bytes_moved_threshold) { 464 464 /* don't move it */ ··· 699 699 rbo = container_of(bo, struct radeon_bo, tbo); 700 700 radeon_bo_check_tiling(rbo, 0, 0); 701 701 rdev = rbo->rdev; 702 - if (bo->mem.mem_type == TTM_PL_VRAM) { 703 - size = bo->mem.num_pages << PAGE_SHIFT; 704 - offset = bo->mem.start << PAGE_SHIFT; 705 - if ((offset + size) > rdev->mc.visible_vram_size) { 706 - /* hurrah the memory is not visible ! */ 707 - radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 708 - rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 709 - r = ttm_bo_validate(bo, &rbo->placement, false, false); 710 - if (unlikely(r != 0)) 711 - return r; 712 - offset = bo->mem.start << PAGE_SHIFT; 713 - /* this should not happen */ 714 - if ((offset + size) > rdev->mc.visible_vram_size) 715 - return -EINVAL; 716 - } 702 + if (bo->mem.mem_type != TTM_PL_VRAM) 703 + return 0; 704 + 705 + size = bo->mem.num_pages << PAGE_SHIFT; 706 + offset = bo->mem.start << PAGE_SHIFT; 707 + if ((offset + size) <= rdev->mc.visible_vram_size) 708 + return 0; 709 + 710 + /* hurrah the memory is not visible ! */ 711 + radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 712 + rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 713 + r = ttm_bo_validate(bo, &rbo->placement, false, false); 714 + if (unlikely(r == -ENOMEM)) { 715 + radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 716 + return ttm_bo_validate(bo, &rbo->placement, false, false); 717 + } else if (unlikely(r != 0)) { 718 + return r; 717 719 } 720 + 721 + offset = bo->mem.start << PAGE_SHIFT; 722 + /* this should never happen */ 723 + if ((offset + size) > rdev->mc.visible_vram_size) 724 + return -EINVAL; 725 + 718 726 return 0; 719 727 } 720 728

+41 -1

drivers/gpu/drm/radeon/radeon_pm.c

··· 361 361 struct drm_device *ddev = dev_get_drvdata(dev); 362 362 struct radeon_device *rdev = ddev->dev_private; 363 363 364 + /* Can't set profile when the card is off */ 365 + if ((rdev->flags & RADEON_IS_PX) && 366 + (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 367 + return -EINVAL; 368 + 364 369 mutex_lock(&rdev->pm.mutex); 365 370 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 366 371 if (strncmp("default", buf, strlen("default")) == 0) ··· 414 409 struct drm_device *ddev = dev_get_drvdata(dev); 415 410 struct radeon_device *rdev = ddev->dev_private; 416 411 412 + /* Can't set method when the card is off */ 413 + if ((rdev->flags & RADEON_IS_PX) && 414 + (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 415 + count = -EINVAL; 416 + goto fail; 417 + } 418 + 417 419 /* we don't support the legacy modes with dpm */ 418 420 if (rdev->pm.pm_method == PM_METHOD_DPM) { 419 421 count = -EINVAL; ··· 458 446 struct radeon_device *rdev = ddev->dev_private; 459 447 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 460 448 449 + if ((rdev->flags & RADEON_IS_PX) && 450 + (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 451 + return snprintf(buf, PAGE_SIZE, "off\n"); 452 + 461 453 return snprintf(buf, PAGE_SIZE, "%s\n", 462 454 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 463 455 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); ··· 474 458 { 475 459 struct drm_device *ddev = dev_get_drvdata(dev); 476 460 struct radeon_device *rdev = ddev->dev_private; 461 + 462 + /* Can't set dpm state when the card is off */ 463 + if ((rdev->flags & RADEON_IS_PX) && 464 + (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 465 + return -EINVAL; 477 466 478 467 mutex_lock(&rdev->pm.mutex); 479 468 if (strncmp("battery", buf, strlen("battery")) == 0) ··· 506 485 struct radeon_device *rdev = ddev->dev_private; 507 486 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 508 487 488 + if ((rdev->flags & RADEON_IS_PX) && 489 + (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 490 + return snprintf(buf, PAGE_SIZE, "off\n"); 491 + 509 492 return snprintf(buf, PAGE_SIZE, "%s\n", 510 493 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 511 494 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); ··· 524 499 struct radeon_device *rdev = ddev->dev_private; 525 500 enum radeon_dpm_forced_level level; 526 501 int ret = 0; 502 + 503 + /* Can't force performance level when the card is off */ 504 + if ((rdev->flags & RADEON_IS_PX) && 505 + (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 506 + return -EINVAL; 527 507 528 508 mutex_lock(&rdev->pm.mutex); 529 509 if (strncmp("low", buf, strlen("low")) == 0) { ··· 568 538 char *buf) 569 539 { 570 540 struct radeon_device *rdev = dev_get_drvdata(dev); 541 + struct drm_device *ddev = rdev->ddev; 571 542 int temp; 543 + 544 + /* Can't get temperature when the card is off */ 545 + if ((rdev->flags & RADEON_IS_PX) && 546 + (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 547 + return -EINVAL; 572 548 573 549 if (rdev->asic->pm.get_temperature) 574 550 temp = radeon_get_temperature(rdev); ··· 1650 1614 struct drm_info_node *node = (struct drm_info_node *) m->private; 1651 1615 struct drm_device *dev = node->minor->dev; 1652 1616 struct radeon_device *rdev = dev->dev_private; 1617 + struct drm_device *ddev = rdev->ddev; 1653 1618 1654 - if (rdev->pm.dpm_enabled) { 1619 + if ((rdev->flags & RADEON_IS_PX) && 1620 + (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1621 + seq_printf(m, "PX asic powered off\n"); 1622 + } else if (rdev->pm.dpm_enabled) { 1655 1623 mutex_lock(&rdev->pm.mutex); 1656 1624 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1657 1625 radeon_dpm_debugfs_print_current_performance_level(rdev, m);

+100 -30

drivers/gpu/drm/radeon/radeon_vce.c

··· 443 443 * @p: parser context 444 444 * @lo: address of lower dword 445 445 * @hi: address of higher dword 446 + * @size: size of checker for relocation buffer 446 447 * 447 448 * Patch relocation inside command stream with real buffer address 448 449 */ 449 - int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi) 450 + int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, 451 + unsigned size) 450 452 { 451 453 struct radeon_cs_chunk *relocs_chunk; 452 - uint64_t offset; 454 + struct radeon_cs_reloc *reloc; 455 + uint64_t start, end, offset; 453 456 unsigned idx; 454 457 455 458 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; ··· 465 462 return -EINVAL; 466 463 } 467 464 468 - offset += p->relocs_ptr[(idx / 4)]->gpu_offset; 465 + reloc = p->relocs_ptr[(idx / 4)]; 466 + start = reloc->gpu_offset; 467 + end = start + radeon_bo_size(reloc->robj); 468 + start += offset; 469 469 470 - p->ib.ptr[lo] = offset & 0xFFFFFFFF; 471 - p->ib.ptr[hi] = offset >> 32; 470 + p->ib.ptr[lo] = start & 0xFFFFFFFF; 471 + p->ib.ptr[hi] = start >> 32; 472 + 473 + if (end <= start) { 474 + DRM_ERROR("invalid reloc offset %llX!\n", offset); 475 + return -EINVAL; 476 + } 477 + if ((end - start) < size) { 478 + DRM_ERROR("buffer to small (%d / %d)!\n", 479 + (unsigned)(end - start), size); 480 + return -EINVAL; 481 + } 472 482 473 483 return 0; 484 + } 485 + 486 + /** 487 + * radeon_vce_validate_handle - validate stream handle 488 + * 489 + * @p: parser context 490 + * @handle: handle to validate 491 + * 492 + * Validates the handle and return the found session index or -EINVAL 493 + * we we don't have another free session index. 494 + */ 495 + int radeon_vce_validate_handle(struct radeon_cs_parser *p, uint32_t handle) 496 + { 497 + unsigned i; 498 + 499 + /* validate the handle */ 500 + for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { 501 + if (atomic_read(&p->rdev->vce.handles[i]) == handle) 502 + return i; 503 + } 504 + 505 + /* handle not found try to alloc a new one */ 506 + for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { 507 + if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) { 508 + p->rdev->vce.filp[i] = p->filp; 509 + p->rdev->vce.img_size[i] = 0; 510 + return i; 511 + } 512 + } 513 + 514 + DRM_ERROR("No more free VCE handles!\n"); 515 + return -EINVAL; 474 516 } 475 517 476 518 /** ··· 526 478 */ 527 479 int radeon_vce_cs_parse(struct radeon_cs_parser *p) 528 480 { 529 - uint32_t handle = 0; 530 - bool destroy = false; 481 + int session_idx = -1; 482 + bool destroyed = false; 483 + uint32_t tmp, handle = 0; 484 + uint32_t *size = &tmp; 531 485 int i, r; 532 486 533 487 while (p->idx < p->chunks[p->chunk_ib_idx].length_dw) { ··· 541 491 return -EINVAL; 542 492 } 543 493 494 + if (destroyed) { 495 + DRM_ERROR("No other command allowed after destroy!\n"); 496 + return -EINVAL; 497 + } 498 + 544 499 switch (cmd) { 545 500 case 0x00000001: // session 546 501 handle = radeon_get_ib_value(p, p->idx + 2); 502 + session_idx = radeon_vce_validate_handle(p, handle); 503 + if (session_idx < 0) 504 + return session_idx; 505 + size = &p->rdev->vce.img_size[session_idx]; 547 506 break; 548 507 549 508 case 0x00000002: // task info 509 + break; 510 + 550 511 case 0x01000001: // create 512 + *size = radeon_get_ib_value(p, p->idx + 8) * 513 + radeon_get_ib_value(p, p->idx + 10) * 514 + 8 * 3 / 2; 515 + break; 516 + 551 517 case 0x04000001: // config extension 552 518 case 0x04000002: // pic control 553 519 case 0x04000005: // rate control ··· 572 506 break; 573 507 574 508 case 0x03000001: // encode 575 - r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9); 509 + r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9, 510 + *size); 576 511 if (r) 577 512 return r; 578 513 579 - r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11); 514 + r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11, 515 + *size / 3); 580 516 if (r) 581 517 return r; 582 518 break; 583 519 584 520 case 0x02000001: // destroy 585 - destroy = true; 521 + destroyed = true; 586 522 break; 587 523 588 524 case 0x05000001: // context buffer 525 + r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2, 526 + *size * 2); 527 + if (r) 528 + return r; 529 + break; 530 + 589 531 case 0x05000004: // video bitstream buffer 532 + tmp = radeon_get_ib_value(p, p->idx + 4); 533 + r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2, 534 + tmp); 535 + if (r) 536 + return r; 537 + break; 538 + 590 539 case 0x05000005: // feedback buffer 591 - r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2); 540 + r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2, 541 + 4096); 592 542 if (r) 593 543 return r; 594 544 break; ··· 614 532 return -EINVAL; 615 533 } 616 534 535 + if (session_idx == -1) { 536 + DRM_ERROR("no session command at start of IB\n"); 537 + return -EINVAL; 538 + } 539 + 617 540 p->idx += len / 4; 618 541 } 619 542 620 - if (destroy) { 543 + if (destroyed) { 621 544 /* IB contains a destroy msg, free the handle */ 622 545 for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) 623 546 atomic_cmpxchg(&p->rdev->vce.handles[i], handle, 0); 624 - 625 - return 0; 626 - } 627 - 628 - /* create or encode, validate the handle */ 629 - for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { 630 - if (atomic_read(&p->rdev->vce.handles[i]) == handle) 631 - return 0; 632 547 } 633 548 634 - /* handle not found try to alloc a new one */ 635 - for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { 636 - if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) { 637 - p->rdev->vce.filp[i] = p->filp; 638 - return 0; 639 - } 640 - } 641 - 642 - DRM_ERROR("No more free VCE handles!\n"); 643 - return -EINVAL; 549 + return 0; 644 550 } 645 551 646 552 /**

+1 -1

drivers/gpu/drm/radeon/radeon_vm.c

··· 595 595 ndw = 64; 596 596 597 597 /* assume the worst case */ 598 - ndw += vm->max_pde_used * 12; 598 + ndw += vm->max_pde_used * 16; 599 599 600 600 /* update too big for an IB */ 601 601 if (ndw > 0xfffff)

+2 -2

drivers/gpu/drm/radeon/sid.h

··· 107 107 #define SPLL_CHG_STATUS (1 << 1) 108 108 #define SPLL_CNTL_MODE 0x618 109 109 #define SPLL_SW_DIR_CONTROL (1 << 0) 110 - # define SPLL_REFCLK_SEL(x) ((x) << 8) 111 - # define SPLL_REFCLK_SEL_MASK 0xFF00 110 + # define SPLL_REFCLK_SEL(x) ((x) << 26) 111 + # define SPLL_REFCLK_SEL_MASK (3 << 26) 112 112 113 113 #define CG_SPLL_SPREAD_SPECTRUM 0x620 114 114 #define SSEN (1 << 0)

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