Merge tag 'turbostat-2025.09.09' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

+550 -221

2 changed files

expand all

tools

power

x86

turbostat

turbostat.8

turbostat.c

+10 -1

tools/power/x86/turbostat/turbostat.8

··· 47 47 MSRs are read as 64-bits, u32 truncates the displayed value to 32-bits. 48 48 default: u64 49 49 50 - format: {\fBraw\fP | \fBdelta\fP | \fBpercent\fP} 50 + format: {\fBraw\fP | \fBdelta\fP | \fBpercent\fP | \fBaverage\fP} 51 51 'raw' shows the MSR contents in hex. 52 52 'delta' shows the difference in values during the measurement interval. 53 53 'percent' shows the delta as a percentage of the cycles elapsed. 54 + 'average' similar to raw, but also averaged for node/package summaries (or when using -S). 54 55 default: delta 55 56 56 57 name: "name_string" ··· 186 185 \fBSAMMHz\fP Instantaneous snapshot of what sysfs presents at the end of the measurement interval. From /sys/class/drm/card0/gt/gt1/rps_cur_freq_mhz or /sys/class/drm/card0/device/tile0/gtN/freq0/cur_freq depending on the graphics driver being used. 187 186 .PP 188 187 \fBSAMAMHz\fP Instantaneous snapshot of what sysfs presents at the end of the measurement interval. From /sys/class/drm/card0/gt/gt1/rps_act_freq_mhz or /sys/class/drm/card0/device/tile0/gtN/freq0/act_freq depending on the graphics driver being used. 188 + .PP 189 + \fBTotl%C0\fP Weighted percentage of time that CPUs are busy. If N CPUs are busy during an interval, the percentage is N * 100%. 190 + .PP 191 + \fBAny%C0\fP Percentage of time that at least one CPU is busy. 192 + .PP 193 + \fBGFX%C0\fP Percentage of time that at least one GFX compute engine is busy. 194 + .PP 195 + \fBCPUGFX%\fP Percentage of time that at least one CPU is busy at the same time as at least one Graphics compute enginer is busy. 189 196 .PP 190 197 \fBPkg%pc2, Pkg%pc3, Pkg%pc6, Pkg%pc7\fP percentage residency in hardware package idle states. These numbers are from hardware residency counters. 191 198 .PP

+540 -220

tools/power/x86/turbostat/turbostat.c

··· 67 67 #include <stdbool.h> 68 68 #include <assert.h> 69 69 #include <linux/kernel.h> 70 + #include <limits.h> 70 71 71 72 #define UNUSED(x) (void)(x) 72 73 ··· 195 194 { 0x0, "APIC", NULL, 0, 0, 0, NULL, 0 }, 196 195 { 0x0, "X2APIC", NULL, 0, 0, 0, NULL, 0 }, 197 196 { 0x0, "Die", NULL, 0, 0, 0, NULL, 0 }, 197 + { 0x0, "L3", NULL, 0, 0, 0, NULL, 0 }, 198 198 { 0x0, "GFXAMHz", NULL, 0, 0, 0, NULL, 0 }, 199 199 { 0x0, "IPC", NULL, 0, 0, 0, NULL, 0 }, 200 200 { 0x0, "CoreThr", NULL, 0, 0, 0, NULL, 0 }, ··· 211 209 { 0x0, "pct_idle", NULL, 0, 0, 0, NULL, 0 }, 212 210 }; 213 211 214 - #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 215 - #define BIC_USEC (1ULL << 0) 216 - #define BIC_TOD (1ULL << 1) 217 - #define BIC_Package (1ULL << 2) 218 - #define BIC_Node (1ULL << 3) 219 - #define BIC_Avg_MHz (1ULL << 4) 220 - #define BIC_Busy (1ULL << 5) 221 - #define BIC_Bzy_MHz (1ULL << 6) 222 - #define BIC_TSC_MHz (1ULL << 7) 223 - #define BIC_IRQ (1ULL << 8) 224 - #define BIC_SMI (1ULL << 9) 225 - #define BIC_cpuidle (1ULL << 10) 226 - #define BIC_CPU_c1 (1ULL << 11) 227 - #define BIC_CPU_c3 (1ULL << 12) 228 - #define BIC_CPU_c6 (1ULL << 13) 229 - #define BIC_CPU_c7 (1ULL << 14) 230 - #define BIC_ThreadC (1ULL << 15) 231 - #define BIC_CoreTmp (1ULL << 16) 232 - #define BIC_CoreCnt (1ULL << 17) 233 - #define BIC_PkgTmp (1ULL << 18) 234 - #define BIC_GFX_rc6 (1ULL << 19) 235 - #define BIC_GFXMHz (1ULL << 20) 236 - #define BIC_Pkgpc2 (1ULL << 21) 237 - #define BIC_Pkgpc3 (1ULL << 22) 238 - #define BIC_Pkgpc6 (1ULL << 23) 239 - #define BIC_Pkgpc7 (1ULL << 24) 240 - #define BIC_Pkgpc8 (1ULL << 25) 241 - #define BIC_Pkgpc9 (1ULL << 26) 242 - #define BIC_Pkgpc10 (1ULL << 27) 243 - #define BIC_CPU_LPI (1ULL << 28) 244 - #define BIC_SYS_LPI (1ULL << 29) 245 - #define BIC_PkgWatt (1ULL << 30) 246 - #define BIC_CorWatt (1ULL << 31) 247 - #define BIC_GFXWatt (1ULL << 32) 248 - #define BIC_PkgCnt (1ULL << 33) 249 - #define BIC_RAMWatt (1ULL << 34) 250 - #define BIC_PKG__ (1ULL << 35) 251 - #define BIC_RAM__ (1ULL << 36) 252 - #define BIC_Pkg_J (1ULL << 37) 253 - #define BIC_Cor_J (1ULL << 38) 254 - #define BIC_GFX_J (1ULL << 39) 255 - #define BIC_RAM_J (1ULL << 40) 256 - #define BIC_Mod_c6 (1ULL << 41) 257 - #define BIC_Totl_c0 (1ULL << 42) 258 - #define BIC_Any_c0 (1ULL << 43) 259 - #define BIC_GFX_c0 (1ULL << 44) 260 - #define BIC_CPUGFX (1ULL << 45) 261 - #define BIC_Core (1ULL << 46) 262 - #define BIC_CPU (1ULL << 47) 263 - #define BIC_APIC (1ULL << 48) 264 - #define BIC_X2APIC (1ULL << 49) 265 - #define BIC_Die (1ULL << 50) 266 - #define BIC_GFXACTMHz (1ULL << 51) 267 - #define BIC_IPC (1ULL << 52) 268 - #define BIC_CORE_THROT_CNT (1ULL << 53) 269 - #define BIC_UNCORE_MHZ (1ULL << 54) 270 - #define BIC_SAM_mc6 (1ULL << 55) 271 - #define BIC_SAMMHz (1ULL << 56) 272 - #define BIC_SAMACTMHz (1ULL << 57) 273 - #define BIC_Diec6 (1ULL << 58) 274 - #define BIC_SysWatt (1ULL << 59) 275 - #define BIC_Sys_J (1ULL << 60) 276 - #define BIC_NMI (1ULL << 61) 277 - #define BIC_CPU_c1e (1ULL << 62) 278 - #define BIC_pct_idle (1ULL << 63) 212 + /* n.b. bic_names must match the order in bic[], above */ 213 + enum bic_names { 214 + BIC_USEC, 215 + BIC_TOD, 216 + BIC_Package, 217 + BIC_Node, 218 + BIC_Avg_MHz, 219 + BIC_Busy, 220 + BIC_Bzy_MHz, 221 + BIC_TSC_MHz, 222 + BIC_IRQ, 223 + BIC_SMI, 224 + BIC_cpuidle, 225 + BIC_CPU_c1, 226 + BIC_CPU_c3, 227 + BIC_CPU_c6, 228 + BIC_CPU_c7, 229 + BIC_ThreadC, 230 + BIC_CoreTmp, 231 + BIC_CoreCnt, 232 + BIC_PkgTmp, 233 + BIC_GFX_rc6, 234 + BIC_GFXMHz, 235 + BIC_Pkgpc2, 236 + BIC_Pkgpc3, 237 + BIC_Pkgpc6, 238 + BIC_Pkgpc7, 239 + BIC_Pkgpc8, 240 + BIC_Pkgpc9, 241 + BIC_Pkgpc10, 242 + BIC_CPU_LPI, 243 + BIC_SYS_LPI, 244 + BIC_PkgWatt, 245 + BIC_CorWatt, 246 + BIC_GFXWatt, 247 + BIC_PkgCnt, 248 + BIC_RAMWatt, 249 + BIC_PKG__, 250 + BIC_RAM__, 251 + BIC_Pkg_J, 252 + BIC_Cor_J, 253 + BIC_GFX_J, 254 + BIC_RAM_J, 255 + BIC_Mod_c6, 256 + BIC_Totl_c0, 257 + BIC_Any_c0, 258 + BIC_GFX_c0, 259 + BIC_CPUGFX, 260 + BIC_Core, 261 + BIC_CPU, 262 + BIC_APIC, 263 + BIC_X2APIC, 264 + BIC_Die, 265 + BIC_L3, 266 + BIC_GFXACTMHz, 267 + BIC_IPC, 268 + BIC_CORE_THROT_CNT, 269 + BIC_UNCORE_MHZ, 270 + BIC_SAM_mc6, 271 + BIC_SAMMHz, 272 + BIC_SAMACTMHz, 273 + BIC_Diec6, 274 + BIC_SysWatt, 275 + BIC_Sys_J, 276 + BIC_NMI, 277 + BIC_CPU_c1e, 278 + BIC_pct_idle, 279 + MAX_BIC 280 + }; 279 281 280 - #define BIC_GROUP_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die) 281 - #define BIC_GROUP_THERMAL_PWR (BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__ | BIC_SysWatt) 282 - #define BIC_GROUP_FREQUENCY (BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_SAMMHz | BIC_SAMACTMHz | BIC_UNCORE_MHZ) 283 - #define BIC_GROUP_HW_IDLE (BIC_Busy | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX | BIC_SAM_mc6 | BIC_Diec6) 284 - #define BIC_GROUP_SW_IDLE (BIC_Busy | BIC_cpuidle | BIC_pct_idle ) 285 - #define BIC_GROUP_IDLE (BIC_GROUP_HW_IDLE | BIC_pct_idle) 286 - #define BIC_OTHER (BIC_IRQ | BIC_NMI | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC) 282 + void print_bic_set(char *s, cpu_set_t *set) 283 + { 284 + int i; 287 285 288 - #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC | BIC_cpuidle) 286 + assert(MAX_BIC < CPU_SETSIZE); 289 287 290 - unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 291 - unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_cpuidle | BIC_pct_idle | BIC_APIC | BIC_X2APIC; 288 + printf("%s:", s); 292 289 293 - #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 294 - #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 295 - #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 296 - #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 297 - #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 298 - #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT) 290 + for (i = 0; i <= MAX_BIC; ++i) { 291 + 292 + if (CPU_ISSET(i, set)) { 293 + assert(i < MAX_BIC); 294 + printf(" %s", bic[i].name); 295 + } 296 + } 297 + putchar('\n'); 298 + } 299 + 300 + static cpu_set_t bic_group_topology; 301 + static cpu_set_t bic_group_thermal_pwr; 302 + static cpu_set_t bic_group_frequency; 303 + static cpu_set_t bic_group_hw_idle; 304 + static cpu_set_t bic_group_sw_idle; 305 + static cpu_set_t bic_group_idle; 306 + static cpu_set_t bic_group_other; 307 + static cpu_set_t bic_group_disabled_by_default; 308 + static cpu_set_t bic_enabled; 309 + static cpu_set_t bic_present; 310 + 311 + /* modify */ 312 + #define BIC_INIT(set) CPU_ZERO(set) 313 + 314 + #define SET_BIC(COUNTER_NUMBER, set) CPU_SET(COUNTER_NUMBER, set) 315 + #define CLR_BIC(COUNTER_NUMBER, set) CPU_CLR(COUNTER_NUMBER, set) 316 + 317 + #define BIC_PRESENT(COUNTER_NUMBER) SET_BIC(COUNTER_NUMBER, &bic_present) 318 + #define BIC_NOT_PRESENT(COUNTER_NUMBER) CPU_CLR(COUNTER_NUMBER, &bic_present) 319 + 320 + /* test */ 321 + #define BIC_IS_ENABLED(COUNTER_NUMBER) CPU_ISSET(COUNTER_NUMBER, &bic_enabled) 322 + #define DO_BIC_READ(COUNTER_NUMBER) CPU_ISSET(COUNTER_NUMBER, &bic_present) 323 + #define DO_BIC(COUNTER_NUMBER) (CPU_ISSET(COUNTER_NUMBER, &bic_enabled) && CPU_ISSET(COUNTER_NUMBER, &bic_present)) 324 + 325 + static void bic_set_all(cpu_set_t *set) 326 + { 327 + int i; 328 + 329 + assert(MAX_BIC < CPU_SETSIZE); 330 + 331 + for (i = 0; i < MAX_BIC; ++i) 332 + SET_BIC(i, set); 333 + } 334 + 335 + /* 336 + * bic_clear_bits() 337 + * clear all the bits from "clr" in "dst" 338 + */ 339 + static void bic_clear_bits(cpu_set_t *dst, cpu_set_t *clr) 340 + { 341 + int i; 342 + 343 + assert(MAX_BIC < CPU_SETSIZE); 344 + 345 + for (i = 0; i < MAX_BIC; ++i) 346 + if (CPU_ISSET(i, clr)) 347 + CLR_BIC(i, dst); 348 + } 349 + 350 + static void bic_groups_init(void) 351 + { 352 + BIC_INIT(&bic_group_topology); 353 + SET_BIC(BIC_Package, &bic_group_topology); 354 + SET_BIC(BIC_Node, &bic_group_topology); 355 + SET_BIC(BIC_CoreCnt, &bic_group_topology); 356 + SET_BIC(BIC_PkgCnt, &bic_group_topology); 357 + SET_BIC(BIC_Core, &bic_group_topology); 358 + SET_BIC(BIC_CPU, &bic_group_topology); 359 + SET_BIC(BIC_Die, &bic_group_topology); 360 + SET_BIC(BIC_L3, &bic_group_topology); 361 + 362 + BIC_INIT(&bic_group_thermal_pwr); 363 + SET_BIC(BIC_CoreTmp, &bic_group_thermal_pwr); 364 + SET_BIC(BIC_PkgTmp, &bic_group_thermal_pwr); 365 + SET_BIC(BIC_PkgWatt, &bic_group_thermal_pwr); 366 + SET_BIC(BIC_CorWatt, &bic_group_thermal_pwr); 367 + SET_BIC(BIC_GFXWatt, &bic_group_thermal_pwr); 368 + SET_BIC(BIC_RAMWatt, &bic_group_thermal_pwr); 369 + SET_BIC(BIC_PKG__, &bic_group_thermal_pwr); 370 + SET_BIC(BIC_RAM__, &bic_group_thermal_pwr); 371 + SET_BIC(BIC_SysWatt, &bic_group_thermal_pwr); 372 + 373 + BIC_INIT(&bic_group_frequency); 374 + SET_BIC(BIC_Avg_MHz, &bic_group_frequency); 375 + SET_BIC(BIC_Busy, &bic_group_frequency); 376 + SET_BIC(BIC_Bzy_MHz, &bic_group_frequency); 377 + SET_BIC(BIC_TSC_MHz, &bic_group_frequency); 378 + SET_BIC(BIC_GFXMHz, &bic_group_frequency); 379 + SET_BIC(BIC_GFXACTMHz, &bic_group_frequency); 380 + SET_BIC(BIC_SAMMHz, &bic_group_frequency); 381 + SET_BIC(BIC_SAMACTMHz, &bic_group_frequency); 382 + SET_BIC(BIC_UNCORE_MHZ, &bic_group_frequency); 383 + 384 + BIC_INIT(&bic_group_hw_idle); 385 + SET_BIC(BIC_Busy, &bic_group_hw_idle); 386 + SET_BIC(BIC_CPU_c1, &bic_group_hw_idle); 387 + SET_BIC(BIC_CPU_c3, &bic_group_hw_idle); 388 + SET_BIC(BIC_CPU_c6, &bic_group_hw_idle); 389 + SET_BIC(BIC_CPU_c7, &bic_group_hw_idle); 390 + SET_BIC(BIC_GFX_rc6, &bic_group_hw_idle); 391 + SET_BIC(BIC_Pkgpc2, &bic_group_hw_idle); 392 + SET_BIC(BIC_Pkgpc3, &bic_group_hw_idle); 393 + SET_BIC(BIC_Pkgpc6, &bic_group_hw_idle); 394 + SET_BIC(BIC_Pkgpc7, &bic_group_hw_idle); 395 + SET_BIC(BIC_Pkgpc8, &bic_group_hw_idle); 396 + SET_BIC(BIC_Pkgpc9, &bic_group_hw_idle); 397 + SET_BIC(BIC_Pkgpc10, &bic_group_hw_idle); 398 + SET_BIC(BIC_CPU_LPI, &bic_group_hw_idle); 399 + SET_BIC(BIC_SYS_LPI, &bic_group_hw_idle); 400 + SET_BIC(BIC_Mod_c6, &bic_group_hw_idle); 401 + SET_BIC(BIC_Totl_c0, &bic_group_hw_idle); 402 + SET_BIC(BIC_Any_c0, &bic_group_hw_idle); 403 + SET_BIC(BIC_GFX_c0, &bic_group_hw_idle); 404 + SET_BIC(BIC_CPUGFX, &bic_group_hw_idle); 405 + SET_BIC(BIC_SAM_mc6, &bic_group_hw_idle); 406 + SET_BIC(BIC_Diec6, &bic_group_hw_idle); 407 + 408 + BIC_INIT(&bic_group_sw_idle); 409 + SET_BIC(BIC_Busy, &bic_group_sw_idle); 410 + SET_BIC(BIC_cpuidle, &bic_group_sw_idle); 411 + SET_BIC(BIC_pct_idle, &bic_group_sw_idle); 412 + 413 + BIC_INIT(&bic_group_idle); 414 + CPU_OR(&bic_group_idle, &bic_group_idle, &bic_group_hw_idle); 415 + SET_BIC(BIC_pct_idle, &bic_group_idle); 416 + 417 + BIC_INIT(&bic_group_other); 418 + SET_BIC(BIC_IRQ, &bic_group_other); 419 + SET_BIC(BIC_NMI, &bic_group_other); 420 + SET_BIC(BIC_SMI, &bic_group_other); 421 + SET_BIC(BIC_ThreadC, &bic_group_other); 422 + SET_BIC(BIC_CoreTmp, &bic_group_other); 423 + SET_BIC(BIC_IPC, &bic_group_other); 424 + 425 + BIC_INIT(&bic_group_disabled_by_default); 426 + SET_BIC(BIC_USEC, &bic_group_disabled_by_default); 427 + SET_BIC(BIC_TOD, &bic_group_disabled_by_default); 428 + SET_BIC(BIC_cpuidle, &bic_group_disabled_by_default); 429 + SET_BIC(BIC_APIC, &bic_group_disabled_by_default); 430 + SET_BIC(BIC_X2APIC, &bic_group_disabled_by_default); 431 + 432 + BIC_INIT(&bic_enabled); 433 + bic_set_all(&bic_enabled); 434 + bic_clear_bits(&bic_enabled, &bic_group_disabled_by_default); 435 + 436 + BIC_INIT(&bic_present); 437 + SET_BIC(BIC_USEC, &bic_present); 438 + SET_BIC(BIC_TOD, &bic_present); 439 + SET_BIC(BIC_cpuidle, &bic_present); 440 + SET_BIC(BIC_APIC, &bic_present); 441 + SET_BIC(BIC_X2APIC, &bic_present); 442 + SET_BIC(BIC_pct_idle, &bic_present); 443 + } 299 444 300 445 /* 301 446 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: ··· 989 840 }; 990 841 991 842 static const struct platform_features dmr_features = { 992 - .has_msr_misc_feature_control = spr_features.has_msr_misc_feature_control, 993 - .has_msr_misc_pwr_mgmt = spr_features.has_msr_misc_pwr_mgmt, 994 - .has_nhm_msrs = spr_features.has_nhm_msrs, 995 - .has_config_tdp = spr_features.has_config_tdp, 996 - .bclk_freq = spr_features.bclk_freq, 997 - .supported_cstates = spr_features.supported_cstates, 998 - .cst_limit = spr_features.cst_limit, 999 - .has_msr_core_c1_res = spr_features.has_msr_core_c1_res, 1000 - .has_msr_module_c6_res_ms = 1, /* DMR has Dual Core Module and MC6 MSR */ 1001 - .has_irtl_msrs = spr_features.has_irtl_msrs, 1002 - .has_cst_prewake_bit = spr_features.has_cst_prewake_bit, 1003 - .has_fixed_rapl_psys_unit = spr_features.has_fixed_rapl_psys_unit, 1004 - .trl_msrs = spr_features.trl_msrs, 1005 - .rapl_msrs = 0, /* DMR does not have RAPL MSRs */ 843 + .has_msr_misc_feature_control = spr_features.has_msr_misc_feature_control, 844 + .has_msr_misc_pwr_mgmt = spr_features.has_msr_misc_pwr_mgmt, 845 + .has_nhm_msrs = spr_features.has_nhm_msrs, 846 + .bclk_freq = spr_features.bclk_freq, 847 + .supported_cstates = spr_features.supported_cstates, 848 + .cst_limit = spr_features.cst_limit, 849 + .has_msr_core_c1_res = spr_features.has_msr_core_c1_res, 850 + .has_cst_prewake_bit = spr_features.has_cst_prewake_bit, 851 + .has_fixed_rapl_psys_unit = spr_features.has_fixed_rapl_psys_unit, 852 + .trl_msrs = spr_features.trl_msrs, 853 + .has_msr_module_c6_res_ms = 1, /* DMR has Dual-Core-Module and MC6 MSR */ 854 + .rapl_msrs = 0, /* DMR does not have RAPL MSRs */ 855 + .plr_msrs = 0, /* DMR does not have PLR MSRs */ 856 + .has_irtl_msrs = 0, /* DMR does not have IRTL MSRs */ 857 + .has_config_tdp = 0, /* DMR does not have CTDP MSRs */ 1006 858 }; 1007 859 1008 860 static const struct platform_features srf_features = { ··· 1354 1204 int msr_shift; /* Positive mean shift right, negative mean shift left */ 1355 1205 double *platform_rapl_msr_scale; /* Scale applied to values read by MSR (platform dependent, filled at runtime) */ 1356 1206 unsigned int rci_index; /* Maps data from perf counters to global variables */ 1357 - unsigned long long bic; 1207 + unsigned int bic_number; 1358 1208 double compat_scale; /* Some counters require constant scaling to be in the same range as other, similar ones */ 1359 1209 unsigned long long flags; 1360 1210 }; ··· 1369 1219 .msr_shift = 0, 1370 1220 .platform_rapl_msr_scale = &rapl_energy_units, 1371 1221 .rci_index = RAPL_RCI_INDEX_ENERGY_PKG, 1372 - .bic = BIC_PkgWatt | BIC_Pkg_J, 1222 + .bic_number = BIC_PkgWatt, 1223 + .compat_scale = 1.0, 1224 + .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1225 + }, 1226 + { 1227 + .feature_mask = RAPL_PKG, 1228 + .perf_subsys = "power", 1229 + .perf_name = "energy-pkg", 1230 + .msr = MSR_PKG_ENERGY_STATUS, 1231 + .msr_mask = 0xFFFFFFFFFFFFFFFF, 1232 + .msr_shift = 0, 1233 + .platform_rapl_msr_scale = &rapl_energy_units, 1234 + .rci_index = RAPL_RCI_INDEX_ENERGY_PKG, 1235 + .bic_number = BIC_Pkg_J, 1373 1236 .compat_scale = 1.0, 1374 1237 .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1375 1238 }, ··· 1395 1232 .msr_shift = 0, 1396 1233 .platform_rapl_msr_scale = &rapl_energy_units, 1397 1234 .rci_index = RAPL_RCI_INDEX_ENERGY_PKG, 1398 - .bic = BIC_PkgWatt | BIC_Pkg_J, 1235 + .bic_number = BIC_PkgWatt, 1236 + .compat_scale = 1.0, 1237 + .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1238 + }, 1239 + { 1240 + .feature_mask = RAPL_AMD_F17H, 1241 + .perf_subsys = "power", 1242 + .perf_name = "energy-pkg", 1243 + .msr = MSR_PKG_ENERGY_STAT, 1244 + .msr_mask = 0xFFFFFFFFFFFFFFFF, 1245 + .msr_shift = 0, 1246 + .platform_rapl_msr_scale = &rapl_energy_units, 1247 + .rci_index = RAPL_RCI_INDEX_ENERGY_PKG, 1248 + .bic_number = BIC_Pkg_J, 1399 1249 .compat_scale = 1.0, 1400 1250 .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1401 1251 }, ··· 1421 1245 .msr_shift = 0, 1422 1246 .platform_rapl_msr_scale = &rapl_energy_units, 1423 1247 .rci_index = RAPL_RCI_INDEX_ENERGY_CORES, 1424 - .bic = BIC_CorWatt | BIC_Cor_J, 1248 + .bic_number = BIC_CorWatt, 1249 + .compat_scale = 1.0, 1250 + .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1251 + }, 1252 + { 1253 + .feature_mask = RAPL_CORE_ENERGY_STATUS, 1254 + .perf_subsys = "power", 1255 + .perf_name = "energy-cores", 1256 + .msr = MSR_PP0_ENERGY_STATUS, 1257 + .msr_mask = 0xFFFFFFFFFFFFFFFF, 1258 + .msr_shift = 0, 1259 + .platform_rapl_msr_scale = &rapl_energy_units, 1260 + .rci_index = RAPL_RCI_INDEX_ENERGY_CORES, 1261 + .bic_number = BIC_Cor_J, 1425 1262 .compat_scale = 1.0, 1426 1263 .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1427 1264 }, ··· 1447 1258 .msr_shift = 0, 1448 1259 .platform_rapl_msr_scale = &rapl_dram_energy_units, 1449 1260 .rci_index = RAPL_RCI_INDEX_DRAM, 1450 - .bic = BIC_RAMWatt | BIC_RAM_J, 1261 + .bic_number = BIC_RAMWatt, 1262 + .compat_scale = 1.0, 1263 + .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1264 + }, 1265 + { 1266 + .feature_mask = RAPL_DRAM, 1267 + .perf_subsys = "power", 1268 + .perf_name = "energy-ram", 1269 + .msr = MSR_DRAM_ENERGY_STATUS, 1270 + .msr_mask = 0xFFFFFFFFFFFFFFFF, 1271 + .msr_shift = 0, 1272 + .platform_rapl_msr_scale = &rapl_dram_energy_units, 1273 + .rci_index = RAPL_RCI_INDEX_DRAM, 1274 + .bic_number = BIC_RAM_J, 1451 1275 .compat_scale = 1.0, 1452 1276 .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1453 1277 }, ··· 1473 1271 .msr_shift = 0, 1474 1272 .platform_rapl_msr_scale = &rapl_energy_units, 1475 1273 .rci_index = RAPL_RCI_INDEX_GFX, 1476 - .bic = BIC_GFXWatt | BIC_GFX_J, 1274 + .bic_number = BIC_GFXWatt, 1275 + .compat_scale = 1.0, 1276 + .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1277 + }, 1278 + { 1279 + .feature_mask = RAPL_GFX, 1280 + .perf_subsys = "power", 1281 + .perf_name = "energy-gpu", 1282 + .msr = MSR_PP1_ENERGY_STATUS, 1283 + .msr_mask = 0xFFFFFFFFFFFFFFFF, 1284 + .msr_shift = 0, 1285 + .platform_rapl_msr_scale = &rapl_energy_units, 1286 + .rci_index = RAPL_RCI_INDEX_GFX, 1287 + .bic_number = BIC_GFX_J, 1477 1288 .compat_scale = 1.0, 1478 1289 .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1479 1290 }, ··· 1499 1284 .msr_shift = 0, 1500 1285 .platform_rapl_msr_scale = &rapl_time_units, 1501 1286 .rci_index = RAPL_RCI_INDEX_PKG_PERF_STATUS, 1502 - .bic = BIC_PKG__, 1287 + .bic_number = BIC_PKG__, 1503 1288 .compat_scale = 100.0, 1504 1289 .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1505 1290 }, ··· 1512 1297 .msr_shift = 0, 1513 1298 .platform_rapl_msr_scale = &rapl_time_units, 1514 1299 .rci_index = RAPL_RCI_INDEX_DRAM_PERF_STATUS, 1515 - .bic = BIC_RAM__, 1300 + .bic_number = BIC_RAM__, 1516 1301 .compat_scale = 100.0, 1517 1302 .flags = RAPL_COUNTER_FLAG_USE_MSR_SUM, 1518 1303 }, ··· 1525 1310 .msr_shift = 0, 1526 1311 .platform_rapl_msr_scale = &rapl_energy_units, 1527 1312 .rci_index = RAPL_RCI_INDEX_CORE_ENERGY, 1528 - .bic = BIC_CorWatt | BIC_Cor_J, 1313 + .bic_number = BIC_CorWatt, 1314 + .compat_scale = 1.0, 1315 + .flags = 0, 1316 + }, 1317 + { 1318 + .feature_mask = RAPL_AMD_F17H, 1319 + .perf_subsys = NULL, 1320 + .perf_name = NULL, 1321 + .msr = MSR_CORE_ENERGY_STAT, 1322 + .msr_mask = 0xFFFFFFFF, 1323 + .msr_shift = 0, 1324 + .platform_rapl_msr_scale = &rapl_energy_units, 1325 + .rci_index = RAPL_RCI_INDEX_CORE_ENERGY, 1326 + .bic_number = BIC_Cor_J, 1529 1327 .compat_scale = 1.0, 1530 1328 .flags = 0, 1531 1329 }, ··· 1551 1323 .msr_shift = 0, 1552 1324 .platform_rapl_msr_scale = &rapl_psys_energy_units, 1553 1325 .rci_index = RAPL_RCI_INDEX_ENERGY_PLATFORM, 1554 - .bic = BIC_SysWatt | BIC_Sys_J, 1326 + .bic_number = BIC_SysWatt, 1327 + .compat_scale = 1.0, 1328 + .flags = RAPL_COUNTER_FLAG_PLATFORM_COUNTER | RAPL_COUNTER_FLAG_USE_MSR_SUM, 1329 + }, 1330 + { 1331 + .feature_mask = RAPL_PSYS, 1332 + .perf_subsys = "power", 1333 + .perf_name = "energy-psys", 1334 + .msr = MSR_PLATFORM_ENERGY_STATUS, 1335 + .msr_mask = 0x00000000FFFFFFFF, 1336 + .msr_shift = 0, 1337 + .platform_rapl_msr_scale = &rapl_psys_energy_units, 1338 + .rci_index = RAPL_RCI_INDEX_ENERGY_PLATFORM, 1339 + .bic_number = BIC_Sys_J, 1555 1340 .compat_scale = 1.0, 1556 1341 .flags = RAPL_COUNTER_FLAG_PLATFORM_COUNTER | RAPL_COUNTER_FLAG_USE_MSR_SUM, 1557 1342 }, ··· 1613 1372 const char *perf_name; 1614 1373 unsigned long long msr; 1615 1374 unsigned int rci_index; /* Maps data from perf counters to global variables */ 1616 - unsigned long long bic; 1375 + unsigned int bic_number; 1617 1376 unsigned long long flags; 1618 1377 int pkg_cstate_limit; 1619 1378 }; ··· 1625 1384 .perf_name = "c1-residency", 1626 1385 .msr = MSR_CORE_C1_RES, 1627 1386 .rci_index = CCSTATE_RCI_INDEX_C1_RESIDENCY, 1628 - .bic = BIC_CPU_c1, 1387 + .bic_number = BIC_CPU_c1, 1629 1388 .flags = CSTATE_COUNTER_FLAG_COLLECT_PER_THREAD, 1630 1389 .pkg_cstate_limit = 0, 1631 1390 }, ··· 1635 1394 .perf_name = "c3-residency", 1636 1395 .msr = MSR_CORE_C3_RESIDENCY, 1637 1396 .rci_index = CCSTATE_RCI_INDEX_C3_RESIDENCY, 1638 - .bic = BIC_CPU_c3, 1397 + .bic_number = BIC_CPU_c3, 1639 1398 .flags = CSTATE_COUNTER_FLAG_COLLECT_PER_CORE | CSTATE_COUNTER_FLAG_SOFT_C1_DEPENDENCY, 1640 1399 .pkg_cstate_limit = 0, 1641 1400 }, ··· 1645 1404 .perf_name = "c6-residency", 1646 1405 .msr = MSR_CORE_C6_RESIDENCY, 1647 1406 .rci_index = CCSTATE_RCI_INDEX_C6_RESIDENCY, 1648 - .bic = BIC_CPU_c6, 1407 + .bic_number = BIC_CPU_c6, 1649 1408 .flags = CSTATE_COUNTER_FLAG_COLLECT_PER_CORE | CSTATE_COUNTER_FLAG_SOFT_C1_DEPENDENCY, 1650 1409 .pkg_cstate_limit = 0, 1651 1410 }, ··· 1655 1414 .perf_name = "c7-residency", 1656 1415 .msr = MSR_CORE_C7_RESIDENCY, 1657 1416 .rci_index = CCSTATE_RCI_INDEX_C7_RESIDENCY, 1658 - .bic = BIC_CPU_c7, 1417 + .bic_number = BIC_CPU_c7, 1659 1418 .flags = CSTATE_COUNTER_FLAG_COLLECT_PER_CORE | CSTATE_COUNTER_FLAG_SOFT_C1_DEPENDENCY, 1660 1419 .pkg_cstate_limit = 0, 1661 1420 }, ··· 1665 1424 .perf_name = "c2-residency", 1666 1425 .msr = MSR_PKG_C2_RESIDENCY, 1667 1426 .rci_index = PCSTATE_RCI_INDEX_C2_RESIDENCY, 1668 - .bic = BIC_Pkgpc2, 1427 + .bic_number = BIC_Pkgpc2, 1669 1428 .flags = 0, 1670 1429 .pkg_cstate_limit = PCL__2, 1671 1430 }, ··· 1675 1434 .perf_name = "c3-residency", 1676 1435 .msr = MSR_PKG_C3_RESIDENCY, 1677 1436 .rci_index = PCSTATE_RCI_INDEX_C3_RESIDENCY, 1678 - .bic = BIC_Pkgpc3, 1437 + .bic_number = BIC_Pkgpc3, 1679 1438 .flags = 0, 1680 1439 .pkg_cstate_limit = PCL__3, 1681 1440 }, ··· 1685 1444 .perf_name = "c6-residency", 1686 1445 .msr = MSR_PKG_C6_RESIDENCY, 1687 1446 .rci_index = PCSTATE_RCI_INDEX_C6_RESIDENCY, 1688 - .bic = BIC_Pkgpc6, 1447 + .bic_number = BIC_Pkgpc6, 1689 1448 .flags = 0, 1690 1449 .pkg_cstate_limit = PCL__6, 1691 1450 }, ··· 1695 1454 .perf_name = "c7-residency", 1696 1455 .msr = MSR_PKG_C7_RESIDENCY, 1697 1456 .rci_index = PCSTATE_RCI_INDEX_C7_RESIDENCY, 1698 - .bic = BIC_Pkgpc7, 1457 + .bic_number = BIC_Pkgpc7, 1699 1458 .flags = 0, 1700 1459 .pkg_cstate_limit = PCL__7, 1701 1460 }, ··· 1705 1464 .perf_name = "c8-residency", 1706 1465 .msr = MSR_PKG_C8_RESIDENCY, 1707 1466 .rci_index = PCSTATE_RCI_INDEX_C8_RESIDENCY, 1708 - .bic = BIC_Pkgpc8, 1467 + .bic_number = BIC_Pkgpc8, 1709 1468 .flags = 0, 1710 1469 .pkg_cstate_limit = PCL__8, 1711 1470 }, ··· 1715 1474 .perf_name = "c9-residency", 1716 1475 .msr = MSR_PKG_C9_RESIDENCY, 1717 1476 .rci_index = PCSTATE_RCI_INDEX_C9_RESIDENCY, 1718 - .bic = BIC_Pkgpc9, 1477 + .bic_number = BIC_Pkgpc9, 1719 1478 .flags = 0, 1720 1479 .pkg_cstate_limit = PCL__9, 1721 1480 }, ··· 1725 1484 .perf_name = "c10-residency", 1726 1485 .msr = MSR_PKG_C10_RESIDENCY, 1727 1486 .rci_index = PCSTATE_RCI_INDEX_C10_RESIDENCY, 1728 - .bic = BIC_Pkgpc10, 1487 + .bic_number = BIC_Pkgpc10, 1729 1488 .flags = 0, 1730 1489 .pkg_cstate_limit = PCL_10, 1731 1490 }, ··· 2081 1840 ((node_no) * topo.cores_per_node) + \ 2082 1841 (core_no)) 2083 1842 2084 - #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 2085 - 2086 1843 /* 2087 1844 * The accumulated sum of MSR is defined as a monotonic 2088 1845 * increasing MSR, it will be accumulated periodically, ··· 2275 2036 struct cpu_topology { 2276 2037 int physical_package_id; 2277 2038 int die_id; 2039 + int l3_id; 2278 2040 int logical_cpu_id; 2279 2041 int physical_node_id; 2280 2042 int logical_node_id; /* 0-based count within the package */ ··· 2297 2057 int max_core_id; 2298 2058 int max_package_id; 2299 2059 int max_die_id; 2060 + int max_l3_id; 2300 2061 int max_node_num; 2301 2062 int nodes_per_pkg; 2302 2063 int cores_per_node; ··· 2331 2090 * skip non-present cpus 2332 2091 */ 2333 2092 2093 + #define PER_THREAD_PARAMS struct thread_data *t, struct core_data *c, struct pkg_data *p 2094 + 2334 2095 int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *), 2335 2096 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 2336 2097 { ··· 2346 2103 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 2347 2104 struct thread_data *t; 2348 2105 struct core_data *c; 2349 - struct pkg_data *p; 2106 + 2350 2107 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 2351 2108 2352 2109 if (cpu_is_not_allowed(t->cpu_id)) 2353 2110 continue; 2354 2111 2355 2112 c = GET_CORE(core_base, core_no, node_no, pkg_no); 2356 - p = GET_PKG(pkg_base, pkg_no); 2357 2113 2358 - retval |= func(t, c, p); 2114 + retval |= func(t, c, &pkg_base[pkg_no]); 2359 2115 } 2360 2116 } 2361 2117 } ··· 2362 2120 return retval; 2363 2121 } 2364 2122 2365 - int is_cpu_first_thread_in_core(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2123 + int is_cpu_first_thread_in_core(PER_THREAD_PARAMS) 2366 2124 { 2367 2125 UNUSED(p); 2368 2126 2369 2127 return ((int)t->cpu_id == c->base_cpu || c->base_cpu < 0); 2370 2128 } 2371 2129 2372 - int is_cpu_first_core_in_package(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2130 + int is_cpu_first_core_in_package(PER_THREAD_PARAMS) 2373 2131 { 2374 2132 UNUSED(c); 2375 2133 2376 2134 return ((int)t->cpu_id == p->base_cpu || p->base_cpu < 0); 2377 2135 } 2378 2136 2379 - int is_cpu_first_thread_in_package(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2137 + int is_cpu_first_thread_in_package(PER_THREAD_PARAMS) 2380 2138 { 2381 2139 return is_cpu_first_thread_in_core(t, c, p) && is_cpu_first_core_in_package(t, c, p); 2382 2140 } ··· 2421 2179 2422 2180 static void bic_disable_msr_access(void) 2423 2181 { 2424 - const unsigned long bic_msrs = BIC_Mod_c6 | BIC_CoreTmp | 2425 - BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX | BIC_PkgTmp; 2426 - 2427 - bic_enabled &= ~bic_msrs; 2182 + CLR_BIC(BIC_Mod_c6, &bic_enabled); 2183 + CLR_BIC(BIC_CoreTmp, &bic_enabled); 2184 + CLR_BIC(BIC_Totl_c0, &bic_enabled); 2185 + CLR_BIC(BIC_Any_c0, &bic_enabled); 2186 + CLR_BIC(BIC_GFX_c0, &bic_enabled); 2187 + CLR_BIC(BIC_CPUGFX, &bic_enabled); 2188 + CLR_BIC(BIC_PkgTmp, &bic_enabled); 2428 2189 2429 2190 free_sys_msr_counters(); 2430 2191 } ··· 2555 2310 char *deferred_skip_names[MAX_DEFERRED]; 2556 2311 int deferred_add_index; 2557 2312 int deferred_skip_index; 2313 + unsigned int deferred_add_consumed; 2314 + unsigned int deferred_skip_consumed; 2558 2315 2559 2316 /* 2560 2317 * HIDE_LIST - hide this list of counters, show the rest [default] ··· 2627 2380 * for all the strings in comma separate name_list, 2628 2381 * set the approprate bit in return value. 2629 2382 */ 2630 - unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 2383 + void bic_lookup(cpu_set_t *ret_set, char *name_list, enum show_hide_mode mode) 2631 2384 { 2632 2385 unsigned int i; 2633 - unsigned long long retval = 0; 2634 2386 2635 2387 while (name_list) { 2636 2388 char *comma; ··· 2641 2395 2642 2396 for (i = 0; i < MAX_BIC; ++i) { 2643 2397 if (!strcmp(name_list, bic[i].name)) { 2644 - retval |= (1ULL << i); 2398 + SET_BIC(i, ret_set); 2645 2399 break; 2646 2400 } 2647 2401 if (!strcmp(name_list, "all")) { 2648 - retval |= ~0; 2402 + bic_set_all(ret_set); 2649 2403 break; 2650 2404 } else if (!strcmp(name_list, "topology")) { 2651 - retval |= BIC_GROUP_TOPOLOGY; 2405 + CPU_OR(ret_set, ret_set, &bic_group_topology); 2652 2406 break; 2653 2407 } else if (!strcmp(name_list, "power")) { 2654 - retval |= BIC_GROUP_THERMAL_PWR; 2408 + CPU_OR(ret_set, ret_set, &bic_group_thermal_pwr); 2655 2409 break; 2656 2410 } else if (!strcmp(name_list, "idle")) { 2657 - retval |= BIC_GROUP_IDLE; 2411 + CPU_OR(ret_set, ret_set, &bic_group_idle); 2658 2412 break; 2659 2413 } else if (!strcmp(name_list, "swidle")) { 2660 - retval |= BIC_GROUP_SW_IDLE; 2414 + CPU_OR(ret_set, ret_set, &bic_group_sw_idle); 2661 2415 break; 2662 2416 } else if (!strcmp(name_list, "sysfs")) { /* legacy compatibility */ 2663 - retval |= BIC_GROUP_SW_IDLE; 2417 + CPU_OR(ret_set, ret_set, &bic_group_sw_idle); 2664 2418 break; 2665 2419 } else if (!strcmp(name_list, "hwidle")) { 2666 - retval |= BIC_GROUP_HW_IDLE; 2420 + CPU_OR(ret_set, ret_set, &bic_group_hw_idle); 2667 2421 break; 2668 2422 } else if (!strcmp(name_list, "frequency")) { 2669 - retval |= BIC_GROUP_FREQUENCY; 2423 + CPU_OR(ret_set, ret_set, &bic_group_frequency); 2670 2424 break; 2671 2425 } else if (!strcmp(name_list, "other")) { 2672 - retval |= BIC_OTHER; 2426 + CPU_OR(ret_set, ret_set, &bic_group_other); 2673 2427 break; 2674 2428 } 2675 - 2676 2429 } 2677 2430 if (i == MAX_BIC) { 2678 - fprintf(stderr, "deferred %s\n", name_list); 2679 2431 if (mode == SHOW_LIST) { 2680 2432 deferred_add_names[deferred_add_index++] = name_list; 2681 2433 if (deferred_add_index >= MAX_DEFERRED) { ··· 2700 2456 name_list++; 2701 2457 2702 2458 } 2703 - return retval; 2704 2459 } 2705 2460 2706 2461 void print_header(char *delim) ··· 2717 2474 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 2718 2475 if (DO_BIC(BIC_Die)) 2719 2476 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 2477 + if (DO_BIC(BIC_L3)) 2478 + outp += sprintf(outp, "%sL3", (printed++ ? delim : "")); 2720 2479 if (DO_BIC(BIC_Node)) 2721 2480 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 2722 2481 if (DO_BIC(BIC_Core)) ··· 2759 2514 2760 2515 for (mp = sys.tp; mp; mp = mp->next) { 2761 2516 2762 - if (mp->format == FORMAT_RAW) { 2517 + if (mp->format == FORMAT_RAW || mp->format == FORMAT_AVERAGE) { 2763 2518 if (mp->width == 64) 2764 2519 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 2765 2520 else ··· 2834 2589 } 2835 2590 2836 2591 for (mp = sys.cp; mp; mp = mp->next) { 2837 - if (mp->format == FORMAT_RAW) { 2592 + if (mp->format == FORMAT_RAW || mp->format == FORMAT_AVERAGE) { 2838 2593 if (mp->width == 64) 2839 2594 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 2840 2595 else ··· 2964 2719 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : "")); 2965 2720 2966 2721 for (mp = sys.pp; mp; mp = mp->next) { 2967 - if (mp->format == FORMAT_RAW) { 2722 + if (mp->format == FORMAT_RAW || mp->format == FORMAT_AVERAGE) { 2968 2723 if (mp->width == 64) 2969 2724 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 2970 2725 else if (mp->width == 32) ··· 3022 2777 outp += sprintf(outp, "\n"); 3023 2778 } 3024 2779 3025 - int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2780 + int dump_counters(PER_THREAD_PARAMS) 3026 2781 { 3027 2782 int i; 3028 2783 struct msr_counter *mp; ··· 3137 2892 /* 3138 2893 * column formatting convention & formats 3139 2894 */ 3140 - int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2895 + int format_counters(PER_THREAD_PARAMS) 3141 2896 { 3142 2897 static int count; 3143 2898 ··· 3190 2945 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 3191 2946 if (DO_BIC(BIC_Die)) 3192 2947 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 2948 + if (DO_BIC(BIC_L3)) 2949 + outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 3193 2950 if (DO_BIC(BIC_Node)) 3194 2951 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 3195 2952 if (DO_BIC(BIC_Core)) ··· 3212 2965 if (DO_BIC(BIC_Die)) { 3213 2966 if (c) 3214 2967 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 2968 + else 2969 + outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 2970 + } 2971 + if (DO_BIC(BIC_L3)) { 2972 + if (c) 2973 + outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].l3_id); 3215 2974 else 3216 2975 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 3217 2976 } ··· 3285 3032 3286 3033 /* Added counters */ 3287 3034 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 3288 - if (mp->format == FORMAT_RAW) { 3035 + if (mp->format == FORMAT_RAW || mp->format == FORMAT_AVERAGE) { 3289 3036 if (mp->width == 32) 3290 3037 outp += 3291 3038 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]); ··· 3382 3129 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt); 3383 3130 3384 3131 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 3385 - if (mp->format == FORMAT_RAW) { 3132 + if (mp->format == FORMAT_RAW || mp->format == FORMAT_AVERAGE) { 3386 3133 if (mp->width == 32) 3387 3134 outp += 3388 3135 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]); ··· 3581 3328 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz); 3582 3329 3583 3330 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 3584 - if (mp->format == FORMAT_RAW) { 3331 + if (mp->format == FORMAT_RAW || mp->format == FORMAT_AVERAGE) { 3585 3332 if (mp->width == 32) 3586 3333 outp += 3587 3334 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]); ··· 3679 3426 outp = output_buffer; 3680 3427 } 3681 3428 3682 - void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3429 + void format_all_counters(PER_THREAD_PARAMS) 3683 3430 { 3684 3431 static int count; 3685 3432 ··· 3758 3505 new->rapl_dram_perf_status.raw_value - old->rapl_dram_perf_status.raw_value; 3759 3506 3760 3507 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 3761 - if (mp->format == FORMAT_RAW) 3508 + if (mp->format == FORMAT_RAW || mp->format == FORMAT_AVERAGE) 3762 3509 old->counter[i] = new->counter[i]; 3763 3510 else if (mp->format == FORMAT_AVERAGE) 3764 3511 old->counter[i] = new->counter[i]; ··· 3802 3549 DELTA_WRAP32(new->core_energy.raw_value, old->core_energy.raw_value); 3803 3550 3804 3551 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 3805 - if (mp->format == FORMAT_RAW) 3552 + if (mp->format == FORMAT_RAW || mp->format == FORMAT_AVERAGE) 3806 3553 old->counter[i] = new->counter[i]; 3807 3554 else 3808 3555 old->counter[i] = new->counter[i] - old->counter[i]; ··· 3916 3663 old->smi_count = new->smi_count - old->smi_count; 3917 3664 3918 3665 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 3919 - if (mp->format == FORMAT_RAW) 3666 + if (mp->format == FORMAT_RAW || mp->format == FORMAT_AVERAGE) 3920 3667 old->counter[i] = new->counter[i]; 3921 3668 else 3922 3669 old->counter[i] = new->counter[i] - old->counter[i]; ··· 3970 3717 c->unit = RAPL_UNIT_INVALID; 3971 3718 } 3972 3719 3973 - void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3720 + void clear_counters(PER_THREAD_PARAMS) 3974 3721 { 3975 3722 int i; 3976 3723 struct msr_counter *mp; ··· 4067 3814 dst->raw_value += src->raw_value; 4068 3815 } 4069 3816 4070 - int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3817 + int sum_counters(PER_THREAD_PARAMS) 4071 3818 { 4072 3819 int i; 4073 3820 struct msr_counter *mp; ··· 4215 3962 * sum the counters for all cpus in the system 4216 3963 * compute the weighted average 4217 3964 */ 4218 - void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3965 + void compute_average(PER_THREAD_PARAMS) 4219 3966 { 4220 3967 int i; 4221 3968 struct msr_counter *mp; ··· 4798 4545 return NULL; 4799 4546 } 4800 4547 4801 - int get_cstate_counters(unsigned int cpu, struct thread_data *t, struct core_data *c, struct pkg_data *p) 4548 + int get_cstate_counters(unsigned int cpu, PER_THREAD_PARAMS) 4802 4549 { 4803 4550 /* 4804 4551 * Overcommit memory a little bit here, ··· 5098 4845 * migrate to cpu 5099 4846 * acquire and record local counters for that cpu 5100 4847 */ 5101 - int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4848 + int get_counters(PER_THREAD_PARAMS) 5102 4849 { 5103 4850 int cpu = t->cpu_id; 5104 4851 unsigned long long msr; ··· 5926 5673 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 5927 5674 } 5928 5675 5676 + int get_l3_id(int cpu) 5677 + { 5678 + return parse_int_file("/sys/devices/system/cpu/cpu%d/cache/index3/id", cpu); 5679 + } 5680 + 5929 5681 int get_core_id(int cpu) 5930 5682 { 5931 5683 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); ··· 6119 5861 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 6120 5862 struct thread_data *t, *t2; 6121 5863 struct core_data *c, *c2; 6122 - struct pkg_data *p, *p2; 6123 5864 6124 5865 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 6125 5866 ··· 6130 5873 c = GET_CORE(core_base, core_no, node_no, pkg_no); 6131 5874 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no); 6132 5875 6133 - p = GET_PKG(pkg_base, pkg_no); 6134 - p2 = GET_PKG(pkg_base2, pkg_no); 6135 - 6136 - retval |= func(t, c, p, t2, c2, p2); 5876 + retval |= func(t, c, &pkg_base[pkg_no], t2, c2, &pkg_base2[pkg_no]); 6137 5877 } 6138 5878 } 6139 5879 } ··· 6588 6334 timer_t timerid; 6589 6335 6590 6336 /* Timer callback, update the sum of MSRs periodically. */ 6591 - static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p) 6337 + static int update_msr_sum(PER_THREAD_PARAMS) 6592 6338 { 6593 6339 int i, ret; 6594 6340 int cpu = t->cpu_id; ··· 6826 6572 int ret = 0; 6827 6573 6828 6574 caps = cap_get_proc(); 6829 - if (caps == NULL) 6575 + if (caps == NULL) { 6576 + /* 6577 + * CONFIG_MULTIUSER=n kernels have no cap_get_proc() 6578 + * Allow them to continue and attempt to access MSRs 6579 + */ 6580 + if (errno == ENOSYS) 6581 + return 0; 6582 + 6830 6583 return 1; 6584 + } 6831 6585 6832 6586 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value)) { 6833 6587 ret = 1; ··· 7002 6740 sprintf(path_base, "/sys/devices/system/cpu/intel_uncore_frequency/package_%02d_die_%02d", i, 7003 6741 j); 7004 6742 7005 - if (access(path_base, R_OK)) 6743 + sprintf(path, "%s/current_freq_khz", path_base); 6744 + if (access(path, R_OK)) 7006 6745 continue; 7007 6746 7008 6747 BIC_PRESENT(BIC_UNCORE_MHZ); ··· 7335 7072 * print_epb() 7336 7073 * Decode the ENERGY_PERF_BIAS MSR 7337 7074 */ 7338 - int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 7075 + int print_epb(PER_THREAD_PARAMS) 7339 7076 { 7340 7077 char *epb_string; 7341 7078 int cpu, epb; ··· 7384 7121 * print_hwp() 7385 7122 * Decode the MSR_HWP_CAPABILITIES 7386 7123 */ 7387 - int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 7124 + int print_hwp(PER_THREAD_PARAMS) 7388 7125 { 7389 7126 unsigned long long msr; 7390 7127 int cpu; ··· 7473 7210 /* 7474 7211 * print_perf_limit() 7475 7212 */ 7476 - int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 7213 + int print_perf_limit(PER_THREAD_PARAMS) 7477 7214 { 7478 7215 unsigned long long msr; 7479 7216 int cpu; ··· 7598 7335 unsigned long long msr; 7599 7336 unsigned int time_unit; 7600 7337 double tdp; 7601 - const unsigned long long bic_watt_bits = BIC_SysWatt | BIC_PkgWatt | BIC_CorWatt | BIC_RAMWatt | BIC_GFXWatt; 7602 - const unsigned long long bic_joules_bits = BIC_Sys_J | BIC_Pkg_J | BIC_Cor_J | BIC_RAM_J | BIC_GFX_J; 7603 7338 7604 - if (rapl_joules) 7605 - bic_enabled &= ~bic_watt_bits; 7606 - else 7607 - bic_enabled &= ~bic_joules_bits; 7339 + if (rapl_joules) { 7340 + CLR_BIC(BIC_SysWatt, &bic_enabled); 7341 + CLR_BIC(BIC_PkgWatt, &bic_enabled); 7342 + CLR_BIC(BIC_CorWatt, &bic_enabled); 7343 + CLR_BIC(BIC_RAMWatt, &bic_enabled); 7344 + CLR_BIC(BIC_GFXWatt, &bic_enabled); 7345 + } else { 7346 + CLR_BIC(BIC_Sys_J, &bic_enabled); 7347 + CLR_BIC(BIC_Pkg_J, &bic_enabled); 7348 + CLR_BIC(BIC_Cor_J, &bic_enabled); 7349 + CLR_BIC(BIC_RAM_J, &bic_enabled); 7350 + CLR_BIC(BIC_GFX_J, &bic_enabled); 7351 + } 7608 7352 7609 7353 if (!platform->rapl_msrs || no_msr) 7610 7354 return; 7611 7355 7612 7356 if (!(platform->rapl_msrs & RAPL_PKG_PERF_STATUS)) 7613 - bic_enabled &= ~BIC_PKG__; 7357 + CLR_BIC(BIC_PKG__, &bic_enabled); 7614 7358 if (!(platform->rapl_msrs & RAPL_DRAM_PERF_STATUS)) 7615 - bic_enabled &= ~BIC_RAM__; 7359 + CLR_BIC(BIC_RAM__, &bic_enabled); 7616 7360 7617 7361 /* units on package 0, verify later other packages match */ 7618 7362 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) ··· 7658 7388 { 7659 7389 unsigned long long msr; 7660 7390 double tdp; 7661 - const unsigned long long bic_watt_bits = BIC_PkgWatt | BIC_CorWatt; 7662 - const unsigned long long bic_joules_bits = BIC_Pkg_J | BIC_Cor_J; 7663 7391 7664 - if (rapl_joules) 7665 - bic_enabled &= ~bic_watt_bits; 7666 - else 7667 - bic_enabled &= ~bic_joules_bits; 7392 + if (rapl_joules) { 7393 + CLR_BIC(BIC_SysWatt, &bic_enabled); 7394 + CLR_BIC(BIC_CorWatt, &bic_enabled); 7395 + } else { 7396 + CLR_BIC(BIC_Pkg_J, &bic_enabled); 7397 + CLR_BIC(BIC_Cor_J, &bic_enabled); 7398 + } 7668 7399 7669 7400 if (!platform->rapl_msrs || no_msr) 7670 7401 return; ··· 7848 7577 return 0; 7849 7578 } 7850 7579 7851 - int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 7580 + int print_rapl(PER_THREAD_PARAMS) 7852 7581 { 7853 7582 unsigned long long msr; 7854 7583 const char *msr_name; ··· 8002 7731 * below this value, including the Digital Thermal Sensor (DTS), 8003 7732 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 8004 7733 */ 8005 - int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 7734 + int set_temperature_target(PER_THREAD_PARAMS) 8006 7735 { 8007 7736 unsigned long long msr; 8008 7737 unsigned int tcc_default, tcc_offset; ··· 8070 7799 return 0; 8071 7800 } 8072 7801 8073 - int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 7802 + int print_thermal(PER_THREAD_PARAMS) 8074 7803 { 8075 7804 unsigned long long msr; 8076 7805 unsigned int dts, dts2; ··· 8150 7879 for_all_cpus(print_thermal, ODD_COUNTERS); 8151 7880 } 8152 7881 8153 - int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p) 7882 + int get_cpu_type(PER_THREAD_PARAMS) 8154 7883 { 8155 7884 unsigned int eax, ebx, ecx, edx; 8156 7885 ··· 8412 8141 enum rapl_unit unit; 8413 8142 unsigned int next_domain; 8414 8143 8415 - if (!BIC_IS_ENABLED(cai->bic)) 8144 + if (!BIC_IS_ENABLED(cai->bic_number)) 8416 8145 continue; 8417 8146 8418 8147 memset(domain_visited, 0, num_domains * sizeof(*domain_visited)); ··· 8476 8205 8477 8206 /* If any CPU has access to the counter, make it present */ 8478 8207 if (has_counter) 8479 - BIC_PRESENT(cai->bic); 8208 + BIC_PRESENT(cai->bic_number); 8480 8209 } 8481 8210 8482 8211 free(domain_visited); ··· 8697 8426 if (!per_core && pkg_visited[pkg_id]) 8698 8427 continue; 8699 8428 8700 - const bool counter_needed = BIC_IS_ENABLED(cai->bic) || 8429 + const bool counter_needed = BIC_IS_ENABLED(cai->bic_number) || 8701 8430 (soft_c1 && (cai->flags & CSTATE_COUNTER_FLAG_SOFT_C1_DEPENDENCY)); 8702 8431 const bool counter_supported = (platform->supported_cstates & cai->feature_mask); 8703 8432 ··· 8724 8453 8725 8454 /* If any CPU has access to the counter, make it present */ 8726 8455 if (has_counter) 8727 - BIC_PRESENT(cai->bic); 8456 + BIC_PRESENT(cai->bic_number); 8728 8457 } 8729 8458 8730 8459 free(cores_visited); ··· 9220 8949 if (cpus[i].die_id > topo.max_die_id) 9221 8950 topo.max_die_id = cpus[i].die_id; 9222 8951 8952 + /* get l3 information */ 8953 + cpus[i].l3_id = get_l3_id(i); 8954 + if (cpus[i].l3_id > topo.max_l3_id) 8955 + topo.max_l3_id = cpus[i].l3_id; 8956 + 9223 8957 /* get numa node information */ 9224 8958 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 9225 8959 if (cpus[i].physical_node_id > topo.max_node_num) ··· 9257 8981 if (!summary_only && topo.num_die > 1) 9258 8982 BIC_PRESENT(BIC_Die); 9259 8983 8984 + if (!summary_only && topo.max_l3_id > 0) 8985 + BIC_PRESENT(BIC_L3); 8986 + 9260 8987 topo.num_packages = max_package_id + 1; 9261 8988 if (debug > 1) 9262 8989 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages); ··· 9283 9004 if (cpu_is_not_present(i)) 9284 9005 continue; 9285 9006 fprintf(outf, 9286 - "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 9287 - i, cpus[i].physical_package_id, cpus[i].die_id, 9007 + "cpu %d pkg %d die %d l3 %d node %d lnode %d core %d thread %d\n", 9008 + i, cpus[i].physical_package_id, cpus[i].die_id, cpus[i].l3_id, 9288 9009 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id); 9289 9010 } 9290 9011 ··· 9339 9060 int thread_id = cpus[cpu_id].thread_id; 9340 9061 struct thread_data *t; 9341 9062 struct core_data *c; 9342 - struct pkg_data *p; 9343 9063 9344 9064 /* Workaround for systems where physical_node_id==-1 9345 9065 * and logical_node_id==(-1 - topo.num_cpus) ··· 9348 9070 9349 9071 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 9350 9072 c = GET_CORE(core_base, core_id, node_id, pkg_id); 9351 - p = GET_PKG(pkg_base, pkg_id); 9352 9073 9353 9074 t->cpu_id = cpu_id; 9354 9075 if (!cpu_is_not_allowed(cpu_id)) { 9355 9076 if (c->base_cpu < 0) 9356 9077 c->base_cpu = t->cpu_id; 9357 - if (p->base_cpu < 0) 9358 - p->base_cpu = t->cpu_id; 9078 + if (pkg_base[pkg_id].base_cpu < 0) 9079 + pkg_base[pkg_id].base_cpu = t->cpu_id; 9359 9080 } 9360 9081 9361 9082 c->core_id = core_id; 9362 - p->package_id = pkg_id; 9083 + pkg_base[pkg_id].package_id = pkg_id; 9363 9084 } 9364 9085 9365 9086 int initialize_counters(int cpu_id) ··· 9398 9121 err(-1, "calloc %d NMI", topo.max_cpu_num + 1); 9399 9122 } 9400 9123 9401 - int update_topo(struct thread_data *t, struct core_data *c, struct pkg_data *p) 9124 + int update_topo(PER_THREAD_PARAMS) 9402 9125 { 9403 9126 topo.allowed_cpus++; 9404 9127 if ((int)t->cpu_id == c->base_cpu) ··· 9466 9189 void check_perf_access(void) 9467 9190 { 9468 9191 if (no_perf || !BIC_IS_ENABLED(BIC_IPC) || !has_instr_count_access()) 9469 - bic_enabled &= ~BIC_IPC; 9192 + CLR_BIC(BIC_IPC, &bic_enabled); 9470 9193 } 9471 9194 9472 9195 bool perf_has_hybrid_devices(void) ··· 10035 9758 * disable more BICs, since it can't be reported accurately. 10036 9759 */ 10037 9760 if (platform->enable_tsc_tweak && !has_base_hz) { 10038 - bic_enabled &= ~BIC_Busy; 10039 - bic_enabled &= ~BIC_Bzy_MHz; 9761 + CLR_BIC(BIC_Busy, &bic_enabled); 9762 + CLR_BIC(BIC_Bzy_MHz, &bic_enabled); 10040 9763 } 10041 9764 } 10042 9765 ··· 10094 9817 timersub(&tv_odd, &tv_even, &tv_delta); 10095 9818 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 10096 9819 fprintf(outf, "%s: Counter reset detected\n", progname); 9820 + delta_platform(&platform_counters_odd, &platform_counters_even); 10097 9821 10098 9822 compute_average(EVEN_COUNTERS); 10099 9823 format_all_counters(EVEN_COUNTERS); ··· 10126 9848 10127 9849 void print_version() 10128 9850 { 10129 - fprintf(outf, "turbostat version 2025.06.08 - Len Brown <lenb@kernel.org>\n"); 9851 + fprintf(outf, "turbostat version 2025.09.09 - Len Brown <lenb@kernel.org>\n"); 10130 9852 } 10131 9853 10132 9854 #define COMMAND_LINE_SIZE 2048 ··· 10423 10145 format = FORMAT_RAW; 10424 10146 goto next; 10425 10147 } 10148 + if (!strncmp(add_command, "average", strlen("average"))) { 10149 + format = FORMAT_AVERAGE; 10150 + goto next; 10151 + } 10426 10152 if (!strncmp(add_command, "delta", strlen("delta"))) { 10427 10153 format = FORMAT_DELTA; 10428 10154 goto next; ··· 10699 10417 has_format = true; 10700 10418 } 10701 10419 10420 + if (strcmp("average", format_name) == 0) { 10421 + format = FORMAT_AVERAGE; 10422 + has_format = true; 10423 + } 10424 + 10702 10425 if (strcmp("delta", format_name) == 0) { 10703 10426 format = FORMAT_DELTA; 10704 10427 has_format = true; 10705 10428 } 10706 10429 10707 10430 if (!has_format) { 10708 - fprintf(stderr, "%s: Invalid format %s. Expected raw or delta\n", __func__, format_name); 10431 + fprintf(stderr, "%s: Invalid format %s. Expected raw, average or delta\n", 10432 + __func__, format_name); 10709 10433 exit(1); 10710 10434 } 10711 10435 } ··· 10801 10513 int i; 10802 10514 10803 10515 for (i = 0; i < deferred_add_index; ++i) 10804 - if (!strcmp(name, deferred_add_names[i])) 10516 + if (!strcmp(name, deferred_add_names[i])) { 10517 + deferred_add_consumed |= (1 << i); 10805 10518 return 1; 10519 + } 10806 10520 return 0; 10807 10521 } 10808 10522 ··· 10813 10523 int i; 10814 10524 10815 10525 for (i = 0; i < deferred_skip_index; ++i) 10816 - if (!strcmp(name, deferred_skip_names[i])) 10526 + if (!strcmp(name, deferred_skip_names[i])) { 10527 + deferred_skip_consumed |= (1 << i); 10817 10528 return 1; 10529 + } 10818 10530 return 0; 10531 + } 10532 + 10533 + void verify_deferred_consumed(void) 10534 + { 10535 + int i; 10536 + int fail = 0; 10537 + 10538 + for (i = 0; i < deferred_add_index; ++i) { 10539 + if (!(deferred_add_consumed & (1 << i))) { 10540 + warnx("Counter '%s' can not be added.", deferred_add_names[i]); 10541 + fail++; 10542 + } 10543 + } 10544 + for (i = 0; i < deferred_skip_index; ++i) { 10545 + if (!(deferred_skip_consumed & (1 << i))) { 10546 + warnx("Counter '%s' can not be skipped.", deferred_skip_names[i]); 10547 + fail++; 10548 + } 10549 + } 10550 + if (fail) 10551 + exit(-EINVAL); 10819 10552 } 10820 10553 10821 10554 void probe_cpuidle_residency(void) ··· 10849 10536 int state; 10850 10537 int min_state = 1024, max_state = 0; 10851 10538 char *sp; 10852 - 10853 - if (!DO_BIC(BIC_pct_idle)) 10854 - return; 10855 10539 10856 10540 for (state = 10; state >= 0; --state) { 10857 10541 ··· 11062 10752 no_perf = 1; 11063 10753 break; 11064 10754 case 'e': 11065 - /* --enable specified counter */ 11066 - bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 10755 + /* --enable specified counter, without clearning existing list */ 10756 + bic_lookup(&bic_enabled, optarg, SHOW_LIST); 11067 10757 break; 11068 10758 case 'f': 11069 10759 force_load++; 11070 10760 break; 11071 10761 case 'd': 11072 10762 debug++; 11073 - ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 10763 + bic_set_all(&bic_enabled); 11074 10764 break; 11075 10765 case 'H': 11076 10766 /* 11077 10767 * --hide: do not show those specified 11078 10768 * multiple invocations simply clear more bits in enabled mask 11079 10769 */ 11080 - bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 10770 + { 10771 + cpu_set_t bic_group_hide; 10772 + 10773 + BIC_INIT(&bic_group_hide); 10774 + 10775 + bic_lookup(&bic_group_hide, optarg, HIDE_LIST); 10776 + bic_clear_bits(&bic_enabled, &bic_group_hide); 10777 + } 11081 10778 break; 11082 10779 case 'h': 11083 10780 default: ··· 11108 10791 rapl_joules++; 11109 10792 break; 11110 10793 case 'l': 11111 - ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 10794 + bic_set_all(&bic_enabled); 11112 10795 list_header_only++; 11113 10796 quiet++; 11114 10797 break; ··· 11145 10828 * subsequent invocations can add to it. 11146 10829 */ 11147 10830 if (shown == 0) 11148 - bic_enabled = bic_lookup(optarg, SHOW_LIST); 11149 - else 11150 - bic_enabled |= bic_lookup(optarg, SHOW_LIST); 10831 + BIC_INIT(&bic_enabled); 10832 + bic_lookup(&bic_enabled, optarg, SHOW_LIST); 11151 10833 shown = 1; 11152 10834 break; 11153 10835 case 'S': ··· 11183 10867 { 11184 10868 int fd, ret; 11185 10869 10870 + bic_groups_init(); 10871 + 11186 10872 fd = open("/sys/fs/cgroup/cgroup.procs", O_WRONLY); 11187 10873 if (fd < 0) 11188 10874 goto skip_cgroup_setting; ··· 11206 10888 11207 10889 probe_cpuidle_residency(); 11208 10890 probe_cpuidle_counts(); 10891 + 10892 + verify_deferred_consumed(); 11209 10893 11210 10894 if (!getuid()) 11211 10895 set_rlimit();

Configure Feed

Configure Feed