tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'usb-4.2-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Pull USB driver fixes from Greg KH:
"Here's some USB driver fixes for 4.2-rc3.

The ususal number of gadget driver fixes are in here, along with some
new device ids and a build fix for the mn10300 arch which required
some symbols to be renamed in the mos7720 driver.

All have been in linux-next for a while with no reported issues"

* tag 'usb-4.2-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb:
USB: serial: Destroy serial_minors IDR on module exit
usb: gadget: f_midi: fix error recovery path
usb: phy: mxs: suspend to RAM causes NULL pointer dereference
usb: gadget: udc: fix free_irq() after request_irq() failed
usb: gadget: composite: Fix NULL pointer dereference
usb: gadget: f_fs: do not set cancel function on synchronous {read,write}
usb: f_mass_storage: limit number of reported LUNs
usb: dwc3: core: avoid NULL pointer dereference
usb: dwc2: embed storage for reg backup in struct dwc2_hsotg
usb: dwc2: host: allocate qtd before atomic enqueue
usb: dwc2: host: allocate qh before atomic enqueue
usb: musb: host: rely on port_mode to call musb_start()
USB: cp210x: add ID for Aruba Networks controllers
USB: mos7720: rename registers
USB: option: add 2020:4000 ID

Linus Torvalds 2b3eb6e3 1ea2a01c

+255 -229
+15 -40
drivers/usb/dwc2/core.c
··· 72 72 dev_dbg(hsotg->dev, "%s\n", __func__); 73 73 74 74 /* Backup Host regs */ 75 - hr = hsotg->hr_backup; 76 - if (!hr) { 77 - hr = devm_kzalloc(hsotg->dev, sizeof(*hr), GFP_KERNEL); 78 - if (!hr) { 79 - dev_err(hsotg->dev, "%s: can't allocate host regs\n", 80 - __func__); 81 - return -ENOMEM; 82 - } 83 - 84 - hsotg->hr_backup = hr; 85 - } 75 + hr = &hsotg->hr_backup; 86 76 hr->hcfg = readl(hsotg->regs + HCFG); 87 77 hr->haintmsk = readl(hsotg->regs + HAINTMSK); 88 78 for (i = 0; i < hsotg->core_params->host_channels; ++i) ··· 80 90 81 91 hr->hprt0 = readl(hsotg->regs + HPRT0); 82 92 hr->hfir = readl(hsotg->regs + HFIR); 93 + hr->valid = true; 83 94 84 95 return 0; 85 96 } ··· 100 109 dev_dbg(hsotg->dev, "%s\n", __func__); 101 110 102 111 /* Restore host regs */ 103 - hr = hsotg->hr_backup; 104 - if (!hr) { 112 + hr = &hsotg->hr_backup; 113 + if (!hr->valid) { 105 114 dev_err(hsotg->dev, "%s: no host registers to restore\n", 106 115 __func__); 107 116 return -EINVAL; 108 117 } 118 + hr->valid = false; 109 119 110 120 writel(hr->hcfg, hsotg->regs + HCFG); 111 121 writel(hr->haintmsk, hsotg->regs + HAINTMSK); ··· 144 152 dev_dbg(hsotg->dev, "%s\n", __func__); 145 153 146 154 /* Backup dev regs */ 147 - dr = hsotg->dr_backup; 148 - if (!dr) { 149 - dr = devm_kzalloc(hsotg->dev, sizeof(*dr), GFP_KERNEL); 150 - if (!dr) { 151 - dev_err(hsotg->dev, "%s: can't allocate device regs\n", 152 - __func__); 153 - return -ENOMEM; 154 - } 155 - 156 - hsotg->dr_backup = dr; 157 - } 155 + dr = &hsotg->dr_backup; 158 156 159 157 dr->dcfg = readl(hsotg->regs + DCFG); 160 158 dr->dctl = readl(hsotg->regs + DCTL); ··· 177 195 dr->doeptsiz[i] = readl(hsotg->regs + DOEPTSIZ(i)); 178 196 dr->doepdma[i] = readl(hsotg->regs + DOEPDMA(i)); 179 197 } 180 - 198 + dr->valid = true; 181 199 return 0; 182 200 } 183 201 ··· 197 215 dev_dbg(hsotg->dev, "%s\n", __func__); 198 216 199 217 /* Restore dev regs */ 200 - dr = hsotg->dr_backup; 201 - if (!dr) { 218 + dr = &hsotg->dr_backup; 219 + if (!dr->valid) { 202 220 dev_err(hsotg->dev, "%s: no device registers to restore\n", 203 221 __func__); 204 222 return -EINVAL; 205 223 } 224 + dr->valid = false; 206 225 207 226 writel(dr->dcfg, hsotg->regs + DCFG); 208 227 writel(dr->dctl, hsotg->regs + DCTL); ··· 251 268 int i; 252 269 253 270 /* Backup global regs */ 254 - gr = hsotg->gr_backup; 255 - if (!gr) { 256 - gr = devm_kzalloc(hsotg->dev, sizeof(*gr), GFP_KERNEL); 257 - if (!gr) { 258 - dev_err(hsotg->dev, "%s: can't allocate global regs\n", 259 - __func__); 260 - return -ENOMEM; 261 - } 262 - 263 - hsotg->gr_backup = gr; 264 - } 271 + gr = &hsotg->gr_backup; 265 272 266 273 gr->gotgctl = readl(hsotg->regs + GOTGCTL); 267 274 gr->gintmsk = readl(hsotg->regs + GINTMSK); ··· 264 291 for (i = 0; i < MAX_EPS_CHANNELS; i++) 265 292 gr->dtxfsiz[i] = readl(hsotg->regs + DPTXFSIZN(i)); 266 293 294 + gr->valid = true; 267 295 return 0; 268 296 } 269 297 ··· 283 309 dev_dbg(hsotg->dev, "%s\n", __func__); 284 310 285 311 /* Restore global regs */ 286 - gr = hsotg->gr_backup; 287 - if (!gr) { 312 + gr = &hsotg->gr_backup; 313 + if (!gr->valid) { 288 314 dev_err(hsotg->dev, "%s: no global registers to restore\n", 289 315 __func__); 290 316 return -EINVAL; 291 317 } 318 + gr->valid = false; 292 319 293 320 writel(0xffffffff, hsotg->regs + GINTSTS); 294 321 writel(gr->gotgctl, hsotg->regs + GOTGCTL);
+6 -3
drivers/usb/dwc2/core.h
··· 492 492 u32 gdfifocfg; 493 493 u32 dtxfsiz[MAX_EPS_CHANNELS]; 494 494 u32 gpwrdn; 495 + bool valid; 495 496 }; 496 497 497 498 /** ··· 522 521 u32 doepctl[MAX_EPS_CHANNELS]; 523 522 u32 doeptsiz[MAX_EPS_CHANNELS]; 524 523 u32 doepdma[MAX_EPS_CHANNELS]; 524 + bool valid; 525 525 }; 526 526 527 527 /** ··· 540 538 u32 hcintmsk[MAX_EPS_CHANNELS]; 541 539 u32 hprt0; 542 540 u32 hfir; 541 + bool valid; 543 542 }; 544 543 545 544 /** ··· 708 705 struct work_struct wf_otg; 709 706 struct timer_list wkp_timer; 710 707 enum dwc2_lx_state lx_state; 711 - struct dwc2_gregs_backup *gr_backup; 712 - struct dwc2_dregs_backup *dr_backup; 713 - struct dwc2_hregs_backup *hr_backup; 708 + struct dwc2_gregs_backup gr_backup; 709 + struct dwc2_dregs_backup dr_backup; 710 + struct dwc2_hregs_backup hr_backup; 714 711 715 712 struct dentry *debug_root; 716 713 struct debugfs_regset32 *regset;
+43 -14
drivers/usb/dwc2/hcd.c
··· 359 359 360 360 /* Caller must hold driver lock */ 361 361 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 362 - struct dwc2_hcd_urb *urb, void **ep_handle, 363 - gfp_t mem_flags) 362 + struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 363 + struct dwc2_qtd *qtd) 364 364 { 365 - struct dwc2_qtd *qtd; 366 365 u32 intr_mask; 367 366 int retval; 368 367 int dev_speed; ··· 385 386 return -ENODEV; 386 387 } 387 388 388 - qtd = kzalloc(sizeof(*qtd), mem_flags); 389 389 if (!qtd) 390 - return -ENOMEM; 390 + return -EINVAL; 391 391 392 392 dwc2_hcd_qtd_init(qtd, urb); 393 - retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, 394 - mem_flags); 393 + retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 395 394 if (retval) { 396 395 dev_err(hsotg->dev, 397 396 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 398 397 retval); 399 - kfree(qtd); 400 398 return retval; 401 399 } 402 400 ··· 2441 2445 u32 tflags = 0; 2442 2446 void *buf; 2443 2447 unsigned long flags; 2448 + struct dwc2_qh *qh; 2449 + bool qh_allocated = false; 2450 + struct dwc2_qtd *qtd; 2444 2451 2445 2452 if (dbg_urb(urb)) { 2446 2453 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); ··· 2522 2523 urb->iso_frame_desc[i].length); 2523 2524 2524 2525 urb->hcpriv = dwc2_urb; 2526 + qh = (struct dwc2_qh *) ep->hcpriv; 2527 + /* Create QH for the endpoint if it doesn't exist */ 2528 + if (!qh) { 2529 + qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 2530 + if (!qh) { 2531 + retval = -ENOMEM; 2532 + goto fail0; 2533 + } 2534 + ep->hcpriv = qh; 2535 + qh_allocated = true; 2536 + } 2537 + 2538 + qtd = kzalloc(sizeof(*qtd), mem_flags); 2539 + if (!qtd) { 2540 + retval = -ENOMEM; 2541 + goto fail1; 2542 + } 2525 2543 2526 2544 spin_lock_irqsave(&hsotg->lock, flags); 2527 2545 retval = usb_hcd_link_urb_to_ep(hcd, urb); 2528 2546 if (retval) 2529 - goto fail1; 2530 - 2531 - retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags); 2532 - if (retval) 2533 2547 goto fail2; 2548 + 2549 + retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 2550 + if (retval) 2551 + goto fail3; 2534 2552 2535 2553 if (alloc_bandwidth) { 2536 2554 dwc2_allocate_bus_bandwidth(hcd, ··· 2559 2543 2560 2544 return 0; 2561 2545 2562 - fail2: 2546 + fail3: 2563 2547 dwc2_urb->priv = NULL; 2564 2548 usb_hcd_unlink_urb_from_ep(hcd, urb); 2565 - fail1: 2549 + fail2: 2566 2550 spin_unlock_irqrestore(&hsotg->lock, flags); 2567 2551 urb->hcpriv = NULL; 2552 + kfree(qtd); 2553 + fail1: 2554 + if (qh_allocated) { 2555 + struct dwc2_qtd *qtd2, *qtd2_tmp; 2556 + 2557 + ep->hcpriv = NULL; 2558 + dwc2_hcd_qh_unlink(hsotg, qh); 2559 + /* Free each QTD in the QH's QTD list */ 2560 + list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 2561 + qtd_list_entry) 2562 + dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 2563 + dwc2_hcd_qh_free(hsotg, qh); 2564 + } 2568 2565 fail0: 2569 2566 kfree(dwc2_urb); 2570 2567
+4 -1
drivers/usb/dwc2/hcd.h
··· 463 463 /* Schedule Queue Functions */ 464 464 /* Implemented in hcd_queue.c */ 465 465 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg); 466 + extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 467 + struct dwc2_hcd_urb *urb, 468 + gfp_t mem_flags); 466 469 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 467 470 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 468 471 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); ··· 474 471 475 472 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 476 473 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 477 - struct dwc2_qh **qh, gfp_t mem_flags); 474 + struct dwc2_qh *qh); 478 475 479 476 /* Unlinks and frees a QTD */ 480 477 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
+12 -37
drivers/usb/dwc2/hcd_queue.c
··· 191 191 * 192 192 * Return: Pointer to the newly allocated QH, or NULL on error 193 193 */ 194 - static struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 194 + struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 195 195 struct dwc2_hcd_urb *urb, 196 196 gfp_t mem_flags) 197 197 { ··· 767 767 * 768 768 * @hsotg: The DWC HCD structure 769 769 * @qtd: The QTD to add 770 - * @qh: Out parameter to return queue head 771 - * @atomic_alloc: Flag to do atomic alloc if needed 770 + * @qh: Queue head to add qtd to 772 771 * 773 772 * Return: 0 if successful, negative error code otherwise 774 773 * 775 - * Finds the correct QH to place the QTD into. If it does not find a QH, it 776 - * will create a new QH. If the QH to which the QTD is added is not currently 777 - * scheduled, it is placed into the proper schedule based on its EP type. 774 + * If the QH to which the QTD is added is not currently scheduled, it is placed 775 + * into the proper schedule based on its EP type. 778 776 */ 779 777 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 780 - struct dwc2_qh **qh, gfp_t mem_flags) 778 + struct dwc2_qh *qh) 781 779 { 782 - struct dwc2_hcd_urb *urb = qtd->urb; 783 - int allocated = 0; 784 780 int retval; 785 781 786 - /* 787 - * Get the QH which holds the QTD-list to insert to. Create QH if it 788 - * doesn't exist. 789 - */ 790 - if (*qh == NULL) { 791 - *qh = dwc2_hcd_qh_create(hsotg, urb, mem_flags); 792 - if (*qh == NULL) 793 - return -ENOMEM; 794 - allocated = 1; 782 + if (unlikely(!qh)) { 783 + dev_err(hsotg->dev, "%s: Invalid QH\n", __func__); 784 + retval = -EINVAL; 785 + goto fail; 795 786 } 796 787 797 - retval = dwc2_hcd_qh_add(hsotg, *qh); 788 + retval = dwc2_hcd_qh_add(hsotg, qh); 798 789 if (retval) 799 790 goto fail; 800 791 801 - qtd->qh = *qh; 802 - list_add_tail(&qtd->qtd_list_entry, &(*qh)->qtd_list); 792 + qtd->qh = qh; 793 + list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); 803 794 804 795 return 0; 805 - 806 796 fail: 807 - if (allocated) { 808 - struct dwc2_qtd *qtd2, *qtd2_tmp; 809 - struct dwc2_qh *qh_tmp = *qh; 810 - 811 - *qh = NULL; 812 - dwc2_hcd_qh_unlink(hsotg, qh_tmp); 813 - 814 - /* Free each QTD in the QH's QTD list */ 815 - list_for_each_entry_safe(qtd2, qtd2_tmp, &qh_tmp->qtd_list, 816 - qtd_list_entry) 817 - dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh_tmp); 818 - 819 - dwc2_hcd_qh_free(hsotg, qh_tmp); 820 - } 821 - 822 797 return retval; 823 798 }
+4 -2
drivers/usb/dwc3/core.c
··· 446 446 /* Select the HS PHY interface */ 447 447 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 448 448 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 449 - if (!strncmp(dwc->hsphy_interface, "utmi", 4)) { 449 + if (dwc->hsphy_interface && 450 + !strncmp(dwc->hsphy_interface, "utmi", 4)) { 450 451 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 451 452 break; 452 - } else if (!strncmp(dwc->hsphy_interface, "ulpi", 4)) { 453 + } else if (dwc->hsphy_interface && 454 + !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 453 455 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 454 456 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 455 457 } else {
+7 -4
drivers/usb/gadget/composite.c
··· 1758 1758 * take such requests too, if that's ever needed: to work 1759 1759 * in config 0, etc. 1760 1760 */ 1761 - list_for_each_entry(f, &cdev->config->functions, list) 1762 - if (f->req_match && f->req_match(f, ctrl)) 1763 - goto try_fun_setup; 1764 - f = NULL; 1761 + if (cdev->config) { 1762 + list_for_each_entry(f, &cdev->config->functions, list) 1763 + if (f->req_match && f->req_match(f, ctrl)) 1764 + goto try_fun_setup; 1765 + f = NULL; 1766 + } 1767 + 1765 1768 switch (ctrl->bRequestType & USB_RECIP_MASK) { 1766 1769 case USB_RECIP_INTERFACE: 1767 1770 if (!cdev->config || intf >= MAX_CONFIG_INTERFACES)
+4 -2
drivers/usb/gadget/function/f_fs.c
··· 924 924 925 925 kiocb->private = p; 926 926 927 - kiocb_set_cancel_fn(kiocb, ffs_aio_cancel); 927 + if (p->aio) 928 + kiocb_set_cancel_fn(kiocb, ffs_aio_cancel); 928 929 929 930 res = ffs_epfile_io(kiocb->ki_filp, p); 930 931 if (res == -EIOCBQUEUED) ··· 969 968 970 969 kiocb->private = p; 971 970 972 - kiocb_set_cancel_fn(kiocb, ffs_aio_cancel); 971 + if (p->aio) 972 + kiocb_set_cancel_fn(kiocb, ffs_aio_cancel); 973 973 974 974 res = ffs_epfile_io(kiocb->ki_filp, p); 975 975 if (res == -EIOCBQUEUED)
+13 -3
drivers/usb/gadget/function/f_mass_storage.c
··· 2786 2786 return -EINVAL; 2787 2787 } 2788 2788 2789 - curlun = kcalloc(nluns, sizeof(*curlun), GFP_KERNEL); 2789 + curlun = kcalloc(FSG_MAX_LUNS, sizeof(*curlun), GFP_KERNEL); 2790 2790 if (unlikely(!curlun)) 2791 2791 return -ENOMEM; 2792 2792 ··· 2795 2795 2796 2796 common->luns = curlun; 2797 2797 common->nluns = nluns; 2798 - 2799 - pr_info("Number of LUNs=%d\n", common->nluns); 2800 2798 2801 2799 return 0; 2802 2800 } ··· 3561 3563 struct fsg_opts *opts = fsg_opts_from_func_inst(fi); 3562 3564 struct fsg_common *common = opts->common; 3563 3565 struct fsg_dev *fsg; 3566 + unsigned nluns, i; 3564 3567 3565 3568 fsg = kzalloc(sizeof(*fsg), GFP_KERNEL); 3566 3569 if (unlikely(!fsg)) 3567 3570 return ERR_PTR(-ENOMEM); 3568 3571 3569 3572 mutex_lock(&opts->lock); 3573 + if (!opts->refcnt) { 3574 + for (nluns = i = 0; i < FSG_MAX_LUNS; ++i) 3575 + if (common->luns[i]) 3576 + nluns = i + 1; 3577 + if (!nluns) 3578 + pr_warn("No LUNS defined, continuing anyway\n"); 3579 + else 3580 + common->nluns = nluns; 3581 + pr_info("Number of LUNs=%u\n", common->nluns); 3582 + } 3570 3583 opts->refcnt++; 3571 3584 mutex_unlock(&opts->lock); 3585 + 3572 3586 fsg->function.name = FSG_DRIVER_DESC; 3573 3587 fsg->function.bind = fsg_bind; 3574 3588 fsg->function.unbind = fsg_unbind;
+1 -3
drivers/usb/gadget/function/f_midi.c
··· 1145 1145 if (opts->id && !midi->id) { 1146 1146 status = -ENOMEM; 1147 1147 mutex_unlock(&opts->lock); 1148 - goto kstrdup_fail; 1148 + goto setup_fail; 1149 1149 } 1150 1150 midi->in_ports = opts->in_ports; 1151 1151 midi->out_ports = opts->out_ports; ··· 1164 1164 1165 1165 return &midi->func; 1166 1166 1167 - kstrdup_fail: 1168 - f_midi_unregister_card(midi); 1169 1167 setup_fail: 1170 1168 for (--i; i >= 0; i--) 1171 1169 kfree(midi->in_port[i]);
+1 -2
drivers/usb/gadget/udc/fotg210-udc.c
··· 1171 1171 udc_name, fotg210); 1172 1172 if (ret < 0) { 1173 1173 pr_err("request_irq error (%d)\n", ret); 1174 - goto err_irq; 1174 + goto err_req; 1175 1175 } 1176 1176 1177 1177 ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget); ··· 1183 1183 return 0; 1184 1184 1185 1185 err_add_udc: 1186 - err_irq: 1187 1186 free_irq(ires->start, fotg210); 1188 1187 1189 1188 err_req:
+1 -3
drivers/usb/musb/musb_virthub.c
··· 275 275 #ifdef CONFIG_USB_MUSB_HOST 276 276 return 1; 277 277 #else 278 - if (musb->port_mode == MUSB_PORT_MODE_HOST) 279 - return 1; 280 - return musb->g.dev.driver != NULL; 278 + return musb->port_mode == MUSB_PORT_MODE_HOST; 281 279 #endif 282 280 } 283 281
+3
drivers/usb/phy/phy-mxs-usb.c
··· 217 217 { 218 218 unsigned int vbus_value; 219 219 220 + if (!mxs_phy->regmap_anatop) 221 + return false; 222 + 220 223 if (mxs_phy->port_id == 0) 221 224 regmap_read(mxs_phy->regmap_anatop, 222 225 ANADIG_USB1_VBUS_DET_STAT,
+1
drivers/usb/serial/cp210x.c
··· 187 187 { USB_DEVICE(0x1FB9, 0x0602) }, /* Lake Shore Model 648 Magnet Power Supply */ 188 188 { USB_DEVICE(0x1FB9, 0x0700) }, /* Lake Shore Model 737 VSM Controller */ 189 189 { USB_DEVICE(0x1FB9, 0x0701) }, /* Lake Shore Model 776 Hall Matrix */ 190 + { USB_DEVICE(0x2626, 0xEA60) }, /* Aruba Networks 7xxx USB Serial Console */ 190 191 { USB_DEVICE(0x3195, 0xF190) }, /* Link Instruments MSO-19 */ 191 192 { USB_DEVICE(0x3195, 0xF280) }, /* Link Instruments MSO-28 */ 192 193 { USB_DEVICE(0x3195, 0xF281) }, /* Link Instruments MSO-28 */
+138 -115
drivers/usb/serial/mos7720.c
··· 121 121 static const unsigned int dummy; /* for clarity in register access fns */ 122 122 123 123 enum mos_regs { 124 - THR, /* serial port regs */ 125 - RHR, 126 - IER, 127 - FCR, 128 - ISR, 129 - LCR, 130 - MCR, 131 - LSR, 132 - MSR, 133 - SPR, 134 - DLL, 135 - DLM, 136 - DPR, /* parallel port regs */ 137 - DSR, 138 - DCR, 139 - ECR, 140 - SP1_REG, /* device control regs */ 141 - SP2_REG, /* serial port 2 (7720 only) */ 142 - PP_REG, 143 - SP_CONTROL_REG, 124 + MOS7720_THR, /* serial port regs */ 125 + MOS7720_RHR, 126 + MOS7720_IER, 127 + MOS7720_FCR, 128 + MOS7720_ISR, 129 + MOS7720_LCR, 130 + MOS7720_MCR, 131 + MOS7720_LSR, 132 + MOS7720_MSR, 133 + MOS7720_SPR, 134 + MOS7720_DLL, 135 + MOS7720_DLM, 136 + MOS7720_DPR, /* parallel port regs */ 137 + MOS7720_DSR, 138 + MOS7720_DCR, 139 + MOS7720_ECR, 140 + MOS7720_SP1_REG, /* device control regs */ 141 + MOS7720_SP2_REG, /* serial port 2 (7720 only) */ 142 + MOS7720_PP_REG, 143 + MOS7720_SP_CONTROL_REG, 144 144 }; 145 145 146 146 /* ··· 150 150 static inline __u16 get_reg_index(enum mos_regs reg) 151 151 { 152 152 static const __u16 mos7715_index_lookup_table[] = { 153 - 0x00, /* THR */ 154 - 0x00, /* RHR */ 155 - 0x01, /* IER */ 156 - 0x02, /* FCR */ 157 - 0x02, /* ISR */ 158 - 0x03, /* LCR */ 159 - 0x04, /* MCR */ 160 - 0x05, /* LSR */ 161 - 0x06, /* MSR */ 162 - 0x07, /* SPR */ 163 - 0x00, /* DLL */ 164 - 0x01, /* DLM */ 165 - 0x00, /* DPR */ 166 - 0x01, /* DSR */ 167 - 0x02, /* DCR */ 168 - 0x0a, /* ECR */ 169 - 0x01, /* SP1_REG */ 170 - 0x02, /* SP2_REG (7720 only) */ 171 - 0x04, /* PP_REG (7715 only) */ 172 - 0x08, /* SP_CONTROL_REG */ 153 + 0x00, /* MOS7720_THR */ 154 + 0x00, /* MOS7720_RHR */ 155 + 0x01, /* MOS7720_IER */ 156 + 0x02, /* MOS7720_FCR */ 157 + 0x02, /* MOS7720_ISR */ 158 + 0x03, /* MOS7720_LCR */ 159 + 0x04, /* MOS7720_MCR */ 160 + 0x05, /* MOS7720_LSR */ 161 + 0x06, /* MOS7720_MSR */ 162 + 0x07, /* MOS7720_SPR */ 163 + 0x00, /* MOS7720_DLL */ 164 + 0x01, /* MOS7720_DLM */ 165 + 0x00, /* MOS7720_DPR */ 166 + 0x01, /* MOS7720_DSR */ 167 + 0x02, /* MOS7720_DCR */ 168 + 0x0a, /* MOS7720_ECR */ 169 + 0x01, /* MOS7720_SP1_REG */ 170 + 0x02, /* MOS7720_SP2_REG (7720 only) */ 171 + 0x04, /* MOS7720_PP_REG (7715 only) */ 172 + 0x08, /* MOS7720_SP_CONTROL_REG */ 173 173 }; 174 174 return mos7715_index_lookup_table[reg]; 175 175 } ··· 181 181 static inline __u16 get_reg_value(enum mos_regs reg, 182 182 unsigned int serial_portnum) 183 183 { 184 - if (reg >= SP1_REG) /* control reg */ 184 + if (reg >= MOS7720_SP1_REG) /* control reg */ 185 185 return 0x0000; 186 186 187 - else if (reg >= DPR) /* parallel port reg (7715 only) */ 187 + else if (reg >= MOS7720_DPR) /* parallel port reg (7715 only) */ 188 188 return 0x0100; 189 189 190 190 else /* serial port reg */ ··· 252 252 enum mos7715_pp_modes mode) 253 253 { 254 254 mos_parport->shadowECR = mode; 255 - write_mos_reg(mos_parport->serial, dummy, ECR, mos_parport->shadowECR); 255 + write_mos_reg(mos_parport->serial, dummy, MOS7720_ECR, 256 + mos_parport->shadowECR); 256 257 return 0; 257 258 } 258 259 ··· 487 486 if (parport_prologue(pp) < 0) 488 487 return; 489 488 mos7715_change_mode(mos_parport, SPP); 490 - write_mos_reg(mos_parport->serial, dummy, DPR, (__u8)d); 489 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DPR, (__u8)d); 491 490 parport_epilogue(pp); 492 491 } 493 492 ··· 498 497 499 498 if (parport_prologue(pp) < 0) 500 499 return 0; 501 - read_mos_reg(mos_parport->serial, dummy, DPR, &d); 500 + read_mos_reg(mos_parport->serial, dummy, MOS7720_DPR, &d); 502 501 parport_epilogue(pp); 503 502 return d; 504 503 } ··· 511 510 if (parport_prologue(pp) < 0) 512 511 return; 513 512 data = ((__u8)d & 0x0f) | (mos_parport->shadowDCR & 0xf0); 514 - write_mos_reg(mos_parport->serial, dummy, DCR, data); 513 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, data); 515 514 mos_parport->shadowDCR = data; 516 515 parport_epilogue(pp); 517 516 } ··· 544 543 if (parport_prologue(pp) < 0) 545 544 return 0; 546 545 mos_parport->shadowDCR = (mos_parport->shadowDCR & (~mask)) ^ val; 547 - write_mos_reg(mos_parport->serial, dummy, DCR, mos_parport->shadowDCR); 546 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, 547 + mos_parport->shadowDCR); 548 548 dcr = mos_parport->shadowDCR & 0x0f; 549 549 parport_epilogue(pp); 550 550 return dcr; ··· 583 581 return; 584 582 mos7715_change_mode(mos_parport, PS2); 585 583 mos_parport->shadowDCR &= ~0x20; 586 - write_mos_reg(mos_parport->serial, dummy, DCR, mos_parport->shadowDCR); 584 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, 585 + mos_parport->shadowDCR); 587 586 parport_epilogue(pp); 588 587 } 589 588 ··· 596 593 return; 597 594 mos7715_change_mode(mos_parport, PS2); 598 595 mos_parport->shadowDCR |= 0x20; 599 - write_mos_reg(mos_parport->serial, dummy, DCR, mos_parport->shadowDCR); 596 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, 597 + mos_parport->shadowDCR); 600 598 parport_epilogue(pp); 601 599 } 602 600 ··· 637 633 spin_unlock(&release_lock); 638 634 return; 639 635 } 640 - write_parport_reg_nonblock(mos_parport, DCR, mos_parport->shadowDCR); 641 - write_parport_reg_nonblock(mos_parport, ECR, mos_parport->shadowECR); 636 + write_parport_reg_nonblock(mos_parport, MOS7720_DCR, 637 + mos_parport->shadowDCR); 638 + write_parport_reg_nonblock(mos_parport, MOS7720_ECR, 639 + mos_parport->shadowECR); 642 640 spin_unlock(&release_lock); 643 641 } 644 642 ··· 720 714 init_completion(&mos_parport->syncmsg_compl); 721 715 722 716 /* cycle parallel port reset bit */ 723 - write_mos_reg(mos_parport->serial, dummy, PP_REG, (__u8)0x80); 724 - write_mos_reg(mos_parport->serial, dummy, PP_REG, (__u8)0x00); 717 + write_mos_reg(mos_parport->serial, dummy, MOS7720_PP_REG, (__u8)0x80); 718 + write_mos_reg(mos_parport->serial, dummy, MOS7720_PP_REG, (__u8)0x00); 725 719 726 720 /* initialize device registers */ 727 721 mos_parport->shadowDCR = DCR_INIT_VAL; 728 - write_mos_reg(mos_parport->serial, dummy, DCR, mos_parport->shadowDCR); 722 + write_mos_reg(mos_parport->serial, dummy, MOS7720_DCR, 723 + mos_parport->shadowDCR); 729 724 mos_parport->shadowECR = ECR_INIT_VAL; 730 - write_mos_reg(mos_parport->serial, dummy, ECR, mos_parport->shadowECR); 725 + write_mos_reg(mos_parport->serial, dummy, MOS7720_ECR, 726 + mos_parport->shadowECR); 731 727 732 728 /* register with parport core */ 733 729 mos_parport->pp = parport_register_port(0, PARPORT_IRQ_NONE, ··· 1041 1033 /* Initialize MCS7720 -- Write Init values to corresponding Registers 1042 1034 * 1043 1035 * Register Index 1044 - * 0 : THR/RHR 1045 - * 1 : IER 1046 - * 2 : FCR 1047 - * 3 : LCR 1048 - * 4 : MCR 1049 - * 5 : LSR 1050 - * 6 : MSR 1051 - * 7 : SPR 1036 + * 0 : MOS7720_THR/MOS7720_RHR 1037 + * 1 : MOS7720_IER 1038 + * 2 : MOS7720_FCR 1039 + * 3 : MOS7720_LCR 1040 + * 4 : MOS7720_MCR 1041 + * 5 : MOS7720_LSR 1042 + * 6 : MOS7720_MSR 1043 + * 7 : MOS7720_SPR 1052 1044 * 1053 1045 * 0x08 : SP1/2 Control Reg 1054 1046 */ 1055 1047 port_number = port->port_number; 1056 - read_mos_reg(serial, port_number, LSR, &data); 1048 + read_mos_reg(serial, port_number, MOS7720_LSR, &data); 1057 1049 1058 1050 dev_dbg(&port->dev, "SS::%p LSR:%x\n", mos7720_port, data); 1059 1051 1060 - write_mos_reg(serial, dummy, SP1_REG, 0x02); 1061 - write_mos_reg(serial, dummy, SP2_REG, 0x02); 1052 + write_mos_reg(serial, dummy, MOS7720_SP1_REG, 0x02); 1053 + write_mos_reg(serial, dummy, MOS7720_SP2_REG, 0x02); 1062 1054 1063 - write_mos_reg(serial, port_number, IER, 0x00); 1064 - write_mos_reg(serial, port_number, FCR, 0x00); 1055 + write_mos_reg(serial, port_number, MOS7720_IER, 0x00); 1056 + write_mos_reg(serial, port_number, MOS7720_FCR, 0x00); 1065 1057 1066 - write_mos_reg(serial, port_number, FCR, 0xcf); 1058 + write_mos_reg(serial, port_number, MOS7720_FCR, 0xcf); 1067 1059 mos7720_port->shadowLCR = 0x03; 1068 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1060 + write_mos_reg(serial, port_number, MOS7720_LCR, 1061 + mos7720_port->shadowLCR); 1069 1062 mos7720_port->shadowMCR = 0x0b; 1070 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1063 + write_mos_reg(serial, port_number, MOS7720_MCR, 1064 + mos7720_port->shadowMCR); 1071 1065 1072 - write_mos_reg(serial, port_number, SP_CONTROL_REG, 0x00); 1073 - read_mos_reg(serial, dummy, SP_CONTROL_REG, &data); 1066 + write_mos_reg(serial, port_number, MOS7720_SP_CONTROL_REG, 0x00); 1067 + read_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, &data); 1074 1068 data = data | (port->port_number + 1); 1075 - write_mos_reg(serial, dummy, SP_CONTROL_REG, data); 1069 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, data); 1076 1070 mos7720_port->shadowLCR = 0x83; 1077 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1078 - write_mos_reg(serial, port_number, THR, 0x0c); 1079 - write_mos_reg(serial, port_number, IER, 0x00); 1071 + write_mos_reg(serial, port_number, MOS7720_LCR, 1072 + mos7720_port->shadowLCR); 1073 + write_mos_reg(serial, port_number, MOS7720_THR, 0x0c); 1074 + write_mos_reg(serial, port_number, MOS7720_IER, 0x00); 1080 1075 mos7720_port->shadowLCR = 0x03; 1081 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1082 - write_mos_reg(serial, port_number, IER, 0x0c); 1076 + write_mos_reg(serial, port_number, MOS7720_LCR, 1077 + mos7720_port->shadowLCR); 1078 + write_mos_reg(serial, port_number, MOS7720_IER, 0x0c); 1083 1079 1084 1080 response = usb_submit_urb(port->read_urb, GFP_KERNEL); 1085 1081 if (response) ··· 1156 1144 usb_kill_urb(port->write_urb); 1157 1145 usb_kill_urb(port->read_urb); 1158 1146 1159 - write_mos_reg(serial, port->port_number, MCR, 0x00); 1160 - write_mos_reg(serial, port->port_number, IER, 0x00); 1147 + write_mos_reg(serial, port->port_number, MOS7720_MCR, 0x00); 1148 + write_mos_reg(serial, port->port_number, MOS7720_IER, 0x00); 1161 1149 1162 1150 mos7720_port->open = 0; 1163 1151 } ··· 1181 1169 data = mos7720_port->shadowLCR & ~UART_LCR_SBC; 1182 1170 1183 1171 mos7720_port->shadowLCR = data; 1184 - write_mos_reg(serial, port->port_number, LCR, mos7720_port->shadowLCR); 1172 + write_mos_reg(serial, port->port_number, MOS7720_LCR, 1173 + mos7720_port->shadowLCR); 1185 1174 } 1186 1175 1187 1176 /* ··· 1310 1297 /* if we are implementing RTS/CTS, toggle that line */ 1311 1298 if (tty->termios.c_cflag & CRTSCTS) { 1312 1299 mos7720_port->shadowMCR &= ~UART_MCR_RTS; 1313 - write_mos_reg(port->serial, port->port_number, MCR, 1300 + write_mos_reg(port->serial, port->port_number, MOS7720_MCR, 1314 1301 mos7720_port->shadowMCR); 1315 1302 } 1316 1303 } ··· 1340 1327 /* if we are implementing RTS/CTS, toggle that line */ 1341 1328 if (tty->termios.c_cflag & CRTSCTS) { 1342 1329 mos7720_port->shadowMCR |= UART_MCR_RTS; 1343 - write_mos_reg(port->serial, port->port_number, MCR, 1330 + write_mos_reg(port->serial, port->port_number, MOS7720_MCR, 1344 1331 mos7720_port->shadowMCR); 1345 1332 } 1346 1333 } ··· 1365 1352 dev_dbg(&port->dev, "Sending Setting Commands ..........\n"); 1366 1353 port_number = port->port_number; 1367 1354 1368 - write_mos_reg(serial, port_number, IER, 0x00); 1369 - write_mos_reg(serial, port_number, FCR, 0x00); 1370 - write_mos_reg(serial, port_number, FCR, 0xcf); 1355 + write_mos_reg(serial, port_number, MOS7720_IER, 0x00); 1356 + write_mos_reg(serial, port_number, MOS7720_FCR, 0x00); 1357 + write_mos_reg(serial, port_number, MOS7720_FCR, 0xcf); 1371 1358 mos7720_port->shadowMCR = 0x0b; 1372 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1373 - write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x00); 1359 + write_mos_reg(serial, port_number, MOS7720_MCR, 1360 + mos7720_port->shadowMCR); 1361 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, 0x00); 1374 1362 1375 1363 /*********************************************** 1376 1364 * Set for higher rates * 1377 1365 ***********************************************/ 1378 1366 /* writing baud rate verbatum into uart clock field clearly not right */ 1379 1367 if (port_number == 0) 1380 - sp_reg = SP1_REG; 1368 + sp_reg = MOS7720_SP1_REG; 1381 1369 else 1382 - sp_reg = SP2_REG; 1370 + sp_reg = MOS7720_SP2_REG; 1383 1371 write_mos_reg(serial, dummy, sp_reg, baud * 0x10); 1384 - write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x03); 1372 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, 0x03); 1385 1373 mos7720_port->shadowMCR = 0x2b; 1386 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1374 + write_mos_reg(serial, port_number, MOS7720_MCR, 1375 + mos7720_port->shadowMCR); 1387 1376 1388 1377 /*********************************************** 1389 1378 * Set DLL/DLM 1390 1379 ***********************************************/ 1391 1380 mos7720_port->shadowLCR = mos7720_port->shadowLCR | UART_LCR_DLAB; 1392 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1393 - write_mos_reg(serial, port_number, DLL, 0x01); 1394 - write_mos_reg(serial, port_number, DLM, 0x00); 1381 + write_mos_reg(serial, port_number, MOS7720_LCR, 1382 + mos7720_port->shadowLCR); 1383 + write_mos_reg(serial, port_number, MOS7720_DLL, 0x01); 1384 + write_mos_reg(serial, port_number, MOS7720_DLM, 0x00); 1395 1385 mos7720_port->shadowLCR = mos7720_port->shadowLCR & ~UART_LCR_DLAB; 1396 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1386 + write_mos_reg(serial, port_number, MOS7720_LCR, 1387 + mos7720_port->shadowLCR); 1397 1388 1398 1389 return 0; 1399 1390 } ··· 1505 1488 1506 1489 /* Enable access to divisor latch */ 1507 1490 mos7720_port->shadowLCR = mos7720_port->shadowLCR | UART_LCR_DLAB; 1508 - write_mos_reg(serial, number, LCR, mos7720_port->shadowLCR); 1491 + write_mos_reg(serial, number, MOS7720_LCR, mos7720_port->shadowLCR); 1509 1492 1510 1493 /* Write the divisor */ 1511 - write_mos_reg(serial, number, DLL, (__u8)(divisor & 0xff)); 1512 - write_mos_reg(serial, number, DLM, (__u8)((divisor & 0xff00) >> 8)); 1494 + write_mos_reg(serial, number, MOS7720_DLL, (__u8)(divisor & 0xff)); 1495 + write_mos_reg(serial, number, MOS7720_DLM, 1496 + (__u8)((divisor & 0xff00) >> 8)); 1513 1497 1514 1498 /* Disable access to divisor latch */ 1515 1499 mos7720_port->shadowLCR = mos7720_port->shadowLCR & ~UART_LCR_DLAB; 1516 - write_mos_reg(serial, number, LCR, mos7720_port->shadowLCR); 1500 + write_mos_reg(serial, number, MOS7720_LCR, mos7720_port->shadowLCR); 1517 1501 1518 1502 return status; 1519 1503 } ··· 1618 1600 1619 1601 1620 1602 /* Disable Interrupts */ 1621 - write_mos_reg(serial, port_number, IER, 0x00); 1622 - write_mos_reg(serial, port_number, FCR, 0x00); 1623 - write_mos_reg(serial, port_number, FCR, 0xcf); 1603 + write_mos_reg(serial, port_number, MOS7720_IER, 0x00); 1604 + write_mos_reg(serial, port_number, MOS7720_FCR, 0x00); 1605 + write_mos_reg(serial, port_number, MOS7720_FCR, 0xcf); 1624 1606 1625 1607 /* Send the updated LCR value to the mos7720 */ 1626 - write_mos_reg(serial, port_number, LCR, mos7720_port->shadowLCR); 1608 + write_mos_reg(serial, port_number, MOS7720_LCR, 1609 + mos7720_port->shadowLCR); 1627 1610 mos7720_port->shadowMCR = 0x0b; 1628 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1611 + write_mos_reg(serial, port_number, MOS7720_MCR, 1612 + mos7720_port->shadowMCR); 1629 1613 1630 1614 /* set up the MCR register and send it to the mos7720 */ 1631 1615 mos7720_port->shadowMCR = UART_MCR_OUT2; ··· 1639 1619 /* To set hardware flow control to the specified * 1640 1620 * serial port, in SP1/2_CONTROL_REG */ 1641 1621 if (port_number) 1642 - write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x01); 1622 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, 1623 + 0x01); 1643 1624 else 1644 - write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x02); 1625 + write_mos_reg(serial, dummy, MOS7720_SP_CONTROL_REG, 1626 + 0x02); 1645 1627 1646 1628 } else 1647 1629 mos7720_port->shadowMCR &= ~(UART_MCR_XONANY); 1648 1630 1649 - write_mos_reg(serial, port_number, MCR, mos7720_port->shadowMCR); 1631 + write_mos_reg(serial, port_number, MOS7720_MCR, 1632 + mos7720_port->shadowMCR); 1650 1633 1651 1634 /* Determine divisor based on baud rate */ 1652 1635 baud = tty_get_baud_rate(tty); ··· 1662 1639 if (baud >= 230400) { 1663 1640 set_higher_rates(mos7720_port, baud); 1664 1641 /* Enable Interrupts */ 1665 - write_mos_reg(serial, port_number, IER, 0x0c); 1642 + write_mos_reg(serial, port_number, MOS7720_IER, 0x0c); 1666 1643 return; 1667 1644 } 1668 1645 ··· 1673 1650 if (cflag & CBAUD) 1674 1651 tty_encode_baud_rate(tty, baud, baud); 1675 1652 /* Enable Interrupts */ 1676 - write_mos_reg(serial, port_number, IER, 0x0c); 1653 + write_mos_reg(serial, port_number, MOS7720_IER, 0x0c); 1677 1654 1678 1655 if (port->read_urb->status != -EINPROGRESS) { 1679 1656 status = usb_submit_urb(port->read_urb, GFP_KERNEL); ··· 1748 1725 1749 1726 count = mos7720_chars_in_buffer(tty); 1750 1727 if (count == 0) { 1751 - read_mos_reg(port->serial, port_number, LSR, &data); 1728 + read_mos_reg(port->serial, port_number, MOS7720_LSR, &data); 1752 1729 if ((data & (UART_LSR_TEMT | UART_LSR_THRE)) 1753 1730 == (UART_LSR_TEMT | UART_LSR_THRE)) { 1754 1731 dev_dbg(&port->dev, "%s -- Empty\n", __func__); ··· 1805 1782 mcr &= ~UART_MCR_LOOP; 1806 1783 1807 1784 mos7720_port->shadowMCR = mcr; 1808 - write_mos_reg(port->serial, port->port_number, MCR, 1785 + write_mos_reg(port->serial, port->port_number, MOS7720_MCR, 1809 1786 mos7720_port->shadowMCR); 1810 1787 1811 1788 return 0; ··· 1850 1827 } 1851 1828 1852 1829 mos7720_port->shadowMCR = mcr; 1853 - write_mos_reg(port->serial, port->port_number, MCR, 1830 + write_mos_reg(port->serial, port->port_number, MOS7720_MCR, 1854 1831 mos7720_port->shadowMCR); 1855 1832 1856 1833 return 0; ··· 1965 1942 } 1966 1943 #endif 1967 1944 /* LSR For Port 1 */ 1968 - read_mos_reg(serial, 0, LSR, &data); 1945 + read_mos_reg(serial, 0, MOS7720_LSR, &data); 1969 1946 dev_dbg(&dev->dev, "LSR:%x\n", data); 1970 1947 1971 1948 return 0;
+1
drivers/usb/serial/option.c
··· 1765 1765 { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x7d03, 0xff, 0x00, 0x00) }, 1766 1766 { USB_DEVICE_AND_INTERFACE_INFO(0x07d1, 0x3e01, 0xff, 0xff, 0xff) }, /* D-Link DWM-152/C1 */ 1767 1767 { USB_DEVICE_AND_INTERFACE_INFO(0x07d1, 0x3e02, 0xff, 0xff, 0xff) }, /* D-Link DWM-156/C1 */ 1768 + { USB_DEVICE_INTERFACE_CLASS(0x2020, 0x4000, 0xff) }, /* OLICARD300 - MT6225 */ 1768 1769 { USB_DEVICE(INOVIA_VENDOR_ID, INOVIA_SEW858) }, 1769 1770 { USB_DEVICE(VIATELECOM_VENDOR_ID, VIATELECOM_PRODUCT_CDS7) }, 1770 1771 { } /* Terminating entry */
+1
drivers/usb/serial/usb-serial.c
··· 1306 1306 tty_unregister_driver(usb_serial_tty_driver); 1307 1307 put_tty_driver(usb_serial_tty_driver); 1308 1308 bus_unregister(&usb_serial_bus_type); 1309 + idr_destroy(&serial_minors); 1309 1310 } 1310 1311 1311 1312