Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2024-01-05' of git://anongit.freedesktop.org/drm/drm
Pull more drm fixes from Dave Airlie:
"The amdgpu ones are fairly normal, the one that is a bit large is a
fix for a newly introduced IP in 6.7 so unlikely to cause regressions.
The nouveau ones are mostly memory leaks and debugging cleanups from
the GSP (new nvidia firmware) enablement. There are some GSP changes
to the message passing code and a subsequent fix for eDP panel turn
on, that means my laptop can turn on the panel in GSP mode. These are
fairly low chance of disrupting things since GSP is new in 6.7. The
final not all in GSP fix is a deadlock seen with i915/nouveau when GSP
is used where the the fence and irq paths have locking inversions,
I've pushed some irq enablement out to a workqueue, and this has seen
some fairly decent testing.
amdgpu:
- DP MST fix
- SMU 13.0.6 fixes
- fix displays on macbooks using vega12
- fix VSC and colorimetry on DP/eDP
nouveau:
- fix deadlock between fence signalling and irq paths
- fix GSP memory leaks
- fix GSP leftover debug
- hide some GSP callback messages
- fix GSP display disable path
- fix GSP ACPI interaction
- handle errors in ctrl messages
- use errors info to fix DP link training"
* tag 'drm-fixes-2024-01-05' of git://anongit.freedesktop.org/drm/drm:
drm/nouveau/dp: Honor GSP link training retry timeouts
nouveau: push event block/allowing out of the fence context
nouveau/gsp: always free the alloc messages on r535
nouveau/gsp: don't free ctrl messages on errors
nouveau/gsp: convert gsp errors to generic errors
drm/nouveau/gsp: Fix ACPI MXDM/MXDS method invocations
nouveau/gsp: free userd allocation.
nouveau/gsp: free acpi object after use
nouveau: fix disp disabling with GSP
nouveau/gsp: drop some acpi related debug
nouveau/gsp: add three notifier callbacks that we see in normal operation (v2)
drm/amd/pm: Use gpu_metrics_v1_5 for SMUv13.0.6
drm/amd/pm: Add gpu_metrics_v1_5
drm/amd/pm: Add mem_busy_percent for GCv9.4.3 apu
drm/amd/display: Fix sending VSC (+ colorimetry) packets for DP/eDP displays without PSR
drm/amdgpu: skip gpu_info fw loading on navi12
drm/amd/display: add nv12 bounding box
drm/amd/pm: Update metric table for jpeg/vcn data
drm/amd/pm: Use separate metric table for APU
drm/amd/display: pbn_div need be updated for hotplug event
+605
-198
+2
-9
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+2
-9
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
2188
2188
2189
2189
adev->firmware.gpu_info_fw = NULL;
2190
2190
2191
-
if (adev->mman.discovery_bin) {
2192
-
/*
2193
-
* FIXME: The bounding box is still needed by Navi12, so
2194
-
* temporarily read it from gpu_info firmware. Should be dropped
2195
-
* when DAL no longer needs it.
2196
-
*/
2197
-
if (adev->asic_type != CHIP_NAVI12)
2198
-
return 0;
2199
-
}
2191
+
if (adev->mman.discovery_bin)
2192
+
return 0;
2200
2193
2201
2194
switch (adev->asic_type) {
2202
2195
default:
+6
-5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+6
-5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
6170
6170
6171
6171
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6172
6172
mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6173
-
6174
-
if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6173
+
else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
6174
+
stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
6175
+
stream->signal == SIGNAL_TYPE_EDP) {
6175
6176
//
6176
6177
// should decide stream support vsc sdp colorimetry capability
6177
6178
// before building vsc info packet
···
6188
6187
if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6189
6188
tf = TRANSFER_FUNC_GAMMA_22;
6190
6189
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6191
-
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6192
6190
6191
+
if (stream->link->psr_settings.psr_feature_enabled)
6192
+
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6193
6193
}
6194
6194
finish:
6195
6195
dc_sink_release(sink);
···
6916
6914
if (IS_ERR(mst_state))
6917
6915
return PTR_ERR(mst_state);
6918
6916
6919
-
if (!mst_state->pbn_div)
6920
-
mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6917
+
mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6921
6918
6922
6919
if (!state->duplicated) {
6923
6920
int max_bpc = conn_state->max_requested_bpc;
+109
-1
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+109
-1
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
···
440
440
.use_urgent_burst_bw = 0
441
441
};
442
442
443
-
struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
443
+
struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = {
444
+
.clock_limits = {
445
+
{
446
+
.state = 0,
447
+
.dcfclk_mhz = 560.0,
448
+
.fabricclk_mhz = 560.0,
449
+
.dispclk_mhz = 513.0,
450
+
.dppclk_mhz = 513.0,
451
+
.phyclk_mhz = 540.0,
452
+
.socclk_mhz = 560.0,
453
+
.dscclk_mhz = 171.0,
454
+
.dram_speed_mts = 1069.0,
455
+
},
456
+
{
457
+
.state = 1,
458
+
.dcfclk_mhz = 694.0,
459
+
.fabricclk_mhz = 694.0,
460
+
.dispclk_mhz = 642.0,
461
+
.dppclk_mhz = 642.0,
462
+
.phyclk_mhz = 600.0,
463
+
.socclk_mhz = 694.0,
464
+
.dscclk_mhz = 214.0,
465
+
.dram_speed_mts = 1324.0,
466
+
},
467
+
{
468
+
.state = 2,
469
+
.dcfclk_mhz = 875.0,
470
+
.fabricclk_mhz = 875.0,
471
+
.dispclk_mhz = 734.0,
472
+
.dppclk_mhz = 734.0,
473
+
.phyclk_mhz = 810.0,
474
+
.socclk_mhz = 875.0,
475
+
.dscclk_mhz = 245.0,
476
+
.dram_speed_mts = 1670.0,
477
+
},
478
+
{
479
+
.state = 3,
480
+
.dcfclk_mhz = 1000.0,
481
+
.fabricclk_mhz = 1000.0,
482
+
.dispclk_mhz = 1100.0,
483
+
.dppclk_mhz = 1100.0,
484
+
.phyclk_mhz = 810.0,
485
+
.socclk_mhz = 1000.0,
486
+
.dscclk_mhz = 367.0,
487
+
.dram_speed_mts = 2000.0,
488
+
},
489
+
{
490
+
.state = 4,
491
+
.dcfclk_mhz = 1200.0,
492
+
.fabricclk_mhz = 1200.0,
493
+
.dispclk_mhz = 1284.0,
494
+
.dppclk_mhz = 1284.0,
495
+
.phyclk_mhz = 810.0,
496
+
.socclk_mhz = 1200.0,
497
+
.dscclk_mhz = 428.0,
498
+
.dram_speed_mts = 2000.0,
499
+
},
500
+
{
501
+
.state = 5,
502
+
.dcfclk_mhz = 1200.0,
503
+
.fabricclk_mhz = 1200.0,
504
+
.dispclk_mhz = 1284.0,
505
+
.dppclk_mhz = 1284.0,
506
+
.phyclk_mhz = 810.0,
507
+
.socclk_mhz = 1200.0,
508
+
.dscclk_mhz = 428.0,
509
+
.dram_speed_mts = 2000.0,
510
+
},
511
+
},
512
+
513
+
.num_states = 5,
514
+
.sr_exit_time_us = 1.9,
515
+
.sr_enter_plus_exit_time_us = 4.4,
516
+
.urgent_latency_us = 3.0,
517
+
.urgent_latency_pixel_data_only_us = 4.0,
518
+
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
519
+
.urgent_latency_vm_data_only_us = 4.0,
520
+
.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
521
+
.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
522
+
.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
523
+
.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
524
+
.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
525
+
.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
526
+
.max_avg_sdp_bw_use_normal_percent = 40.0,
527
+
.max_avg_dram_bw_use_normal_percent = 40.0,
528
+
.writeback_latency_us = 12.0,
529
+
.ideal_dram_bw_after_urgent_percent = 40.0,
530
+
.max_request_size_bytes = 256,
531
+
.dram_channel_width_bytes = 16,
532
+
.fabric_datapath_to_dcn_data_return_bytes = 64,
533
+
.dcn_downspread_percent = 0.5,
534
+
.downspread_percent = 0.5,
535
+
.dram_page_open_time_ns = 50.0,
536
+
.dram_rw_turnaround_time_ns = 17.5,
537
+
.dram_return_buffer_per_channel_bytes = 8192,
538
+
.round_trip_ping_latency_dcfclk_cycles = 131,
539
+
.urgent_out_of_order_return_per_channel_bytes = 4096,
540
+
.channel_interleave_bytes = 256,
541
+
.num_banks = 8,
542
+
.num_chans = 16,
543
+
.vmm_page_size_bytes = 4096,
544
+
.dram_clock_change_latency_us = 45.0,
545
+
.writeback_dram_clock_change_latency_us = 23.0,
546
+
.return_bus_width_bytes = 64,
547
+
.dispclk_dppclk_vco_speed_mhz = 3850,
548
+
.xfc_bus_transport_time_us = 20,
549
+
.xfc_xbuf_latency_tolerance_us = 50,
550
+
.use_urgent_burst_bw = 0,
551
+
};
444
552
445
553
struct _vcs_dpi_ip_params_st dcn2_1_ip = {
446
554
.odm_capable = 1,
+8
-5
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+8
-5
drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
···
147
147
}
148
148
149
149
/* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */
150
-
if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
150
+
if (stream->link->psr_settings.psr_feature_enabled) {
151
+
if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
152
+
vsc_packet_revision = vsc_packet_rev4;
153
+
else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
154
+
vsc_packet_revision = vsc_packet_rev2;
155
+
}
156
+
157
+
if (stream->link->replay_settings.config.replay_supported)
151
158
vsc_packet_revision = vsc_packet_rev4;
152
-
else if (stream->link->replay_settings.config.replay_supported)
153
-
vsc_packet_revision = vsc_packet_rev4;
154
-
else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
155
-
vsc_packet_revision = vsc_packet_rev2;
156
159
157
160
/* Update to revision 5 for extended colorimetry support */
158
161
if (stream->use_vsc_sdp_for_colorimetry)
+80
drivers/gpu/drm/amd/include/kgd_pp_interface.h
+80
drivers/gpu/drm/amd/include/kgd_pp_interface.h
···
318
318
#define MAX_GFX_CLKS 8
319
319
#define MAX_CLKS 4
320
320
#define NUM_VCN 4
321
+
#define NUM_JPEG_ENG 32
321
322
322
323
struct seq_file;
323
324
enum amd_pp_clock_type;
···
757
756
758
757
/* PCIE replay rollover accumulated count */
759
758
uint64_t pcie_replay_rover_count_acc;
759
+
760
+
/* XGMI accumulated data transfer size(KiloBytes) */
761
+
uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
762
+
uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
763
+
764
+
/* PMFW attached timestamp (10ns resolution) */
765
+
uint64_t firmware_timestamp;
766
+
767
+
/* Current clocks (Mhz) */
768
+
uint16_t current_gfxclk[MAX_GFX_CLKS];
769
+
uint16_t current_socclk[MAX_CLKS];
770
+
uint16_t current_vclk0[MAX_CLKS];
771
+
uint16_t current_dclk0[MAX_CLKS];
772
+
uint16_t current_uclk;
773
+
774
+
uint16_t padding;
775
+
};
776
+
777
+
struct gpu_metrics_v1_5 {
778
+
struct metrics_table_header common_header;
779
+
780
+
/* Temperature (Celsius) */
781
+
uint16_t temperature_hotspot;
782
+
uint16_t temperature_mem;
783
+
uint16_t temperature_vrsoc;
784
+
785
+
/* Power (Watts) */
786
+
uint16_t curr_socket_power;
787
+
788
+
/* Utilization (%) */
789
+
uint16_t average_gfx_activity;
790
+
uint16_t average_umc_activity; // memory controller
791
+
uint16_t vcn_activity[NUM_VCN];
792
+
uint16_t jpeg_activity[NUM_JPEG_ENG];
793
+
794
+
/* Energy (15.259uJ (2^-16) units) */
795
+
uint64_t energy_accumulator;
796
+
797
+
/* Driver attached timestamp (in ns) */
798
+
uint64_t system_clock_counter;
799
+
800
+
/* Throttle status */
801
+
uint32_t throttle_status;
802
+
803
+
/* Clock Lock Status. Each bit corresponds to clock instance */
804
+
uint32_t gfxclk_lock_status;
805
+
806
+
/* Link width (number of lanes) and speed (in 0.1 GT/s) */
807
+
uint16_t pcie_link_width;
808
+
uint16_t pcie_link_speed;
809
+
810
+
/* XGMI bus width and bitrate (in Gbps) */
811
+
uint16_t xgmi_link_width;
812
+
uint16_t xgmi_link_speed;
813
+
814
+
/* Utilization Accumulated (%) */
815
+
uint32_t gfx_activity_acc;
816
+
uint32_t mem_activity_acc;
817
+
818
+
/*PCIE accumulated bandwidth (GB/sec) */
819
+
uint64_t pcie_bandwidth_acc;
820
+
821
+
/*PCIE instantaneous bandwidth (GB/sec) */
822
+
uint64_t pcie_bandwidth_inst;
823
+
824
+
/* PCIE L0 to recovery state transition accumulated count */
825
+
uint64_t pcie_l0_to_recov_count_acc;
826
+
827
+
/* PCIE replay accumulated count */
828
+
uint64_t pcie_replay_count_acc;
829
+
830
+
/* PCIE replay rollover accumulated count */
831
+
uint64_t pcie_replay_rover_count_acc;
832
+
833
+
/* PCIE NAK sent accumulated count */
834
+
uint32_t pcie_nak_sent_count_acc;
835
+
836
+
/* PCIE NAK received accumulated count */
837
+
uint32_t pcie_nak_rcvd_count_acc;
760
838
761
839
/* XGMI accumulated data transfer size(KiloBytes) */
762
840
uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
+3
-1
drivers/gpu/drm/amd/pm/amdgpu_pm.c
+3
-1
drivers/gpu/drm/amd/pm/amdgpu_pm.c
···
2128
2128
if (amdgpu_dpm_is_overdrive_supported(adev))
2129
2129
*states = ATTR_STATE_SUPPORTED;
2130
2130
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2131
-
if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
2131
+
if ((adev->flags & AMD_IS_APU &&
2132
+
gc_ver != IP_VERSION(9, 4, 3)) ||
2133
+
gc_ver == IP_VERSION(9, 0, 1))
2132
2134
*states = ATTR_STATE_UNSUPPORTED;
2133
2135
} else if (DEVICE_ATTR_IS(pcie_bw)) {
2134
2136
/* PCIe Perf counters won't work on APU nodes */
+98
-2
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
+98
-2
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
···
123
123
VOLTAGE_GUARDBAND_COUNT
124
124
} GFX_GUARDBAND_e;
125
125
126
-
#define SMU_METRICS_TABLE_VERSION 0x9
126
+
#define SMU_METRICS_TABLE_VERSION 0xB
127
127
128
128
typedef struct __attribute__((packed, aligned(4))) {
129
129
uint32_t AccumulationCounter;
···
219
219
uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated
220
220
uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated
221
221
uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated
222
-
} MetricsTable_t;
222
+
223
+
// VCN/JPEG ACTIVITY
224
+
uint32_t VcnBusy[4];
225
+
uint32_t JpegBusy[32];
226
+
} MetricsTableX_t;
227
+
228
+
typedef struct __attribute__((packed, aligned(4))) {
229
+
uint32_t AccumulationCounter;
230
+
231
+
//TEMPERATURE
232
+
uint32_t MaxSocketTemperature;
233
+
uint32_t MaxVrTemperature;
234
+
uint32_t MaxHbmTemperature;
235
+
uint64_t MaxSocketTemperatureAcc;
236
+
uint64_t MaxVrTemperatureAcc;
237
+
uint64_t MaxHbmTemperatureAcc;
238
+
239
+
//POWER
240
+
uint32_t SocketPowerLimit;
241
+
uint32_t MaxSocketPowerLimit;
242
+
uint32_t SocketPower;
243
+
244
+
//ENERGY
245
+
uint64_t Timestamp;
246
+
uint64_t SocketEnergyAcc;
247
+
uint64_t CcdEnergyAcc;
248
+
uint64_t XcdEnergyAcc;
249
+
uint64_t AidEnergyAcc;
250
+
uint64_t HbmEnergyAcc;
251
+
252
+
//FREQUENCY
253
+
uint32_t CclkFrequencyLimit;
254
+
uint32_t GfxclkFrequencyLimit;
255
+
uint32_t FclkFrequency;
256
+
uint32_t UclkFrequency;
257
+
uint32_t SocclkFrequency[4];
258
+
uint32_t VclkFrequency[4];
259
+
uint32_t DclkFrequency[4];
260
+
uint32_t LclkFrequency[4];
261
+
uint64_t GfxclkFrequencyAcc[8];
262
+
uint64_t CclkFrequencyAcc[96];
263
+
264
+
//FREQUENCY RANGE
265
+
uint32_t MaxCclkFrequency;
266
+
uint32_t MinCclkFrequency;
267
+
uint32_t MaxGfxclkFrequency;
268
+
uint32_t MinGfxclkFrequency;
269
+
uint32_t FclkFrequencyTable[4];
270
+
uint32_t UclkFrequencyTable[4];
271
+
uint32_t SocclkFrequencyTable[4];
272
+
uint32_t VclkFrequencyTable[4];
273
+
uint32_t DclkFrequencyTable[4];
274
+
uint32_t LclkFrequencyTable[4];
275
+
uint32_t MaxLclkDpmRange;
276
+
uint32_t MinLclkDpmRange;
277
+
278
+
//XGMI
279
+
uint32_t XgmiWidth;
280
+
uint32_t XgmiBitrate;
281
+
uint64_t XgmiReadBandwidthAcc[8];
282
+
uint64_t XgmiWriteBandwidthAcc[8];
283
+
284
+
//ACTIVITY
285
+
uint32_t SocketC0Residency;
286
+
uint32_t SocketGfxBusy;
287
+
uint32_t DramBandwidthUtilization;
288
+
uint64_t SocketC0ResidencyAcc;
289
+
uint64_t SocketGfxBusyAcc;
290
+
uint64_t DramBandwidthAcc;
291
+
uint32_t MaxDramBandwidth;
292
+
uint64_t DramBandwidthUtilizationAcc;
293
+
uint64_t PcieBandwidthAcc[4];
294
+
295
+
//THROTTLERS
296
+
uint32_t ProchotResidencyAcc;
297
+
uint32_t PptResidencyAcc;
298
+
uint32_t SocketThmResidencyAcc;
299
+
uint32_t VrThmResidencyAcc;
300
+
uint32_t HbmThmResidencyAcc;
301
+
uint32_t GfxLockXCDMak;
302
+
303
+
// New Items at end to maintain driver compatibility
304
+
uint32_t GfxclkFrequency[8];
305
+
306
+
//PSNs
307
+
uint64_t PublicSerialNumber_AID[4];
308
+
uint64_t PublicSerialNumber_XCD[8];
309
+
uint64_t PublicSerialNumber_CCD[12];
310
+
311
+
//XGMI Data tranfser size
312
+
uint64_t XgmiReadDataSizeAcc[8];//in KByte
313
+
uint64_t XgmiWriteDataSizeAcc[8];//in KByte
314
+
315
+
// VCN/JPEG ACTIVITY
316
+
uint32_t VcnBusy[4];
317
+
uint32_t JpegBusy[32];
318
+
} MetricsTableA_t;
223
319
224
320
#define SMU_VF_METRICS_TABLE_VERSION 0x3
225
321
+91
-62
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+91
-62
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
···
245
245
#define SMUQ10_TO_UINT(x) ((x) >> 10)
246
246
#define SMUQ10_FRAC(x) ((x) & 0x3ff)
247
247
#define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
248
+
#define GET_METRIC_FIELD(field) ((adev->flags & AMD_IS_APU) ?\
249
+
(metrics_a->field) : (metrics_x->field))
248
250
249
251
struct smu_v13_0_6_dpm_map {
250
252
enum smu_clk_type clk_type;
···
329
327
SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
330
328
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
331
329
332
-
SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(MetricsTable_t),
330
+
SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
331
+
max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)),
333
332
PAGE_SIZE,
334
333
AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
335
334
···
338
335
PAGE_SIZE,
339
336
AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
340
337
341
-
smu_table->metrics_table = kzalloc(sizeof(MetricsTable_t), GFP_KERNEL);
338
+
smu_table->metrics_table = kzalloc(max(sizeof(MetricsTableX_t),
339
+
sizeof(MetricsTableA_t)), GFP_KERNEL);
342
340
if (!smu_table->metrics_table)
343
341
return -ENOMEM;
344
342
smu_table->metrics_time = 0;
345
343
346
-
smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_4);
344
+
smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_5);
347
345
smu_table->gpu_metrics_table =
348
346
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
349
347
if (!smu_table->gpu_metrics_table) {
···
435
431
static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
436
432
{
437
433
struct smu_table_context *smu_table = &smu->smu_table;
438
-
MetricsTable_t *metrics = (MetricsTable_t *)smu_table->metrics_table;
434
+
MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
435
+
MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
439
436
struct PPTable_t *pptable =
440
437
(struct PPTable_t *)smu_table->driver_pptable;
438
+
struct amdgpu_device *adev = smu->adev;
441
439
int ret, i, retry = 100;
442
440
443
441
/* Store one-time values in driver PPTable */
···
450
444
return ret;
451
445
452
446
/* Ensure that metrics have been updated */
453
-
if (metrics->AccumulationCounter)
447
+
if (GET_METRIC_FIELD(AccumulationCounter))
454
448
break;
455
449
456
450
usleep_range(1000, 1100);
···
460
454
return -ETIME;
461
455
462
456
pptable->MaxSocketPowerLimit =
463
-
SMUQ10_ROUND(metrics->MaxSocketPowerLimit);
457
+
SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit));
464
458
pptable->MaxGfxclkFrequency =
465
-
SMUQ10_ROUND(metrics->MaxGfxclkFrequency);
459
+
SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency));
466
460
pptable->MinGfxclkFrequency =
467
-
SMUQ10_ROUND(metrics->MinGfxclkFrequency);
461
+
SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency));
468
462
469
463
for (i = 0; i < 4; ++i) {
470
464
pptable->FclkFrequencyTable[i] =
471
-
SMUQ10_ROUND(metrics->FclkFrequencyTable[i]);
465
+
SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable)[i]);
472
466
pptable->UclkFrequencyTable[i] =
473
-
SMUQ10_ROUND(metrics->UclkFrequencyTable[i]);
467
+
SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable)[i]);
474
468
pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
475
-
metrics->SocclkFrequencyTable[i]);
469
+
GET_METRIC_FIELD(SocclkFrequencyTable)[i]);
476
470
pptable->VclkFrequencyTable[i] =
477
-
SMUQ10_ROUND(metrics->VclkFrequencyTable[i]);
471
+
SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable)[i]);
478
472
pptable->DclkFrequencyTable[i] =
479
-
SMUQ10_ROUND(metrics->DclkFrequencyTable[i]);
473
+
SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable)[i]);
480
474
pptable->LclkFrequencyTable[i] =
481
-
SMUQ10_ROUND(metrics->LclkFrequencyTable[i]);
475
+
SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable)[i]);
482
476
}
483
477
484
478
/* use AID0 serial number by default */
485
-
pptable->PublicSerialNumber_AID = metrics->PublicSerialNumber_AID[0];
479
+
pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID)[0];
486
480
487
481
pptable->Init = true;
488
482
}
···
784
778
uint32_t *value)
785
779
{
786
780
struct smu_table_context *smu_table = &smu->smu_table;
787
-
MetricsTable_t *metrics = (MetricsTable_t *)smu_table->metrics_table;
781
+
MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
782
+
MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
788
783
struct amdgpu_device *adev = smu->adev;
789
784
int ret = 0;
790
785
int xcc_id;
···
800
793
case METRICS_AVERAGE_GFXCLK:
801
794
if (smu->smc_fw_version >= 0x552F00) {
802
795
xcc_id = GET_INST(GC, 0);
803
-
*value = SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]);
796
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]);
804
797
} else {
805
798
*value = 0;
806
799
}
807
800
break;
808
801
case METRICS_CURR_SOCCLK:
809
802
case METRICS_AVERAGE_SOCCLK:
810
-
*value = SMUQ10_ROUND(metrics->SocclkFrequency[0]);
803
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[0]);
811
804
break;
812
805
case METRICS_CURR_UCLK:
813
806
case METRICS_AVERAGE_UCLK:
814
-
*value = SMUQ10_ROUND(metrics->UclkFrequency);
807
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency));
815
808
break;
816
809
case METRICS_CURR_VCLK:
817
-
*value = SMUQ10_ROUND(metrics->VclkFrequency[0]);
810
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[0]);
818
811
break;
819
812
case METRICS_CURR_DCLK:
820
-
*value = SMUQ10_ROUND(metrics->DclkFrequency[0]);
813
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[0]);
821
814
break;
822
815
case METRICS_CURR_FCLK:
823
-
*value = SMUQ10_ROUND(metrics->FclkFrequency);
816
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency));
824
817
break;
825
818
case METRICS_AVERAGE_GFXACTIVITY:
826
-
*value = SMUQ10_ROUND(metrics->SocketGfxBusy);
819
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy));
827
820
break;
828
821
case METRICS_AVERAGE_MEMACTIVITY:
829
-
*value = SMUQ10_ROUND(metrics->DramBandwidthUtilization);
822
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization));
830
823
break;
831
824
case METRICS_CURR_SOCKETPOWER:
832
-
*value = SMUQ10_ROUND(metrics->SocketPower) << 8;
825
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)) << 8;
833
826
break;
834
827
case METRICS_TEMPERATURE_HOTSPOT:
835
-
*value = SMUQ10_ROUND(metrics->MaxSocketTemperature) *
828
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)) *
836
829
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
837
830
break;
838
831
case METRICS_TEMPERATURE_MEM:
839
-
*value = SMUQ10_ROUND(metrics->MaxHbmTemperature) *
832
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)) *
840
833
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
841
834
break;
842
835
/* This is the max of all VRs and not just SOC VR.
843
836
* No need to define another data type for the same.
844
837
*/
845
838
case METRICS_TEMPERATURE_VRSOC:
846
-
*value = SMUQ10_ROUND(metrics->MaxVrTemperature) *
839
+
*value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)) *
847
840
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
848
841
break;
849
842
default:
···
2029
2022
static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
2030
2023
{
2031
2024
struct smu_table_context *smu_table = &smu->smu_table;
2032
-
struct gpu_metrics_v1_4 *gpu_metrics =
2033
-
(struct gpu_metrics_v1_4 *)smu_table->gpu_metrics_table;
2025
+
struct gpu_metrics_v1_5 *gpu_metrics =
2026
+
(struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table;
2034
2027
struct amdgpu_device *adev = smu->adev;
2035
-
int ret = 0, xcc_id, inst, i;
2036
-
MetricsTable_t *metrics;
2028
+
int ret = 0, xcc_id, inst, i, j;
2029
+
MetricsTableX_t *metrics_x;
2030
+
MetricsTableA_t *metrics_a;
2037
2031
u16 link_width_level;
2038
2032
2039
-
metrics = kzalloc(sizeof(MetricsTable_t), GFP_KERNEL);
2040
-
ret = smu_v13_0_6_get_metrics_table(smu, metrics, true);
2033
+
metrics_x = kzalloc(max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)), GFP_KERNEL);
2034
+
ret = smu_v13_0_6_get_metrics_table(smu, metrics_x, true);
2041
2035
if (ret) {
2042
-
kfree(metrics);
2036
+
kfree(metrics_x);
2043
2037
return ret;
2044
2038
}
2045
2039
2046
-
smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 4);
2040
+
metrics_a = (MetricsTableA_t *)metrics_x;
2041
+
2042
+
smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5);
2047
2043
2048
2044
gpu_metrics->temperature_hotspot =
2049
-
SMUQ10_ROUND(metrics->MaxSocketTemperature);
2045
+
SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature));
2050
2046
/* Individual HBM stack temperature is not reported */
2051
2047
gpu_metrics->temperature_mem =
2052
-
SMUQ10_ROUND(metrics->MaxHbmTemperature);
2048
+
SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature));
2053
2049
/* Reports max temperature of all voltage rails */
2054
2050
gpu_metrics->temperature_vrsoc =
2055
-
SMUQ10_ROUND(metrics->MaxVrTemperature);
2051
+
SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature));
2056
2052
2057
2053
gpu_metrics->average_gfx_activity =
2058
-
SMUQ10_ROUND(metrics->SocketGfxBusy);
2054
+
SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy));
2059
2055
gpu_metrics->average_umc_activity =
2060
-
SMUQ10_ROUND(metrics->DramBandwidthUtilization);
2056
+
SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization));
2061
2057
2062
2058
gpu_metrics->curr_socket_power =
2063
-
SMUQ10_ROUND(metrics->SocketPower);
2059
+
SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower));
2064
2060
/* Energy counter reported in 15.259uJ (2^-16) units */
2065
-
gpu_metrics->energy_accumulator = metrics->SocketEnergyAcc;
2061
+
gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc);
2066
2062
2067
2063
for (i = 0; i < MAX_GFX_CLKS; i++) {
2068
2064
xcc_id = GET_INST(GC, i);
2069
2065
if (xcc_id >= 0)
2070
2066
gpu_metrics->current_gfxclk[i] =
2071
-
SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]);
2067
+
SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]);
2072
2068
2073
2069
if (i < MAX_CLKS) {
2074
2070
gpu_metrics->current_socclk[i] =
2075
-
SMUQ10_ROUND(metrics->SocclkFrequency[i]);
2071
+
SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[i]);
2076
2072
inst = GET_INST(VCN, i);
2077
2073
if (inst >= 0) {
2078
2074
gpu_metrics->current_vclk0[i] =
2079
-
SMUQ10_ROUND(metrics->VclkFrequency[inst]);
2075
+
SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[inst]);
2080
2076
gpu_metrics->current_dclk0[i] =
2081
-
SMUQ10_ROUND(metrics->DclkFrequency[inst]);
2077
+
SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[inst]);
2082
2078
}
2083
2079
}
2084
2080
}
2085
2081
2086
-
gpu_metrics->current_uclk = SMUQ10_ROUND(metrics->UclkFrequency);
2082
+
gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency));
2087
2083
2088
2084
/* Throttle status is not reported through metrics now */
2089
2085
gpu_metrics->throttle_status = 0;
2090
2086
2091
2087
/* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
2092
-
gpu_metrics->gfxclk_lock_status = metrics->GfxLockXCDMak >> GET_INST(GC, 0);
2088
+
gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak) >> GET_INST(GC, 0);
2093
2089
2094
2090
if (!(adev->flags & AMD_IS_APU)) {
2095
2091
link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
···
2104
2094
gpu_metrics->pcie_link_speed =
2105
2095
smu_v13_0_6_get_current_pcie_link_speed(smu);
2106
2096
gpu_metrics->pcie_bandwidth_acc =
2107
-
SMUQ10_ROUND(metrics->PcieBandwidthAcc[0]);
2097
+
SMUQ10_ROUND(metrics_x->PcieBandwidthAcc[0]);
2108
2098
gpu_metrics->pcie_bandwidth_inst =
2109
-
SMUQ10_ROUND(metrics->PcieBandwidth[0]);
2099
+
SMUQ10_ROUND(metrics_x->PcieBandwidth[0]);
2110
2100
gpu_metrics->pcie_l0_to_recov_count_acc =
2111
-
metrics->PCIeL0ToRecoveryCountAcc;
2101
+
metrics_x->PCIeL0ToRecoveryCountAcc;
2112
2102
gpu_metrics->pcie_replay_count_acc =
2113
-
metrics->PCIenReplayAAcc;
2103
+
metrics_x->PCIenReplayAAcc;
2114
2104
gpu_metrics->pcie_replay_rover_count_acc =
2115
-
metrics->PCIenReplayARolloverCountAcc;
2105
+
metrics_x->PCIenReplayARolloverCountAcc;
2106
+
gpu_metrics->pcie_nak_sent_count_acc =
2107
+
metrics_x->PCIeNAKSentCountAcc;
2108
+
gpu_metrics->pcie_nak_rcvd_count_acc =
2109
+
metrics_x->PCIeNAKReceivedCountAcc;
2116
2110
}
2117
2111
2118
2112
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2119
2113
2120
2114
gpu_metrics->gfx_activity_acc =
2121
-
SMUQ10_ROUND(metrics->SocketGfxBusyAcc);
2115
+
SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc));
2122
2116
gpu_metrics->mem_activity_acc =
2123
-
SMUQ10_ROUND(metrics->DramBandwidthUtilizationAcc);
2117
+
SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc));
2124
2118
2125
2119
for (i = 0; i < NUM_XGMI_LINKS; i++) {
2126
2120
gpu_metrics->xgmi_read_data_acc[i] =
2127
-
SMUQ10_ROUND(metrics->XgmiReadDataSizeAcc[i]);
2121
+
SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc)[i]);
2128
2122
gpu_metrics->xgmi_write_data_acc[i] =
2129
-
SMUQ10_ROUND(metrics->XgmiWriteDataSizeAcc[i]);
2123
+
SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc)[i]);
2130
2124
}
2131
2125
2132
-
gpu_metrics->xgmi_link_width = SMUQ10_ROUND(metrics->XgmiWidth);
2133
-
gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(metrics->XgmiBitrate);
2126
+
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
2127
+
inst = GET_INST(JPEG, i);
2128
+
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
2129
+
gpu_metrics->jpeg_activity[(i * adev->jpeg.num_jpeg_rings) + j] =
2130
+
SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy)
2131
+
[(inst * adev->jpeg.num_jpeg_rings) + j]);
2132
+
}
2133
+
}
2134
2134
2135
-
gpu_metrics->firmware_timestamp = metrics->Timestamp;
2135
+
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2136
+
inst = GET_INST(VCN, i);
2137
+
gpu_metrics->vcn_activity[i] =
2138
+
SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy)[inst]);
2139
+
}
2140
+
2141
+
gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth));
2142
+
gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate));
2143
+
2144
+
gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp);
2136
2145
2137
2146
*table = (void *)gpu_metrics;
2138
-
kfree(metrics);
2147
+
kfree(metrics_x);
2139
2148
2140
2149
return sizeof(*gpu_metrics);
2141
2150
}
+3
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+3
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
···
989
989
case METRICS_VERSION(1, 4):
990
990
structure_size = sizeof(struct gpu_metrics_v1_4);
991
991
break;
992
+
case METRICS_VERSION(1, 5):
993
+
structure_size = sizeof(struct gpu_metrics_v1_5);
994
+
break;
992
995
case METRICS_VERSION(2, 0):
993
996
structure_size = sizeof(struct gpu_metrics_v2_0);
994
997
break;
+10
-7
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
+10
-7
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
···
187
187
void (*rpc_done)(struct nvkm_gsp *gsp, void *repv);
188
188
189
189
void *(*rm_ctrl_get)(struct nvkm_gsp_object *, u32 cmd, u32 argc);
190
-
void *(*rm_ctrl_push)(struct nvkm_gsp_object *, void *argv, u32 repc);
190
+
int (*rm_ctrl_push)(struct nvkm_gsp_object *, void **argv, u32 repc);
191
191
void (*rm_ctrl_done)(struct nvkm_gsp_object *, void *repv);
192
192
193
193
void *(*rm_alloc_get)(struct nvkm_gsp_object *, u32 oclass, u32 argc);
···
265
265
return object->client->gsp->rm->rm_ctrl_get(object, cmd, argc);
266
266
}
267
267
268
-
static inline void *
268
+
static inline int
269
269
nvkm_gsp_rm_ctrl_push(struct nvkm_gsp_object *object, void *argv, u32 repc)
270
270
{
271
271
return object->client->gsp->rm->rm_ctrl_push(object, argv, repc);
···
275
275
nvkm_gsp_rm_ctrl_rd(struct nvkm_gsp_object *object, u32 cmd, u32 repc)
276
276
{
277
277
void *argv = nvkm_gsp_rm_ctrl_get(object, cmd, repc);
278
+
int ret;
278
279
279
280
if (IS_ERR(argv))
280
281
return argv;
281
282
282
-
return nvkm_gsp_rm_ctrl_push(object, argv, repc);
283
+
ret = nvkm_gsp_rm_ctrl_push(object, &argv, repc);
284
+
if (ret)
285
+
return ERR_PTR(ret);
286
+
return argv;
283
287
}
284
288
285
289
static inline int
286
290
nvkm_gsp_rm_ctrl_wr(struct nvkm_gsp_object *object, void *argv)
287
291
{
288
-
void *repv = nvkm_gsp_rm_ctrl_push(object, argv, 0);
292
+
int ret = nvkm_gsp_rm_ctrl_push(object, &argv, 0);
289
293
290
-
if (IS_ERR(repv))
291
-
return PTR_ERR(repv);
292
-
294
+
if (ret)
295
+
return ret;
293
296
return 0;
294
297
}
295
298
+23
-5
drivers/gpu/drm/nouveau/nouveau_fence.c
+23
-5
drivers/gpu/drm/nouveau/nouveau_fence.c
···
62
62
if (test_bit(DMA_FENCE_FLAG_USER_BITS, &fence->base.flags)) {
63
63
struct nouveau_fence_chan *fctx = nouveau_fctx(fence);
64
64
65
-
if (!--fctx->notify_ref)
65
+
if (atomic_dec_and_test(&fctx->notify_ref))
66
66
drop = 1;
67
67
}
68
68
···
103
103
void
104
104
nouveau_fence_context_del(struct nouveau_fence_chan *fctx)
105
105
{
106
+
cancel_work_sync(&fctx->allow_block_work);
106
107
nouveau_fence_context_kill(fctx, 0);
107
108
nvif_event_dtor(&fctx->event);
108
109
fctx->dead = 1;
···
168
167
return ret;
169
168
}
170
169
170
+
static void
171
+
nouveau_fence_work_allow_block(struct work_struct *work)
172
+
{
173
+
struct nouveau_fence_chan *fctx = container_of(work, struct nouveau_fence_chan,
174
+
allow_block_work);
175
+
176
+
if (atomic_read(&fctx->notify_ref) == 0)
177
+
nvif_event_block(&fctx->event);
178
+
else
179
+
nvif_event_allow(&fctx->event);
180
+
}
181
+
171
182
void
172
183
nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_chan *fctx)
173
184
{
···
191
178
} args;
192
179
int ret;
193
180
181
+
INIT_WORK(&fctx->allow_block_work, nouveau_fence_work_allow_block);
194
182
INIT_LIST_HEAD(&fctx->flip);
195
183
INIT_LIST_HEAD(&fctx->pending);
196
184
spin_lock_init(&fctx->lock);
···
535
521
struct nouveau_fence *fence = from_fence(f);
536
522
struct nouveau_fence_chan *fctx = nouveau_fctx(fence);
537
523
bool ret;
524
+
bool do_work;
538
525
539
-
if (!fctx->notify_ref++)
540
-
nvif_event_allow(&fctx->event);
526
+
if (atomic_inc_return(&fctx->notify_ref) == 0)
527
+
do_work = true;
541
528
542
529
ret = nouveau_fence_no_signaling(f);
543
530
if (ret)
544
531
set_bit(DMA_FENCE_FLAG_USER_BITS, &fence->base.flags);
545
-
else if (!--fctx->notify_ref)
546
-
nvif_event_block(&fctx->event);
532
+
else if (atomic_dec_and_test(&fctx->notify_ref))
533
+
do_work = true;
534
+
535
+
if (do_work)
536
+
schedule_work(&fctx->allow_block_work);
547
537
548
538
return ret;
549
539
}
+4
-1
drivers/gpu/drm/nouveau/nouveau_fence.h
+4
-1
drivers/gpu/drm/nouveau/nouveau_fence.h
···
3
3
#define __NOUVEAU_FENCE_H__
4
4
5
5
#include <linux/dma-fence.h>
6
+
#include <linux/workqueue.h>
6
7
#include <nvif/event.h>
7
8
8
9
struct nouveau_drm;
···
46
45
char name[32];
47
46
48
47
struct nvif_event event;
49
-
int notify_ref, dead, killed;
48
+
struct work_struct allow_block_work;
49
+
atomic_t notify_ref;
50
+
int dead, killed;
50
51
};
51
52
52
53
struct nouveau_fence_priv {
+4
-2
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
+4
-2
drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c
···
209
209
nvkm_head_del(&head);
210
210
}
211
211
212
-
if (disp->func->dtor)
212
+
if (disp->func && disp->func->dtor)
213
213
disp->func->dtor(disp);
214
214
215
215
return data;
···
243
243
spin_lock_init(&disp->client.lock);
244
244
245
245
ret = nvkm_engine_ctor(&nvkm_disp, device, type, inst, true, &disp->engine);
246
-
if (ret)
246
+
if (ret) {
247
+
disp->func = NULL;
247
248
return ret;
249
+
}
248
250
249
251
if (func->super) {
250
252
disp->super.wq = create_singlethread_workqueue("nvkm-disp");
+107
-64
drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c
+107
-64
drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c
···
282
282
{
283
283
struct nvkm_disp *disp = sor->disp;
284
284
NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *ctrl;
285
-
int lvl;
285
+
int ret, lvl;
286
286
287
287
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom,
288
288
NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS,
···
292
292
293
293
ctrl->displayId = BIT(sor->asy.outp->index);
294
294
295
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
296
-
if (IS_ERR(ctrl))
297
-
return PTR_ERR(ctrl);
295
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
296
+
if (ret) {
297
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
298
+
return ret;
299
+
}
298
300
299
301
lvl = ctrl->brightness;
300
302
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
···
651
649
ctrl->subDeviceInstance = 0;
652
650
ctrl->displayId = BIT(id);
653
651
654
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
655
-
if (IS_ERR(ctrl))
656
-
return (void *)ctrl;
652
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
653
+
if (ret) {
654
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
655
+
return ERR_PTR(ret);
656
+
}
657
657
658
658
list_for_each_entry(conn, &disp->conns, head) {
659
659
if (conn->index == ctrl->data[0].index) {
···
690
686
struct nvkm_disp *disp = outp->disp;
691
687
struct nvkm_ior *ior;
692
688
NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS *ctrl;
693
-
int or;
689
+
int ret, or;
694
690
695
691
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom,
696
692
NV0073_CTRL_CMD_DFP_ASSIGN_SOR, sizeof(*ctrl));
···
703
699
if (hda)
704
700
ctrl->flags |= NVDEF(NV0073_CTRL, DFP_ASSIGN_SOR_FLAGS, AUDIO, OPTIMAL);
705
701
706
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
707
-
if (IS_ERR(ctrl))
708
-
return PTR_ERR(ctrl);
702
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
703
+
if (ret) {
704
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
705
+
return ret;
706
+
}
709
707
710
708
for (or = 0; or < ARRAY_SIZE(ctrl->sorAssignListWithTag); or++) {
711
709
if (ctrl->sorAssignListWithTag[or].displayMask & BIT(outp->index)) {
···
733
727
r535_disp_head_displayid(struct nvkm_disp *disp, int head, u32 *displayid)
734
728
{
735
729
NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS *ctrl;
730
+
int ret;
736
731
737
732
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom,
738
733
NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE, sizeof(*ctrl));
···
743
736
ctrl->subDeviceInstance = 0;
744
737
ctrl->head = head;
745
738
746
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
747
-
if (IS_ERR(ctrl))
748
-
return PTR_ERR(ctrl);
739
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
740
+
if (ret) {
741
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
742
+
return ret;
743
+
}
749
744
750
745
*displayid = ctrl->displayId;
751
746
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
···
781
772
ctrl->subDeviceInstance = 0;
782
773
ctrl->displayId = displayid;
783
774
784
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
785
-
if (IS_ERR(ctrl))
775
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
776
+
if (ret) {
777
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
786
778
return NULL;
779
+
}
787
780
788
781
id = ctrl->index;
789
782
proto = ctrl->protocol;
···
836
825
{
837
826
NV0073_CTRL_DFP_GET_INFO_PARAMS *ctrl;
838
827
struct nvkm_disp *disp = outp->disp;
828
+
int ret;
839
829
840
830
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom, NV0073_CTRL_CMD_DFP_GET_INFO, sizeof(*ctrl));
841
831
if (IS_ERR(ctrl))
···
844
832
845
833
ctrl->displayId = BIT(outp->index);
846
834
847
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
848
-
if (IS_ERR(ctrl))
849
-
return PTR_ERR(ctrl);
835
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
836
+
if (ret) {
837
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
838
+
return ret;
839
+
}
850
840
851
841
nvkm_debug(&disp->engine.subdev, "DFP %08x: flags:%08x flags2:%08x\n",
852
842
ctrl->displayId, ctrl->flags, ctrl->flags2);
···
872
858
ctrl->subDeviceInstance = 0;
873
859
ctrl->displayMask = BIT(outp->index);
874
860
875
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
876
-
if (IS_ERR(ctrl))
877
-
return PTR_ERR(ctrl);
861
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
862
+
if (ret) {
863
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
864
+
return ret;
865
+
}
878
866
879
867
if (ctrl->displayMask & BIT(outp->index)) {
880
868
ret = r535_outp_dfp_get_info(outp);
···
911
895
{
912
896
NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS *ctrl;
913
897
struct nvkm_disp *disp = outp->disp;
898
+
int ret;
914
899
915
900
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom,
916
901
NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID,
···
921
904
922
905
ctrl->subDeviceInstance = 0;
923
906
ctrl->displayId = BIT(outp->index);
924
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
925
-
if (IS_ERR(ctrl))
926
-
return PTR_ERR(ctrl);
907
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
908
+
if (ret) {
909
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
910
+
return ret;
911
+
}
927
912
928
913
*pid = ctrl->displayIdAssigned;
929
914
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
···
957
938
{
958
939
struct nvkm_disp *disp = outp->disp;
959
940
NV0073_CTRL_DP_CTRL_PARAMS *ctrl;
960
-
int ret;
941
+
int ret, retries;
942
+
u32 cmd, data;
961
943
962
-
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom, NV0073_CTRL_CMD_DP_CTRL, sizeof(*ctrl));
963
-
if (IS_ERR(ctrl))
964
-
return PTR_ERR(ctrl);
965
-
966
-
ctrl->subDeviceInstance = 0;
967
-
ctrl->displayId = BIT(outp->index);
968
-
ctrl->cmd = NVDEF(NV0073_CTRL, DP_CMD, SET_LANE_COUNT, TRUE) |
969
-
NVDEF(NV0073_CTRL, DP_CMD, SET_LINK_BW, TRUE) |
970
-
NVDEF(NV0073_CTRL, DP_CMD, TRAIN_PHY_REPEATER, YES);
971
-
ctrl->data = NVVAL(NV0073_CTRL, DP_DATA, SET_LANE_COUNT, link_nr) |
972
-
NVVAL(NV0073_CTRL, DP_DATA, SET_LINK_BW, link_bw) |
973
-
NVVAL(NV0073_CTRL, DP_DATA, TARGET, target);
944
+
cmd = NVDEF(NV0073_CTRL, DP_CMD, SET_LANE_COUNT, TRUE) |
945
+
NVDEF(NV0073_CTRL, DP_CMD, SET_LINK_BW, TRUE) |
946
+
NVDEF(NV0073_CTRL, DP_CMD, TRAIN_PHY_REPEATER, YES);
947
+
data = NVVAL(NV0073_CTRL, DP_DATA, SET_LANE_COUNT, link_nr) |
948
+
NVVAL(NV0073_CTRL, DP_DATA, SET_LINK_BW, link_bw) |
949
+
NVVAL(NV0073_CTRL, DP_DATA, TARGET, target);
974
950
975
951
if (mst)
976
-
ctrl->cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_FORMAT_MODE, MULTI_STREAM);
952
+
cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_FORMAT_MODE, MULTI_STREAM);
977
953
978
954
if (outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
979
-
ctrl->cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_ENHANCED_FRAMING, TRUE);
955
+
cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_ENHANCED_FRAMING, TRUE);
980
956
981
957
if (target == 0 &&
982
958
(outp->dp.dpcd[DPCD_RC02] & 0x20) &&
983
959
!(outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED))
984
-
ctrl->cmd |= NVDEF(NV0073_CTRL, DP_CMD, POST_LT_ADJ_REQ_GRANTED, YES);
960
+
cmd |= NVDEF(NV0073_CTRL, DP_CMD, POST_LT_ADJ_REQ_GRANTED, YES);
985
961
986
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
987
-
if (IS_ERR(ctrl))
988
-
return PTR_ERR(ctrl);
962
+
/* We should retry up to 3 times, but only if GSP asks politely */
963
+
for (retries = 0; retries < 3; ++retries) {
964
+
ctrl = nvkm_gsp_rm_ctrl_get(&disp->rm.objcom, NV0073_CTRL_CMD_DP_CTRL,
965
+
sizeof(*ctrl));
966
+
if (IS_ERR(ctrl))
967
+
return PTR_ERR(ctrl);
989
968
990
-
ret = ctrl->err ? -EIO : 0;
991
-
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
969
+
ctrl->subDeviceInstance = 0;
970
+
ctrl->displayId = BIT(outp->index);
971
+
ctrl->retryTimeMs = 0;
972
+
ctrl->cmd = cmd;
973
+
ctrl->data = data;
974
+
975
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
976
+
if (ret == -EAGAIN && ctrl->retryTimeMs) {
977
+
/*
978
+
* Device (likely an eDP panel) isn't ready yet, wait for the time specified
979
+
* by GSP before retrying again
980
+
*/
981
+
nvkm_debug(&disp->engine.subdev,
982
+
"Waiting %dms for GSP LT panel delay before retrying\n",
983
+
ctrl->retryTimeMs);
984
+
msleep(ctrl->retryTimeMs);
985
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
986
+
} else {
987
+
/* GSP didn't say to retry, or we were successful */
988
+
if (ctrl->err)
989
+
ret = -EIO;
990
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
991
+
break;
992
+
}
993
+
}
994
+
992
995
return ret;
993
996
}
994
997
···
1077
1036
ctrl->size = !ctrl->bAddrOnly ? (size - 1) : 0;
1078
1037
memcpy(ctrl->data, data, size);
1079
1038
1080
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
1081
-
if (IS_ERR(ctrl))
1039
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
1040
+
if (ret) {
1041
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
1082
1042
return PTR_ERR(ctrl);
1043
+
}
1083
1044
1084
1045
memcpy(data, ctrl->data, size);
1085
1046
*psize = ctrl->size;
···
1154
1111
ctrl->subDeviceInstance = 0;
1155
1112
ctrl->displayId = BIT(outp->index);
1156
1113
1157
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
1158
-
if (IS_ERR(ctrl))
1159
-
return PTR_ERR(ctrl);
1114
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
1115
+
if (ret) {
1116
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
1117
+
return ret;
1118
+
}
1160
1119
1120
+
ret = -E2BIG;
1161
1121
if (ctrl->bufferSize <= *psize) {
1162
1122
memcpy(data, ctrl->edidBuffer, ctrl->bufferSize);
1163
1123
*psize = ctrl->bufferSize;
···
1199
1153
ctrl->subDeviceInstance = 0;
1200
1154
ctrl->displayId = BIT(id);
1201
1155
1202
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
1203
-
if (IS_ERR(ctrl))
1204
-
return PTR_ERR(ctrl);
1156
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
1157
+
if (ret) {
1158
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
1159
+
return ret;
1160
+
}
1205
1161
1206
1162
switch (ctrl->type) {
1207
1163
case NV0073_CTRL_SPECIFIC_OR_TYPE_NONE:
···
1277
1229
1278
1230
ctrl->sorIndex = ~0;
1279
1231
1280
-
ctrl = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, ctrl, sizeof(*ctrl));
1281
-
if (IS_ERR(ctrl))
1282
-
return PTR_ERR(ctrl);
1232
+
ret = nvkm_gsp_rm_ctrl_push(&disp->rm.objcom, &ctrl, sizeof(*ctrl));
1233
+
if (ret) {
1234
+
nvkm_gsp_rm_ctrl_done(&disp->rm.objcom, ctrl);
1235
+
return ret;
1236
+
}
1283
1237
1284
1238
switch (NVVAL_GET(ctrl->maxLinkRate, NV0073_CTRL_CMD, DP_GET_CAPS, MAX_LINK_RATE)) {
1285
1239
case NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62:
···
1515
1465
bool nvhg = acpi_check_dsm(handle, &NVHG_DSM_GUID, NVHG_DSM_REV,
1516
1466
1ULL << 0x00000014);
1517
1467
1518
-
printk(KERN_ERR "bl: nbci:%d nvhg:%d\n", nbci, nvhg);
1519
-
1520
1468
if (nbci || nvhg) {
1521
1469
union acpi_object argv4 = {
1522
1470
.buffer.type = ACPI_TYPE_BUFFER,
···
1527
1479
if (!obj) {
1528
1480
acpi_handle_info(handle, "failed to evaluate _DSM\n");
1529
1481
} else {
1530
-
printk(KERN_ERR "bl: obj type %d\n", obj->type);
1531
-
printk(KERN_ERR "bl: obj len %d\n", obj->package.count);
1532
-
1533
1482
for (int i = 0; i < obj->package.count; i++) {
1534
1483
union acpi_object *elt = &obj->package.elements[i];
1535
1484
u32 size;
···
1536
1491
else
1537
1492
size = 4;
1538
1493
1539
-
printk(KERN_ERR "elt %03d: type %d size %d\n", i, elt->type, size);
1540
1494
memcpy(&ctrl->backLightData[ctrl->backLightDataSize], &elt->integer.value, size);
1541
1495
ctrl->backLightDataSize += size;
1542
1496
}
1543
1497
1544
-
printk(KERN_ERR "bl: data size %d\n", ctrl->backLightDataSize);
1545
1498
ctrl->status = 0;
1546
1499
ACPI_FREE(obj);
1547
1500
}
+1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c
+1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c
+56
-34
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
+56
-34
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
···
70
70
71
71
#define GSP_MSG_HDR_SIZE offsetof(struct r535_gsp_msg, data)
72
72
73
+
static int
74
+
r535_rpc_status_to_errno(uint32_t rpc_status)
75
+
{
76
+
switch (rpc_status) {
77
+
case 0x55: /* NV_ERR_NOT_READY */
78
+
case 0x66: /* NV_ERR_TIMEOUT_RETRY */
79
+
return -EAGAIN;
80
+
case 0x51: /* NV_ERR_NO_MEMORY */
81
+
return -ENOMEM;
82
+
default:
83
+
return -EINVAL;
84
+
}
85
+
}
86
+
73
87
static void *
74
88
r535_gsp_msgq_wait(struct nvkm_gsp *gsp, u32 repc, u32 *prepc, int *ptime)
75
89
{
···
312
298
struct nvkm_gsp_msgq_ntfy *ntfy = &gsp->msgq.ntfy[i];
313
299
314
300
if (ntfy->fn == msg->function) {
315
-
ntfy->func(ntfy->priv, ntfy->fn, msg->data, msg->length - sizeof(*msg));
301
+
if (ntfy->func)
302
+
ntfy->func(ntfy->priv, ntfy->fn, msg->data, msg->length - sizeof(*msg));
316
303
break;
317
304
}
318
305
}
···
598
583
return rpc;
599
584
600
585
if (rpc->status) {
601
-
nvkm_error(&gsp->subdev, "RM_ALLOC: 0x%x\n", rpc->status);
602
-
ret = ERR_PTR(-EINVAL);
586
+
ret = ERR_PTR(r535_rpc_status_to_errno(rpc->status));
587
+
if (PTR_ERR(ret) != -EAGAIN)
588
+
nvkm_error(&gsp->subdev, "RM_ALLOC: 0x%x\n", rpc->status);
603
589
} else {
604
590
ret = repc ? rpc->params : NULL;
605
591
}
606
592
607
-
if (IS_ERR_OR_NULL(ret))
608
-
nvkm_gsp_rpc_done(gsp, rpc);
593
+
nvkm_gsp_rpc_done(gsp, rpc);
609
594
610
595
return ret;
611
596
}
···
638
623
{
639
624
rpc_gsp_rm_control_v03_00 *rpc = container_of(repv, typeof(*rpc), params);
640
625
626
+
if (!repv)
627
+
return;
641
628
nvkm_gsp_rpc_done(object->client->gsp, rpc);
642
629
}
643
630
644
-
static void *
645
-
r535_gsp_rpc_rm_ctrl_push(struct nvkm_gsp_object *object, void *argv, u32 repc)
631
+
static int
632
+
r535_gsp_rpc_rm_ctrl_push(struct nvkm_gsp_object *object, void **argv, u32 repc)
646
633
{
647
-
rpc_gsp_rm_control_v03_00 *rpc = container_of(argv, typeof(*rpc), params);
634
+
rpc_gsp_rm_control_v03_00 *rpc = container_of((*argv), typeof(*rpc), params);
648
635
struct nvkm_gsp *gsp = object->client->gsp;
649
-
void *ret;
636
+
int ret = 0;
650
637
651
638
rpc = nvkm_gsp_rpc_push(gsp, rpc, true, repc);
652
-
if (IS_ERR_OR_NULL(rpc))
653
-
return rpc;
654
-
655
-
if (rpc->status) {
656
-
nvkm_error(&gsp->subdev, "cli:0x%08x obj:0x%08x ctrl cmd:0x%08x failed: 0x%08x\n",
657
-
object->client->object.handle, object->handle, rpc->cmd, rpc->status);
658
-
ret = ERR_PTR(-EINVAL);
659
-
} else {
660
-
ret = repc ? rpc->params : NULL;
639
+
if (IS_ERR_OR_NULL(rpc)) {
640
+
*argv = NULL;
641
+
return PTR_ERR(rpc);
661
642
}
662
643
663
-
if (IS_ERR_OR_NULL(ret))
644
+
if (rpc->status) {
645
+
ret = r535_rpc_status_to_errno(rpc->status);
646
+
if (ret != -EAGAIN)
647
+
nvkm_error(&gsp->subdev, "cli:0x%08x obj:0x%08x ctrl cmd:0x%08x failed: 0x%08x\n",
648
+
object->client->object.handle, object->handle, rpc->cmd, rpc->status);
649
+
}
650
+
651
+
if (repc)
652
+
*argv = rpc->params;
653
+
else
664
654
nvkm_gsp_rpc_done(gsp, rpc);
665
655
666
656
return ret;
···
863
843
if (IS_ERR(ctrl))
864
844
return PTR_ERR(ctrl);
865
845
866
-
ctrl = nvkm_gsp_rm_ctrl_push(&gsp->internal.device.subdevice, ctrl, sizeof(*ctrl));
867
-
if (WARN_ON(IS_ERR(ctrl)))
868
-
return PTR_ERR(ctrl);
846
+
ret = nvkm_gsp_rm_ctrl_push(&gsp->internal.device.subdevice, &ctrl, sizeof(*ctrl));
847
+
if (WARN_ON(ret)) {
848
+
nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, ctrl);
849
+
return ret;
850
+
}
869
851
870
852
for (unsigned i = 0; i < ctrl->tableLen; i++) {
871
853
enum nvkm_subdev_type type;
···
1121
1099
if (!obj)
1122
1100
return;
1123
1101
1124
-
printk(KERN_ERR "nvop: obj type %d\n", obj->type);
1125
-
printk(KERN_ERR "nvop: obj len %d\n", obj->buffer.length);
1126
-
1127
1102
if (WARN_ON(obj->type != ACPI_TYPE_BUFFER) ||
1128
1103
WARN_ON(obj->buffer.length != 4))
1129
1104
return;
1130
1105
1131
1106
caps->status = 0;
1132
1107
caps->optimusCaps = *(u32 *)obj->buffer.pointer;
1133
-
printk(KERN_ERR "nvop: caps %08x\n", caps->optimusCaps);
1134
1108
1135
1109
ACPI_FREE(obj);
1136
1110
···
1153
1135
if (!obj)
1154
1136
return;
1155
1137
1156
-
printk(KERN_ERR "jt: obj type %d\n", obj->type);
1157
-
printk(KERN_ERR "jt: obj len %d\n", obj->buffer.length);
1158
-
1159
1138
if (WARN_ON(obj->type != ACPI_TYPE_BUFFER) ||
1160
1139
WARN_ON(obj->buffer.length != 4))
1161
1140
return;
···
1161
1146
jt->jtCaps = *(u32 *)obj->buffer.pointer;
1162
1147
jt->jtRevId = (jt->jtCaps & 0xfff00000) >> 20;
1163
1148
jt->bSBIOSCaps = 0;
1164
-
printk(KERN_ERR "jt: caps %08x rev:%04x\n", jt->jtCaps, jt->jtRevId);
1165
1149
1166
1150
ACPI_FREE(obj);
1167
1151
···
1171
1157
r535_gsp_acpi_mux_id(acpi_handle handle, u32 id, MUX_METHOD_DATA_ELEMENT *mode,
1172
1158
MUX_METHOD_DATA_ELEMENT *part)
1173
1159
{
1160
+
union acpi_object mux_arg = { ACPI_TYPE_INTEGER };
1161
+
struct acpi_object_list input = { 1, &mux_arg };
1174
1162
acpi_handle iter = NULL, handle_mux = NULL;
1175
1163
acpi_status status;
1176
1164
unsigned long long value;
···
1195
1179
if (!handle_mux)
1196
1180
return;
1197
1181
1198
-
status = acpi_evaluate_integer(handle_mux, "MXDM", NULL, &value);
1182
+
/* I -think- 0 means "acquire" according to nvidia's driver source */
1183
+
input.pointer->integer.type = ACPI_TYPE_INTEGER;
1184
+
input.pointer->integer.value = 0;
1185
+
1186
+
status = acpi_evaluate_integer(handle_mux, "MXDM", &input, &value);
1199
1187
if (ACPI_SUCCESS(status)) {
1200
1188
mode->acpiId = id;
1201
1189
mode->mode = value;
1202
1190
mode->status = 0;
1203
1191
}
1204
1192
1205
-
status = acpi_evaluate_integer(handle_mux, "MXDS", NULL, &value);
1193
+
status = acpi_evaluate_integer(handle_mux, "MXDS", &input, &value);
1206
1194
if (ACPI_SUCCESS(status)) {
1207
1195
part->acpiId = id;
1208
1196
part->mode = value;
···
1252
1232
dod->acpiIdListLen += sizeof(dod->acpiIdList[0]);
1253
1233
}
1254
1234
1255
-
printk(KERN_ERR "_DOD: ok! len:%d\n", dod->acpiIdListLen);
1256
1235
dod->status = 0;
1236
+
kfree(output.pointer);
1257
1237
}
1258
1238
#endif
1259
1239
···
2206
2186
r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED,
2207
2187
r535_gsp_msg_mmu_fault_queued, gsp);
2208
2188
r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_OS_ERROR_LOG, r535_gsp_msg_os_error_log, gsp);
2209
-
2189
+
r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE, NULL, NULL);
2190
+
r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT, NULL, NULL);
2191
+
r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_GSP_SEND_USER_SHARED_DATA, NULL, NULL);
2210
2192
ret = r535_gsp_rm_boot_ctor(gsp);
2211
2193
if (ret)
2212
2194
return ret;