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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pwm: Add Loongson PWM controller support
This commit adds a generic PWM framework driver for the PWM controller
found on Loongson family chips.
Acked-by: Huacai Chen <chenhuacai@loongson.cn>
Co-developed-by: Juxin Gao <gaojuxin@loongson.cn>
Signed-off-by: Juxin Gao <gaojuxin@loongson.cn>
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Link: https://lore.kernel.org/r/76050a903a8015422fb9261ad88c7d9cc2edbbd8.1743403075.git.zhoubinbin@loongson.cn
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
authored by
Binbin Zhou
and committed by
Uwe Kleine-König
2b62c894
90cd430f
+304
+1
MAINTAINERS
+1
MAINTAINERS
+12
drivers/pwm/Kconfig
+12
drivers/pwm/Kconfig
···
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To compile this driver as a module, choose M here: the module
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will be called pwm-keembay.
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config PWM_LOONGSON
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tristate "Loongson PWM support"
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depends on MACH_LOONGSON64 || COMPILE_TEST
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depends on COMMON_CLK
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help
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Generic PWM framework driver for Loongson family.
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It can be found on Loongson-2K series cpus and Loongson LS7A
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bridge chips.
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To compile this driver as a module, choose M here: the module
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will be called pwm-loongson.
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config PWM_LP3943
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tristate "TI/National Semiconductor LP3943 PWM support"
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depends on MFD_LP3943
+1
drivers/pwm/Makefile
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drivers/pwm/Makefile
···
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obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o
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obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
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obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o
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obj-$(CONFIG_PWM_LOONGSON) += pwm-loongson.o
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obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o
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obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o
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obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o
+290
drivers/pwm/pwm-loongson.c
+290
drivers/pwm/pwm-loongson.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017-2025 Loongson Technology Corporation Limited.
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*
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* Loongson PWM driver
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*
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* For Loongson's PWM IP block documentation please refer Chapter 11 of
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* Reference Manual: https://loongson.github.io/LoongArch-Documentation/Loongson-7A1000-usermanual-EN.pdf
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*
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* Author: Juxin Gao <gaojuxin@loongson.cn>
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* Further cleanup and restructuring by:
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* Binbin Zhou <zhoubinbin@loongson.cn>
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*
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* Limitations:
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* - If both DUTY and PERIOD are set to 0, the output is a constant low signal.
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* - When disabled the output is driven to 0 independent of the configured
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* polarity.
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* - If the register is reconfigured while PWM is running, it does not complete
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* the currently running period.
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* - Disabling the PWM stops the output immediately (without waiting for current
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* period to complete first).
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*/
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/units.h>
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/* Loongson PWM registers */
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#define LOONGSON_PWM_REG_DUTY 0x4 /* Low Pulse Buffer Register */
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#define LOONGSON_PWM_REG_PERIOD 0x8 /* Pulse Period Buffer Register */
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#define LOONGSON_PWM_REG_CTRL 0xc /* Control Register */
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/* Control register bits */
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#define LOONGSON_PWM_CTRL_REG_EN BIT(0) /* Counter Enable Bit */
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#define LOONGSON_PWM_CTRL_REG_OE BIT(3) /* Pulse Output Enable Control Bit, Valid Low */
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#define LOONGSON_PWM_CTRL_REG_SINGLE BIT(4) /* Single Pulse Control Bit */
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#define LOONGSON_PWM_CTRL_REG_INTE BIT(5) /* Interrupt Enable Bit */
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#define LOONGSON_PWM_CTRL_REG_INT BIT(6) /* Interrupt Bit */
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#define LOONGSON_PWM_CTRL_REG_RST BIT(7) /* Counter Reset Bit */
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#define LOONGSON_PWM_CTRL_REG_CAPTE BIT(8) /* Measurement Pulse Enable Bit */
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#define LOONGSON_PWM_CTRL_REG_INVERT BIT(9) /* Output flip-flop Enable Bit */
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#define LOONGSON_PWM_CTRL_REG_DZONE BIT(10) /* Anti-dead Zone Enable Bit */
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/* default input clk frequency for the ACPI case */
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#define LOONGSON_PWM_FREQ_DEFAULT 50000 /* Hz */
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struct pwm_loongson_ddata {
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struct clk *clk;
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void __iomem *base;
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u64 clk_rate;
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};
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static inline __pure struct pwm_loongson_ddata *to_pwm_loongson_ddata(struct pwm_chip *chip)
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{
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return pwmchip_get_drvdata(chip);
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}
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static inline u32 pwm_loongson_readl(struct pwm_loongson_ddata *ddata, u32 offset)
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{
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return readl(ddata->base + offset);
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}
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static inline void pwm_loongson_writel(struct pwm_loongson_ddata *ddata,
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u32 val, u32 offset)
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{
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writel(val, ddata->base + offset);
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}
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static int pwm_loongson_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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u16 val;
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struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip);
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val = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL);
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if (polarity == PWM_POLARITY_INVERSED)
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/* Duty cycle defines LOW period of PWM */
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val |= LOONGSON_PWM_CTRL_REG_INVERT;
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else
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/* Duty cycle defines HIGH period of PWM */
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val &= ~LOONGSON_PWM_CTRL_REG_INVERT;
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pwm_loongson_writel(ddata, val, LOONGSON_PWM_REG_CTRL);
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return 0;
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}
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static void pwm_loongson_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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u32 val;
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struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip);
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val = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL);
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val &= ~LOONGSON_PWM_CTRL_REG_EN;
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pwm_loongson_writel(ddata, val, LOONGSON_PWM_REG_CTRL);
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}
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static int pwm_loongson_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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u32 val;
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struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip);
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val = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL);
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val |= LOONGSON_PWM_CTRL_REG_EN;
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pwm_loongson_writel(ddata, val, LOONGSON_PWM_REG_CTRL);
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return 0;
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}
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static int pwm_loongson_config(struct pwm_chip *chip, struct pwm_device *pwm,
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u64 duty_ns, u64 period_ns)
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{
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u32 duty, period;
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struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip);
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/* duty = duty_ns * ddata->clk_rate / NSEC_PER_SEC */
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duty = mul_u64_u64_div_u64(duty_ns, ddata->clk_rate, NSEC_PER_SEC);
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if (duty > U32_MAX)
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duty = U32_MAX;
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/* period = period_ns * ddata->clk_rate / NSEC_PER_SEC */
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period = mul_u64_u64_div_u64(period_ns, ddata->clk_rate, NSEC_PER_SEC);
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if (period > U32_MAX)
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period = U32_MAX;
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pwm_loongson_writel(ddata, duty, LOONGSON_PWM_REG_DUTY);
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pwm_loongson_writel(ddata, period, LOONGSON_PWM_REG_PERIOD);
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return 0;
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}
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static int pwm_loongson_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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int ret;
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bool enabled = pwm->state.enabled;
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if (!state->enabled) {
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if (enabled)
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pwm_loongson_disable(chip, pwm);
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return 0;
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}
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ret = pwm_loongson_set_polarity(chip, pwm, state->polarity);
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if (ret)
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return ret;
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ret = pwm_loongson_config(chip, pwm, state->duty_cycle, state->period);
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if (ret)
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return ret;
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if (!enabled && state->enabled)
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ret = pwm_loongson_enable(chip, pwm);
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return ret;
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}
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static int pwm_loongson_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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u32 duty, period, ctrl;
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struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip);
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duty = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_DUTY);
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period = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_PERIOD);
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ctrl = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL);
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/* duty & period have a max of 2^32, so we can't overflow */
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state->duty_cycle = DIV64_U64_ROUND_UP((u64)duty * NSEC_PER_SEC, ddata->clk_rate);
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state->period = DIV64_U64_ROUND_UP((u64)period * NSEC_PER_SEC, ddata->clk_rate);
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state->polarity = (ctrl & LOONGSON_PWM_CTRL_REG_INVERT) ? PWM_POLARITY_INVERSED :
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PWM_POLARITY_NORMAL;
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state->enabled = (ctrl & LOONGSON_PWM_CTRL_REG_EN) ? true : false;
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return 0;
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}
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static const struct pwm_ops pwm_loongson_ops = {
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.apply = pwm_loongson_apply,
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.get_state = pwm_loongson_get_state,
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};
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static int pwm_loongson_probe(struct platform_device *pdev)
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{
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int ret;
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struct pwm_chip *chip;
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struct pwm_loongson_ddata *ddata;
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struct device *dev = &pdev->dev;
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chip = devm_pwmchip_alloc(dev, 1, sizeof(*ddata));
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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ddata = to_pwm_loongson_ddata(chip);
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ddata->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(ddata->base))
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return PTR_ERR(ddata->base);
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ddata->clk = devm_clk_get_optional_enabled(dev, NULL);
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if (IS_ERR(ddata->clk))
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return dev_err_probe(dev, PTR_ERR(ddata->clk),
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"Failed to get pwm clock\n");
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if (ddata->clk) {
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ret = devm_clk_rate_exclusive_get(dev, ddata->clk);
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if (ret)
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return dev_err_probe(dev, PTR_ERR(ddata->clk),
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"Failed to get exclusive rate\n");
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ddata->clk_rate = clk_get_rate(ddata->clk);
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if (!ddata->clk_rate)
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return dev_err_probe(dev, -EINVAL,
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"Failed to get frequency\n");
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} else {
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ddata->clk_rate = LOONGSON_PWM_FREQ_DEFAULT;
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}
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/* This check is done to prevent an overflow in .apply */
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if (ddata->clk_rate > NSEC_PER_SEC)
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return dev_err_probe(dev, -EINVAL, "PWM clock out of range\n");
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chip->ops = &pwm_loongson_ops;
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chip->atomic = true;
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dev_set_drvdata(dev, chip);
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ret = devm_pwmchip_add(dev, chip);
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if (ret < 0)
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return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
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return 0;
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}
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static int pwm_loongson_suspend(struct device *dev)
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{
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struct pwm_chip *chip = dev_get_drvdata(dev);
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struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip);
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struct pwm_device *pwm = &chip->pwms[0];
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if (pwm->state.enabled)
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return -EBUSY;
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clk_disable_unprepare(ddata->clk);
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return 0;
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}
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static int pwm_loongson_resume(struct device *dev)
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{
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struct pwm_chip *chip = dev_get_drvdata(dev);
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struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip);
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return clk_prepare_enable(ddata->clk);
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(pwm_loongson_pm_ops, pwm_loongson_suspend,
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pwm_loongson_resume);
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static const struct of_device_id pwm_loongson_of_ids[] = {
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{ .compatible = "loongson,ls7a-pwm" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, pwm_loongson_of_ids);
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static const struct acpi_device_id pwm_loongson_acpi_ids[] = {
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{ "LOON0006" },
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{ }
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};
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MODULE_DEVICE_TABLE(acpi, pwm_loongson_acpi_ids);
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static struct platform_driver pwm_loongson_driver = {
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.probe = pwm_loongson_probe,
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.driver = {
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.name = "loongson-pwm",
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.pm = pm_ptr(&pwm_loongson_pm_ops),
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.of_match_table = pwm_loongson_of_ids,
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.acpi_match_table = pwm_loongson_acpi_ids,
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},
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};
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module_platform_driver(pwm_loongson_driver);
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MODULE_DESCRIPTION("Loongson PWM driver");
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MODULE_AUTHOR("Loongson Technology Corporation Limited.");
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MODULE_LICENSE("GPL");