Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Madhavan Srinivasan:
- Correct MSI allocation tracking
- Always use 64 bits PTE for powerpc/e500
- Fix inline assembly for clang build on PPC32
- Fixes for clang build issues in powerpc64/ftrace
- Fixes for powerpc64/bpf JIT and tailcall support
- Cleanup MPC83XX devicetrees
- Fix keymile vendor prefix
- Fix to use big-endian types for crash variables
Thanks to Abhishek Dubey, Christophe Leroy (CS GROUP), Hari Bathini,
Heiko Schocher, J. Neuschäfer, Mahesh Salgaonkar, Nam Cao, Nilay Shroff,
Rob Herring (Arm), Saket Kumar Bhaskar, Sourabh Jain, Stan Johnson, and
Venkat Rao Bagalkote.
* tag 'powerpc-7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (23 commits)
powerpc/pseries: Correct MSI allocation tracking
powerpc: dts: mpc83xx: Add unit addresses to /memory
powerpc: dts: mpc8315erdb: Add missing #cells properties to SPI bus
powerpc: dts: mpc8315erdb: Rename LED nodes to comply with schema
powerpc: dts: mpc8315erdb: Use IRQ_TYPE_* macros
powerpc: dts: mpc8313erdb: Use IRQ_TYPE_* macros
powerpc: 83xx: km83xx: Fix keymile vendor prefix
dt-bindings: powerpc: Add Freescale/NXP MPC83xx SoCs
powerpc64/bpf: fix kfunc call support
powerpc64/bpf: fix handling of BPF stack in exception callback
powerpc64/bpf: remove BPF redzone protection in trampoline stack
powerpc64/bpf: use consistent tailcall offset in trampoline
powerpc64/bpf: fix the address returned by bpf_get_func_ip
powerpc64/bpf: do not increment tailcall count when prog is NULL
powerpc64/ftrace: workaround clang recording GEP in __patchable_function_entries
powerpc64/ftrace: fix OOL stub count with clang
powerpc64: make clang cross-build friendly
powerpc/crash: adjust the elfcorehdr size
powerpc/kexec/core: use big-endian types for crash variables
powerpc/prom_init: Fixup missing #size-cells on PowerMac media-bay nodes
...
+460
-661
+93
Documentation/devicetree/bindings/powerpc/fsl/fsl,mpc83xx.yaml
+93
Documentation/devicetree/bindings/powerpc/fsl/fsl,mpc83xx.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/powerpc/fsl/fsl,mpc83xx.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale PowerQUICC II Pro (MPC83xx) platforms
8
+
9
+
maintainers:
10
+
- J. Neuschäfer <j.ne@posteo.net>
11
+
12
+
properties:
13
+
$nodename:
14
+
const: '/'
15
+
compatible:
16
+
oneOf:
17
+
- description: MPC83xx Reference Design Boards
18
+
items:
19
+
- enum:
20
+
- fsl,mpc8308rdb
21
+
- fsl,mpc8315erdb
22
+
- fsl,mpc8360rdk
23
+
- fsl,mpc8377rdb
24
+
- fsl,mpc8377wlan
25
+
- fsl,mpc8378rdb
26
+
- fsl,mpc8379rdb
27
+
28
+
- description: MPC8313E Reference Design Board
29
+
items:
30
+
- const: MPC8313ERDB
31
+
- const: MPC831xRDB
32
+
- const: MPC83xxRDB
33
+
34
+
- description: MPC8323E Reference Design Board
35
+
items:
36
+
- const: MPC8323ERDB
37
+
- const: MPC832xRDB
38
+
- const: MPC83xxRDB
39
+
40
+
- description: MPC8349E-mITX(-GP) Reference Design Platform
41
+
items:
42
+
- enum:
43
+
- MPC8349EMITX
44
+
- MPC8349EMITXGP
45
+
- const: MPC834xMITX
46
+
- const: MPC83xxMITX
47
+
48
+
- description: Keymile KMETER1 board
49
+
const: keymile,KMETER1
50
+
51
+
- description: MPC8308 P1M board
52
+
const: denx,mpc8308_p1m
53
+
54
+
patternProperties:
55
+
"^soc@.*$":
56
+
type: object
57
+
properties:
58
+
compatible:
59
+
oneOf:
60
+
- items:
61
+
- enum:
62
+
- fsl,mpc8315-immr
63
+
- fsl,mpc8308-immr
64
+
- const: simple-bus
65
+
- items:
66
+
- const: fsl,mpc8360-immr
67
+
- const: fsl,immr
68
+
- const: fsl,soc
69
+
- const: simple-bus
70
+
- const: simple-bus
71
+
72
+
additionalProperties: true
73
+
74
+
examples:
75
+
- |
76
+
/ {
77
+
compatible = "fsl,mpc8315erdb";
78
+
model = "MPC8315E-RDB";
79
+
#address-cells = <1>;
80
+
#size-cells = <1>;
81
+
82
+
soc@e0000000 {
83
+
compatible = "fsl,mpc8315-immr", "simple-bus";
84
+
reg = <0xe0000000 0x00000200>;
85
+
#address-cells = <1>;
86
+
#size-cells = <1>;
87
+
device_type = "soc";
88
+
ranges = <0 0xe0000000 0x00100000>;
89
+
bus-frequency = <0>;
90
+
};
91
+
};
92
+
93
+
...
+2
-2
arch/powerpc/Kconfig
+2
-2
arch/powerpc/Kconfig
···
573
573
depends on FUNCTION_TRACER && (PPC32 || PPC64_ELF_ABI_V2)
574
574
depends on $(cc-option,-fpatchable-function-entry=2)
575
575
def_bool y if PPC32
576
-
def_bool $(success,$(srctree)/arch/powerpc/tools/gcc-check-fpatchable-function-entry.sh $(CC) -mlittle-endian) if PPC64 && CPU_LITTLE_ENDIAN
577
-
def_bool $(success,$(srctree)/arch/powerpc/tools/gcc-check-fpatchable-function-entry.sh $(CC) -mbig-endian) if PPC64 && CPU_BIG_ENDIAN
576
+
def_bool $(success,$(srctree)/arch/powerpc/tools/check-fpatchable-function-entry.sh $(CC) $(CLANG_FLAGS) -mlittle-endian) if PPC64 && CPU_LITTLE_ENDIAN
577
+
def_bool $(success,$(srctree)/arch/powerpc/tools/check-fpatchable-function-entry.sh $(CC) -mbig-endian) if PPC64 && CPU_BIG_ENDIAN
578
578
579
579
config PPC_FTRACE_OUT_OF_LINE
580
580
def_bool PPC64 && ARCH_USING_PATCHABLE_FUNCTION_ENTRY
+1
-1
arch/powerpc/boot/dts/asp834x-redboot.dts
+1
-1
arch/powerpc/boot/dts/asp834x-redboot.dts
-156
arch/powerpc/boot/dts/fsl/interlaken-lac-portals.dtsi
-156
arch/powerpc/boot/dts/fsl/interlaken-lac-portals.dtsi
···
1
-
/* T4240 Interlaken LAC Portal device tree stub with 24 portals.
2
-
*
3
-
* Copyright 2012 Freescale Semiconductor Inc.
4
-
*
5
-
* Redistribution and use in source and binary forms, with or without
6
-
* modification, are permitted provided that the following conditions are met:
7
-
* * Redistributions of source code must retain the above copyright
8
-
* notice, this list of conditions and the following disclaimer.
9
-
* * Redistributions in binary form must reproduce the above copyright
10
-
* notice, this list of conditions and the following disclaimer in the
11
-
* documentation and/or other materials provided with the distribution.
12
-
* * Neither the name of Freescale Semiconductor nor the
13
-
* names of its contributors may be used to endorse or promote products
14
-
* derived from this software without specific prior written permission.
15
-
*
16
-
*
17
-
* ALTERNATIVELY, this software may be distributed under the terms of the
18
-
* GNU General Public License ("GPL") as published by the Free Software
19
-
* Foundation, either version 2 of that License or (at your option) any
20
-
* later version.
21
-
*
22
-
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
23
-
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24
-
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25
-
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
26
-
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27
-
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28
-
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29
-
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30
-
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31
-
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32
-
*/
33
-
34
-
#address-cells = <0x1>;
35
-
#size-cells = <0x1>;
36
-
compatible = "fsl,interlaken-lac-portals";
37
-
38
-
lportal0: lac-portal@0 {
39
-
compatible = "fsl,interlaken-lac-portal-v1.0";
40
-
reg = <0x0 0x1000>;
41
-
};
42
-
43
-
lportal1: lac-portal@1000 {
44
-
compatible = "fsl,interlaken-lac-portal-v1.0";
45
-
reg = <0x1000 0x1000>;
46
-
};
47
-
48
-
lportal2: lac-portal@2000 {
49
-
compatible = "fsl,interlaken-lac-portal-v1.0";
50
-
reg = <0x2000 0x1000>;
51
-
};
52
-
53
-
lportal3: lac-portal@3000 {
54
-
compatible = "fsl,interlaken-lac-portal-v1.0";
55
-
reg = <0x3000 0x1000>;
56
-
};
57
-
58
-
lportal4: lac-portal@4000 {
59
-
compatible = "fsl,interlaken-lac-portal-v1.0";
60
-
reg = <0x4000 0x1000>;
61
-
};
62
-
63
-
lportal5: lac-portal@5000 {
64
-
compatible = "fsl,interlaken-lac-portal-v1.0";
65
-
reg = <0x5000 0x1000>;
66
-
};
67
-
68
-
lportal6: lac-portal@6000 {
69
-
compatible = "fsl,interlaken-lac-portal-v1.0";
70
-
reg = <0x6000 0x1000>;
71
-
};
72
-
73
-
lportal7: lac-portal@7000 {
74
-
compatible = "fsl,interlaken-lac-portal-v1.0";
75
-
reg = <0x7000 0x1000>;
76
-
};
77
-
78
-
lportal8: lac-portal@8000 {
79
-
compatible = "fsl,interlaken-lac-portal-v1.0";
80
-
reg = <0x8000 0x1000>;
81
-
};
82
-
83
-
lportal9: lac-portal@9000 {
84
-
compatible = "fsl,interlaken-lac-portal-v1.0";
85
-
reg = <0x9000 0x1000>;
86
-
};
87
-
88
-
lportal10: lac-portal@A000 {
89
-
compatible = "fsl,interlaken-lac-portal-v1.0";
90
-
reg = <0xA000 0x1000>;
91
-
};
92
-
93
-
lportal11: lac-portal@B000 {
94
-
compatible = "fsl,interlaken-lac-portal-v1.0";
95
-
reg = <0xB000 0x1000>;
96
-
};
97
-
98
-
lportal12: lac-portal@C000 {
99
-
compatible = "fsl,interlaken-lac-portal-v1.0";
100
-
reg = <0xC000 0x1000>;
101
-
};
102
-
103
-
lportal13: lac-portal@D000 {
104
-
compatible = "fsl,interlaken-lac-portal-v1.0";
105
-
reg = <0xD000 0x1000>;
106
-
};
107
-
108
-
lportal14: lac-portal@E000 {
109
-
compatible = "fsl,interlaken-lac-portal-v1.0";
110
-
reg = <0xE000 0x1000>;
111
-
};
112
-
113
-
lportal15: lac-portal@F000 {
114
-
compatible = "fsl,interlaken-lac-portal-v1.0";
115
-
reg = <0xF000 0x1000>;
116
-
};
117
-
118
-
lportal16: lac-portal@10000 {
119
-
compatible = "fsl,interlaken-lac-portal-v1.0";
120
-
reg = <0x10000 0x1000>;
121
-
};
122
-
123
-
lportal17: lac-portal@11000 {
124
-
compatible = "fsl,interlaken-lac-portal-v1.0";
125
-
reg = <0x11000 0x1000>;
126
-
};
127
-
128
-
lportal18: lac-portal@1200 {
129
-
compatible = "fsl,interlaken-lac-portal-v1.0";
130
-
reg = <0x12000 0x1000>;
131
-
};
132
-
133
-
lportal19: lac-portal@13000 {
134
-
compatible = "fsl,interlaken-lac-portal-v1.0";
135
-
reg = <0x13000 0x1000>;
136
-
};
137
-
138
-
lportal20: lac-portal@14000 {
139
-
compatible = "fsl,interlaken-lac-portal-v1.0";
140
-
reg = <0x14000 0x1000>;
141
-
};
142
-
143
-
lportal21: lac-portal@15000 {
144
-
compatible = "fsl,interlaken-lac-portal-v1.0";
145
-
reg = <0x15000 0x1000>;
146
-
};
147
-
148
-
lportal22: lac-portal@16000 {
149
-
compatible = "fsl,interlaken-lac-portal-v1.0";
150
-
reg = <0x16000 0x1000>;
151
-
};
152
-
153
-
lportal23: lac-portal@17000 {
154
-
compatible = "fsl,interlaken-lac-portal-v1.0";
155
-
reg = <0x17000 0x1000>;
156
-
};
-45
arch/powerpc/boot/dts/fsl/interlaken-lac.dtsi
-45
arch/powerpc/boot/dts/fsl/interlaken-lac.dtsi
···
1
-
/*
2
-
* T4 Interlaken Look-aside Controller (LAC) device tree stub
3
-
*
4
-
* Copyright 2012 Freescale Semiconductor Inc.
5
-
*
6
-
* Redistribution and use in source and binary forms, with or without
7
-
* modification, are permitted provided that the following conditions are met:
8
-
* * Redistributions of source code must retain the above copyright
9
-
* notice, this list of conditions and the following disclaimer.
10
-
* * Redistributions in binary form must reproduce the above copyright
11
-
* notice, this list of conditions and the following disclaimer in the
12
-
* documentation and/or other materials provided with the distribution.
13
-
* * Neither the name of Freescale Semiconductor nor the
14
-
* names of its contributors may be used to endorse or promote products
15
-
* derived from this software without specific prior written permission.
16
-
*
17
-
*
18
-
* ALTERNATIVELY, this software may be distributed under the terms of the
19
-
* GNU General Public License ("GPL") as published by the Free Software
20
-
* Foundation, either version 2 of that License or (at your option) any
21
-
* later version.
22
-
*
23
-
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24
-
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25
-
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26
-
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27
-
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28
-
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29
-
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30
-
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31
-
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32
-
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33
-
*/
34
-
35
-
lac: lac@229000 {
36
-
compatible = "fsl,interlaken-lac";
37
-
reg = <0x229000 0x1000>;
38
-
interrupts = <16 2 1 18>;
39
-
};
40
-
41
-
lac-hv@228000 {
42
-
compatible = "fsl,interlaken-lac-hv";
43
-
reg = <0x228000 0x1000>;
44
-
fsl,non-hv-node = <&lac>;
45
-
};
-43
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
-43
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
···
1
-
/*
2
-
* PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
3
-
*
4
-
* Copyright 2012 Freescale Semiconductor Inc.
5
-
*
6
-
* Redistribution and use in source and binary forms, with or without
7
-
* modification, are permitted provided that the following conditions are met:
8
-
* * Redistributions of source code must retain the above copyright
9
-
* notice, this list of conditions and the following disclaimer.
10
-
* * Redistributions in binary form must reproduce the above copyright
11
-
* notice, this list of conditions and the following disclaimer in the
12
-
* documentation and/or other materials provided with the distribution.
13
-
* * Neither the name of Freescale Semiconductor nor the
14
-
* names of its contributors may be used to endorse or promote products
15
-
* derived from this software without specific prior written permission.
16
-
*
17
-
*
18
-
* ALTERNATIVELY, this software may be distributed under the terms of the
19
-
* GNU General Public License ("GPL") as published by the Free Software
20
-
* Foundation, either version 2 of that License or (at your option) any
21
-
* later version.
22
-
*
23
-
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24
-
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25
-
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26
-
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27
-
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28
-
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29
-
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30
-
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31
-
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32
-
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33
-
*/
34
-
35
-
message@42400 {
36
-
compatible = "fsl,mpic-v3.1-msgr";
37
-
reg = <0x42400 0x200>;
38
-
interrupts = <
39
-
0xb4 2 0 0
40
-
0xb5 2 0 0
41
-
0xb6 2 0 0
42
-
0xb7 2 0 0>;
43
-
};
-80
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
-80
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
···
1
-
/*
2
-
* QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
3
-
*
4
-
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
5
-
*
6
-
* Redistribution and use in source and binary forms, with or without
7
-
* modification, are permitted provided that the following conditions are met:
8
-
* * Redistributions of source code must retain the above copyright
9
-
* notice, this list of conditions and the following disclaimer.
10
-
* * Redistributions in binary form must reproduce the above copyright
11
-
* notice, this list of conditions and the following disclaimer in the
12
-
* documentation and/or other materials provided with the distribution.
13
-
* * Neither the name of Freescale Semiconductor nor the
14
-
* names of its contributors may be used to endorse or promote products
15
-
* derived from this software without specific prior written permission.
16
-
*
17
-
*
18
-
* ALTERNATIVELY, this software may be distributed under the terms of the
19
-
* GNU General Public License ("GPL") as published by the Free Software
20
-
* Foundation, either version 2 of that License or (at your option) any
21
-
* later version.
22
-
*
23
-
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24
-
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25
-
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26
-
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27
-
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28
-
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29
-
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30
-
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31
-
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32
-
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33
-
*/
34
-
35
-
fman@400000 {
36
-
fman0_rx_0x09: port@89000 {
37
-
cell-index = <0x9>;
38
-
compatible = "fsl,fman-v3-port-rx";
39
-
reg = <0x89000 0x1000>;
40
-
fsl,fman-10g-port;
41
-
fsl,fman-best-effort-port;
42
-
};
43
-
44
-
fman0_tx_0x29: port@a9000 {
45
-
cell-index = <0x29>;
46
-
compatible = "fsl,fman-v3-port-tx";
47
-
reg = <0xa9000 0x1000>;
48
-
fsl,fman-10g-port;
49
-
fsl,fman-best-effort-port;
50
-
};
51
-
52
-
ethernet@e2000 {
53
-
cell-index = <1>;
54
-
compatible = "fsl,fman-memac";
55
-
reg = <0xe2000 0x1000>;
56
-
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
57
-
ptp-timer = <&ptp_timer0>;
58
-
pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
59
-
pcs-handle-names = "sgmii", "qsgmii";
60
-
};
61
-
62
-
mdio@e1000 {
63
-
qsgmiia_pcs1: ethernet-pcs@1 {
64
-
compatible = "fsl,lynx-pcs";
65
-
reg = <1>;
66
-
};
67
-
};
68
-
69
-
mdio@e3000 {
70
-
#address-cells = <1>;
71
-
#size-cells = <0>;
72
-
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
73
-
reg = <0xe3000 0x1000>;
74
-
fsl,erratum-a011043; /* must ignore read errors */
75
-
76
-
pcsphy1: ethernet-phy@0 {
77
-
reg = <0x0>;
78
-
};
79
-
};
80
-
};
+1
-1
arch/powerpc/boot/dts/mpc8308_p1m.dts
+1
-1
arch/powerpc/boot/dts/mpc8308_p1m.dts
+1
-1
arch/powerpc/boot/dts/mpc8308rdb.dts
+1
-1
arch/powerpc/boot/dts/mpc8308rdb.dts
+35
-26
arch/powerpc/boot/dts/mpc8313erdb.dts
+35
-26
arch/powerpc/boot/dts/mpc8313erdb.dts
···
6
6
*/
7
7
8
8
/dts-v1/;
9
+
#include <dt-bindings/interrupt-controller/irq.h>
9
10
10
11
/ {
11
12
model = "MPC8313ERDB";
···
39
38
};
40
39
};
41
40
42
-
memory {
41
+
memory@0 {
43
42
device_type = "memory";
44
43
reg = <0x00000000 0x08000000>; // 128MB at 0
45
44
};
···
49
48
#size-cells = <1>;
50
49
compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
51
50
reg = <0xe0005000 0x1000>;
52
-
interrupts = <77 0x8>;
51
+
interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
53
52
interrupt-parent = <&ipic>;
54
53
55
54
// CS0 and CS1 are swapped when
···
119
118
cell-index = <0>;
120
119
compatible = "fsl-i2c";
121
120
reg = <0x3000 0x100>;
122
-
interrupts = <14 0x8>;
121
+
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
123
122
interrupt-parent = <&ipic>;
124
123
dfsrr;
125
124
rtc@68 {
···
132
131
compatible = "fsl,sec2.2", "fsl,sec2.1",
133
132
"fsl,sec2.0";
134
133
reg = <0x30000 0x10000>;
135
-
interrupts = <11 0x8>;
134
+
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
136
135
interrupt-parent = <&ipic>;
137
136
fsl,num-channels = <1>;
138
137
fsl,channel-fifo-len = <24>;
···
147
146
cell-index = <1>;
148
147
compatible = "fsl-i2c";
149
148
reg = <0x3100 0x100>;
150
-
interrupts = <15 0x8>;
149
+
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
151
150
interrupt-parent = <&ipic>;
152
151
dfsrr;
153
152
};
···
156
155
cell-index = <0>;
157
156
compatible = "fsl,spi";
158
157
reg = <0x7000 0x1000>;
159
-
interrupts = <16 0x8>;
158
+
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
160
159
interrupt-parent = <&ipic>;
161
160
mode = "cpu";
162
161
};
···
168
167
#address-cells = <1>;
169
168
#size-cells = <0>;
170
169
interrupt-parent = <&ipic>;
171
-
interrupts = <38 0x8>;
170
+
interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
172
171
phy_type = "utmi_wide";
173
172
sleep = <&pmc 0x00300000>;
174
173
};
···
176
175
ptp_clock@24E00 {
177
176
compatible = "fsl,etsec-ptp";
178
177
reg = <0x24E00 0xB0>;
179
-
interrupts = <12 0x8 13 0x8>;
178
+
interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
179
+
<13 IRQ_TYPE_LEVEL_LOW>;
180
180
interrupt-parent = < &ipic >;
181
181
fsl,tclk-period = <10>;
182
182
fsl,tmr-prsc = <100>;
···
199
197
compatible = "gianfar";
200
198
reg = <0x24000 0x1000>;
201
199
local-mac-address = [ 00 00 00 00 00 00 ];
202
-
interrupts = <37 0x8 36 0x8 35 0x8>;
200
+
interrupts = <37 IRQ_TYPE_LEVEL_LOW>,
201
+
<36 IRQ_TYPE_LEVEL_LOW>,
202
+
<35 IRQ_TYPE_LEVEL_LOW>;
203
203
interrupt-parent = <&ipic>;
204
204
tbi-handle = < &tbi0 >;
205
205
/* Vitesse 7385 isn't on the MDIO bus */
···
215
211
reg = <0x520 0x20>;
216
212
phy4: ethernet-phy@4 {
217
213
interrupt-parent = <&ipic>;
218
-
interrupts = <20 0x8>;
214
+
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
219
215
reg = <0x4>;
220
216
};
221
217
tbi0: tbi-phy@11 {
···
235
231
reg = <0x25000 0x1000>;
236
232
ranges = <0x0 0x25000 0x1000>;
237
233
local-mac-address = [ 00 00 00 00 00 00 ];
238
-
interrupts = <34 0x8 33 0x8 32 0x8>;
234
+
interrupts = <34 IRQ_TYPE_LEVEL_LOW>,
235
+
<33 IRQ_TYPE_LEVEL_LOW>,
236
+
<32 IRQ_TYPE_LEVEL_LOW>;
239
237
interrupt-parent = <&ipic>;
240
238
tbi-handle = < &tbi1 >;
241
239
phy-handle = < &phy4 >;
···
265
259
compatible = "fsl,ns16550", "ns16550";
266
260
reg = <0x4500 0x100>;
267
261
clock-frequency = <0>;
268
-
interrupts = <9 0x8>;
262
+
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
269
263
interrupt-parent = <&ipic>;
270
264
};
271
265
···
275
269
compatible = "fsl,ns16550", "ns16550";
276
270
reg = <0x4600 0x100>;
277
271
clock-frequency = <0>;
278
-
interrupts = <10 0x8>;
272
+
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
279
273
interrupt-parent = <&ipic>;
280
274
};
281
275
282
276
/* IPIC
283
-
* interrupts cell = <intr #, sense>
284
-
* sense values match linux IORESOURCE_IRQ_* defines:
285
-
* sense == 8: Level, low assertion
286
-
* sense == 2: Edge, high-to-low change
277
+
* interrupts cell = <intr #, type>
287
278
*/
288
279
ipic: pic@700 {
289
280
interrupt-controller;
···
293
290
pmc: power@b00 {
294
291
compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
295
292
reg = <0xb00 0x100 0xa00 0x100>;
296
-
interrupts = <80 8>;
293
+
interrupts = <80 IRQ_TYPE_LEVEL_LOW>;
297
294
interrupt-parent = <&ipic>;
298
295
fsl,mpc8313-wakeup-timer = <>m1>;
299
296
···
309
306
gtm1: timer@500 {
310
307
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
311
308
reg = <0x500 0x100>;
312
-
interrupts = <90 8 78 8 84 8 72 8>;
309
+
interrupts = <90 IRQ_TYPE_LEVEL_LOW>,
310
+
<78 IRQ_TYPE_LEVEL_LOW>,
311
+
<84 IRQ_TYPE_LEVEL_LOW>,
312
+
<72 IRQ_TYPE_LEVEL_LOW>;
313
313
interrupt-parent = <&ipic>;
314
314
};
315
315
316
316
timer@600 {
317
317
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
318
318
reg = <0x600 0x100>;
319
-
interrupts = <91 8 79 8 85 8 73 8>;
319
+
interrupts = <91 IRQ_TYPE_LEVEL_LOW>,
320
+
<79 IRQ_TYPE_LEVEL_LOW>,
321
+
<85 IRQ_TYPE_LEVEL_LOW>,
322
+
<73 IRQ_TYPE_LEVEL_LOW>;
320
323
interrupt-parent = <&ipic>;
321
324
};
322
325
};
···
350
341
0x7800 0x0 0x0 0x3 &ipic 17 0x8
351
342
0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
352
343
interrupt-parent = <&ipic>;
353
-
interrupts = <66 0x8>;
344
+
interrupts = <66 IRQ_TYPE_LEVEL_LOW>;
354
345
bus-range = <0x0 0x0>;
355
346
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
356
347
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
···
372
363
reg = <0xe00082a8 4>;
373
364
ranges = <0 0xe0008100 0x1a8>;
374
365
interrupt-parent = <&ipic>;
375
-
interrupts = <71 8>;
366
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
376
367
377
368
dma-channel@0 {
378
369
compatible = "fsl,mpc8313-dma-channel",
379
370
"fsl,elo-dma-channel";
380
371
reg = <0 0x28>;
381
372
interrupt-parent = <&ipic>;
382
-
interrupts = <71 8>;
373
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
383
374
cell-index = <0>;
384
375
};
385
376
···
388
379
"fsl,elo-dma-channel";
389
380
reg = <0x80 0x28>;
390
381
interrupt-parent = <&ipic>;
391
-
interrupts = <71 8>;
382
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
392
383
cell-index = <1>;
393
384
};
394
385
···
397
388
"fsl,elo-dma-channel";
398
389
reg = <0x100 0x28>;
399
390
interrupt-parent = <&ipic>;
400
-
interrupts = <71 8>;
391
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
401
392
cell-index = <2>;
402
393
};
403
394
···
406
397
"fsl,elo-dma-channel";
407
398
reg = <0x180 0x28>;
408
399
interrupt-parent = <&ipic>;
409
-
interrupts = <71 8>;
400
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
410
401
cell-index = <3>;
411
402
};
412
403
};
+64
-55
arch/powerpc/boot/dts/mpc8315erdb.dts
+64
-55
arch/powerpc/boot/dts/mpc8315erdb.dts
···
40
40
};
41
41
};
42
42
43
-
memory {
43
+
memory@0 {
44
44
device_type = "memory";
45
45
reg = <0x00000000 0x08000000>; // 128MB at 0
46
46
};
···
50
50
#size-cells = <1>;
51
51
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
52
52
reg = <0xe0005000 0x1000>;
53
-
interrupts = <77 0x8>;
53
+
interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
54
54
interrupt-parent = <&ipic>;
55
55
56
56
// CS0 and CS1 are swapped when
···
112
112
cell-index = <0>;
113
113
compatible = "fsl-i2c";
114
114
reg = <0x3000 0x100>;
115
-
interrupts = <14 0x8>;
115
+
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
116
116
interrupt-parent = <&ipic>;
117
117
dfsrr;
118
118
rtc@68 {
···
133
133
cell-index = <0>;
134
134
compatible = "fsl,spi";
135
135
reg = <0x7000 0x1000>;
136
-
interrupts = <16 0x8>;
136
+
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
137
137
interrupt-parent = <&ipic>;
138
+
#address-cells = <1>;
139
+
#size-cells = <0>;
138
140
mode = "cpu";
139
141
};
140
142
···
147
145
reg = <0x82a8 4>;
148
146
ranges = <0 0x8100 0x1a8>;
149
147
interrupt-parent = <&ipic>;
150
-
interrupts = <71 8>;
148
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
151
149
cell-index = <0>;
152
150
dma-channel@0 {
153
151
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
154
152
reg = <0 0x80>;
155
153
cell-index = <0>;
156
154
interrupt-parent = <&ipic>;
157
-
interrupts = <71 8>;
155
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
158
156
};
159
157
dma-channel@80 {
160
158
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
161
159
reg = <0x80 0x80>;
162
160
cell-index = <1>;
163
161
interrupt-parent = <&ipic>;
164
-
interrupts = <71 8>;
162
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
165
163
};
166
164
dma-channel@100 {
167
165
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
168
166
reg = <0x100 0x80>;
169
167
cell-index = <2>;
170
168
interrupt-parent = <&ipic>;
171
-
interrupts = <71 8>;
169
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
172
170
};
173
171
dma-channel@180 {
174
172
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
175
173
reg = <0x180 0x28>;
176
174
cell-index = <3>;
177
175
interrupt-parent = <&ipic>;
178
-
interrupts = <71 8>;
176
+
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
179
177
};
180
178
};
181
179
···
185
183
#address-cells = <1>;
186
184
#size-cells = <0>;
187
185
interrupt-parent = <&ipic>;
188
-
interrupts = <38 0x8>;
186
+
interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
189
187
phy_type = "utmi";
190
188
};
191
189
···
199
197
reg = <0x24000 0x1000>;
200
198
ranges = <0x0 0x24000 0x1000>;
201
199
local-mac-address = [ 00 00 00 00 00 00 ];
202
-
interrupts = <32 0x8 33 0x8 34 0x8>;
200
+
interrupts = <32 IRQ_TYPE_LEVEL_LOW>,
201
+
<33 IRQ_TYPE_LEVEL_LOW>,
202
+
<34 IRQ_TYPE_LEVEL_LOW>;
203
203
interrupt-parent = <&ipic>;
204
204
tbi-handle = <&tbi0>;
205
205
phy-handle = < &phy0 >;
···
242
238
reg = <0x25000 0x1000>;
243
239
ranges = <0x0 0x25000 0x1000>;
244
240
local-mac-address = [ 00 00 00 00 00 00 ];
245
-
interrupts = <35 0x8 36 0x8 37 0x8>;
241
+
interrupts = <35 IRQ_TYPE_LEVEL_LOW>,
242
+
<36 IRQ_TYPE_LEVEL_LOW>,
243
+
<37 IRQ_TYPE_LEVEL_LOW>;
246
244
interrupt-parent = <&ipic>;
247
245
tbi-handle = <&tbi1>;
248
246
phy-handle = < &phy1 >;
···
269
263
compatible = "fsl,ns16550", "ns16550";
270
264
reg = <0x4500 0x100>;
271
265
clock-frequency = <133333333>;
272
-
interrupts = <9 0x8>;
266
+
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
273
267
interrupt-parent = <&ipic>;
274
268
};
275
269
···
279
273
compatible = "fsl,ns16550", "ns16550";
280
274
reg = <0x4600 0x100>;
281
275
clock-frequency = <133333333>;
282
-
interrupts = <10 0x8>;
276
+
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
283
277
interrupt-parent = <&ipic>;
284
278
};
285
279
···
288
282
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
289
283
"fsl,sec2.0";
290
284
reg = <0x30000 0x10000>;
291
-
interrupts = <11 0x8>;
285
+
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
292
286
interrupt-parent = <&ipic>;
293
287
fsl,num-channels = <4>;
294
288
fsl,channel-fifo-len = <24>;
···
300
294
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
301
295
reg = <0x18000 0x1000>;
302
296
cell-index = <1>;
303
-
interrupts = <44 0x8>;
297
+
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
304
298
interrupt-parent = <&ipic>;
305
299
};
306
300
···
308
302
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
309
303
reg = <0x19000 0x1000>;
310
304
cell-index = <2>;
311
-
interrupts = <45 0x8>;
305
+
interrupts = <45 IRQ_TYPE_LEVEL_LOW>;
312
306
interrupt-parent = <&ipic>;
313
307
};
314
308
315
309
gtm1: timer@500 {
316
310
compatible = "fsl,mpc8315-gtm", "fsl,gtm";
317
311
reg = <0x500 0x100>;
318
-
interrupts = <90 8 78 8 84 8 72 8>;
312
+
interrupts = <90 IRQ_TYPE_LEVEL_LOW>,
313
+
<78 IRQ_TYPE_LEVEL_LOW>,
314
+
<84 IRQ_TYPE_LEVEL_LOW>,
315
+
<72 IRQ_TYPE_LEVEL_LOW>;
319
316
interrupt-parent = <&ipic>;
320
317
clock-frequency = <133333333>;
321
318
};
···
326
317
timer@600 {
327
318
compatible = "fsl,mpc8315-gtm", "fsl,gtm";
328
319
reg = <0x600 0x100>;
329
-
interrupts = <91 8 79 8 85 8 73 8>;
320
+
interrupts = <91 IRQ_TYPE_LEVEL_LOW>,
321
+
<79 IRQ_TYPE_LEVEL_LOW>,
322
+
<85 IRQ_TYPE_LEVEL_LOW>,
323
+
<73 IRQ_TYPE_LEVEL_LOW>;
330
324
interrupt-parent = <&ipic>;
331
325
clock-frequency = <133333333>;
332
326
};
333
327
334
328
/* IPIC
335
-
* interrupts cell = <intr #, sense>
336
-
* sense values match linux IORESOURCE_IRQ_* defines:
337
-
* sense == 8: Level, low assertion
338
-
* sense == 2: Edge, high-to-low change
329
+
* interrupts cell = <intr #, type>
339
330
*/
340
331
ipic: interrupt-controller@700 {
341
332
interrupt-controller;
···
349
340
compatible = "fsl,ipic-msi";
350
341
reg = <0x7c0 0x40>;
351
342
msi-available-ranges = <0 0x100>;
352
-
interrupts = <0x43 0x8
353
-
0x4 0x8
354
-
0x51 0x8
355
-
0x52 0x8
356
-
0x56 0x8
357
-
0x57 0x8
358
-
0x58 0x8
359
-
0x59 0x8>;
343
+
interrupts = <0x43 IRQ_TYPE_LEVEL_LOW
344
+
0x4 IRQ_TYPE_LEVEL_LOW
345
+
0x51 IRQ_TYPE_LEVEL_LOW
346
+
0x52 IRQ_TYPE_LEVEL_LOW
347
+
0x56 IRQ_TYPE_LEVEL_LOW
348
+
0x57 IRQ_TYPE_LEVEL_LOW
349
+
0x58 IRQ_TYPE_LEVEL_LOW
350
+
0x59 IRQ_TYPE_LEVEL_LOW>;
360
351
interrupt-parent = < &ipic >;
361
352
};
362
353
···
364
355
compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
365
356
"fsl,mpc8349-pmc";
366
357
reg = <0xb00 0x100 0xa00 0x100>;
367
-
interrupts = <80 8>;
358
+
interrupts = <80 IRQ_TYPE_LEVEL_LOW>;
368
359
interrupt-parent = <&ipic>;
369
360
fsl,mpc8313-wakeup-timer = <>m1>;
370
361
};
···
383
374
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
384
375
interrupt-map = <
385
376
/* IDSEL 0x0E -mini PCI */
386
-
0x7000 0x0 0x0 0x1 &ipic 18 0x8
387
-
0x7000 0x0 0x0 0x2 &ipic 18 0x8
388
-
0x7000 0x0 0x0 0x3 &ipic 18 0x8
389
-
0x7000 0x0 0x0 0x4 &ipic 18 0x8
377
+
0x7000 0x0 0x0 0x1 &ipic 18 IRQ_TYPE_LEVEL_LOW
378
+
0x7000 0x0 0x0 0x2 &ipic 18 IRQ_TYPE_LEVEL_LOW
379
+
0x7000 0x0 0x0 0x3 &ipic 18 IRQ_TYPE_LEVEL_LOW
380
+
0x7000 0x0 0x0 0x4 &ipic 18 IRQ_TYPE_LEVEL_LOW
390
381
391
382
/* IDSEL 0x0F -mini PCI */
392
-
0x7800 0x0 0x0 0x1 &ipic 17 0x8
393
-
0x7800 0x0 0x0 0x2 &ipic 17 0x8
394
-
0x7800 0x0 0x0 0x3 &ipic 17 0x8
395
-
0x7800 0x0 0x0 0x4 &ipic 17 0x8
383
+
0x7800 0x0 0x0 0x1 &ipic 17 IRQ_TYPE_LEVEL_LOW
384
+
0x7800 0x0 0x0 0x2 &ipic 17 IRQ_TYPE_LEVEL_LOW
385
+
0x7800 0x0 0x0 0x3 &ipic 17 IRQ_TYPE_LEVEL_LOW
386
+
0x7800 0x0 0x0 0x4 &ipic 17 IRQ_TYPE_LEVEL_LOW
396
387
397
388
/* IDSEL 0x10 - PCI slot */
398
-
0x8000 0x0 0x0 0x1 &ipic 48 0x8
399
-
0x8000 0x0 0x0 0x2 &ipic 17 0x8
400
-
0x8000 0x0 0x0 0x3 &ipic 48 0x8
401
-
0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
389
+
0x8000 0x0 0x0 0x1 &ipic 48 IRQ_TYPE_LEVEL_LOW
390
+
0x8000 0x0 0x0 0x2 &ipic 17 IRQ_TYPE_LEVEL_LOW
391
+
0x8000 0x0 0x0 0x3 &ipic 48 IRQ_TYPE_LEVEL_LOW
392
+
0x8000 0x0 0x0 0x4 &ipic 17 IRQ_TYPE_LEVEL_LOW>;
402
393
interrupt-parent = <&ipic>;
403
-
interrupts = <66 0x8>;
394
+
interrupts = <66 IRQ_TYPE_LEVEL_LOW>;
404
395
bus-range = <0x0 0x0>;
405
396
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
406
397
0x42000000 0 0x80000000 0x80000000 0 0x10000000
···
426
417
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
427
418
bus-range = <0 255>;
428
419
interrupt-map-mask = <0xf800 0 0 7>;
429
-
interrupt-map = <0 0 0 1 &ipic 1 8
430
-
0 0 0 2 &ipic 1 8
431
-
0 0 0 3 &ipic 1 8
432
-
0 0 0 4 &ipic 1 8>;
420
+
interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW
421
+
0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW
422
+
0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW
423
+
0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>;
433
424
clock-frequency = <0>;
434
425
435
426
pcie@0 {
···
457
448
0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
458
449
bus-range = <0 255>;
459
450
interrupt-map-mask = <0xf800 0 0 7>;
460
-
interrupt-map = <0 0 0 1 &ipic 2 8
461
-
0 0 0 2 &ipic 2 8
462
-
0 0 0 3 &ipic 2 8
463
-
0 0 0 4 &ipic 2 8>;
451
+
interrupt-map = <0 0 0 1 &ipic 2 IRQ_TYPE_LEVEL_LOW
452
+
0 0 0 2 &ipic 2 IRQ_TYPE_LEVEL_LOW
453
+
0 0 0 3 &ipic 2 IRQ_TYPE_LEVEL_LOW
454
+
0 0 0 4 &ipic 2 IRQ_TYPE_LEVEL_LOW>;
464
455
clock-frequency = <0>;
465
456
466
457
pcie@0 {
···
480
471
leds {
481
472
compatible = "gpio-leds";
482
473
483
-
pwr {
474
+
led-pwr {
484
475
gpios = <&mcu_pio 0 0>;
485
476
default-state = "on";
486
477
};
487
478
488
-
hdd {
479
+
led-hdd {
489
480
gpios = <&mcu_pio 1 0>;
490
481
linux,default-trigger = "disk-activity";
491
482
};
+1
-1
arch/powerpc/boot/dts/mpc832x_rdb.dts
+1
-1
arch/powerpc/boot/dts/mpc832x_rdb.dts
+1
-1
arch/powerpc/boot/dts/mpc8349emitx.dts
+1
-1
arch/powerpc/boot/dts/mpc8349emitx.dts
+1
-1
arch/powerpc/boot/dts/mpc8349emitxgp.dts
+1
-1
arch/powerpc/boot/dts/mpc8349emitxgp.dts
+1
-1
arch/powerpc/boot/dts/mpc8377_rdb.dts
+1
-1
arch/powerpc/boot/dts/mpc8377_rdb.dts
+1
-1
arch/powerpc/boot/dts/mpc8377_wlan.dts
+1
-1
arch/powerpc/boot/dts/mpc8377_wlan.dts
+1
-1
arch/powerpc/boot/dts/mpc8378_rdb.dts
+1
-1
arch/powerpc/boot/dts/mpc8378_rdb.dts
+1
-1
arch/powerpc/boot/dts/mpc8379_rdb.dts
+1
-1
arch/powerpc/boot/dts/mpc8379_rdb.dts
+1
-3
arch/powerpc/include/asm/nohash/32/pgtable.h
+1
-3
arch/powerpc/include/asm/nohash/32/pgtable.h
···
120
120
121
121
#if defined(CONFIG_44x)
122
122
#include <asm/nohash/32/pte-44x.h>
123
-
#elif defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT)
124
-
#include <asm/nohash/pte-e500.h>
125
123
#elif defined(CONFIG_PPC_85xx)
126
-
#include <asm/nohash/32/pte-85xx.h>
124
+
#include <asm/nohash/pte-e500.h>
127
125
#elif defined(CONFIG_PPC_8xx)
128
126
#include <asm/nohash/32/pte-8xx.h>
129
127
#endif
-59
arch/powerpc/include/asm/nohash/32/pte-85xx.h
-59
arch/powerpc/include/asm/nohash/32/pte-85xx.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
#ifndef _ASM_POWERPC_NOHASH_32_PTE_85xx_H
3
-
#define _ASM_POWERPC_NOHASH_32_PTE_85xx_H
4
-
#ifdef __KERNEL__
5
-
6
-
/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
7
-
* processors
8
-
*
9
-
MMU Assist Register 3:
10
-
11
-
32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
12
-
RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
13
-
14
-
- PRESENT *must* be in the bottom two bits because swap PTEs use
15
-
the top 30 bits.
16
-
17
-
*/
18
-
19
-
/* Definitions for FSL Book-E Cores */
20
-
#define _PAGE_READ 0x00001 /* H: Read permission (SR) */
21
-
#define _PAGE_PRESENT 0x00002 /* S: PTE contains a translation */
22
-
#define _PAGE_WRITE 0x00004 /* S: Write permission (SW) */
23
-
#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
24
-
#define _PAGE_EXEC 0x00010 /* H: SX permission */
25
-
#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
26
-
27
-
#define _PAGE_ENDIAN 0x00040 /* H: E bit */
28
-
#define _PAGE_GUARDED 0x00080 /* H: G bit */
29
-
#define _PAGE_COHERENT 0x00100 /* H: M bit */
30
-
#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
31
-
#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
32
-
#define _PAGE_SPECIAL 0x00800 /* S: Special page */
33
-
34
-
#define _PMD_PRESENT 0
35
-
#define _PMD_PRESENT_MASK (PAGE_MASK)
36
-
#define _PMD_BAD (~PAGE_MASK)
37
-
#define _PMD_USER 0
38
-
39
-
#define _PTE_NONE_MASK 0
40
-
41
-
#define PTE_WIMGE_SHIFT (6)
42
-
43
-
/*
44
-
* We define 2 sets of base prot bits, one for basic pages (ie,
45
-
* cacheable kernel and user pages) and one for non cacheable
46
-
* pages. We always set _PAGE_COHERENT when SMP is enabled or
47
-
* the processor might need it for DMA coherency.
48
-
*/
49
-
#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
50
-
#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
51
-
#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
52
-
#else
53
-
#define _PAGE_BASE (_PAGE_BASE_NC)
54
-
#endif
55
-
56
-
#include <asm/pgtable-masks.h>
57
-
58
-
#endif /* __KERNEL__ */
59
-
#endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_85xx_H */
+1
-1
arch/powerpc/include/asm/pgtable-types.h
+1
-1
arch/powerpc/include/asm/pgtable-types.h
+1
-1
arch/powerpc/include/asm/uaccess.h
+1
-1
arch/powerpc/include/asm/uaccess.h
+1
-45
arch/powerpc/kernel/head_85xx.S
+1
-45
arch/powerpc/kernel/head_85xx.S
···
305
305
* r12 is pointer to the pte
306
306
* r10 is the pshift from the PGD, if we're a hugepage
307
307
*/
308
-
#ifdef CONFIG_PTE_64BIT
309
308
#ifdef CONFIG_HUGETLB_PAGE
310
309
#define FIND_PTE \
311
310
rlwinm r12, r13, 14, 18, 28; /* Compute pgdir/pmd offset */ \
···
328
329
rlwimi r12, r13, 23, 20, 28; /* Compute pte address */ \
329
330
lwz r11, 4(r12); /* Get pte entry */
330
331
#endif /* HUGEPAGE */
331
-
#else /* !PTE_64BIT */
332
-
#define FIND_PTE \
333
-
rlwimi r11, r13, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
334
-
lwz r11, 0(r11); /* Get L1 entry */ \
335
-
rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
336
-
beq 2f; /* Bail if no table */ \
337
-
rlwimi r12, r13, 22, 20, 29; /* Compute PTE address */ \
338
-
lwz r11, 0(r12); /* Get Linux PTE */
339
-
#endif
340
332
341
333
/*
342
334
* Interrupt vector entry code
···
463
473
4:
464
474
FIND_PTE
465
475
466
-
#ifdef CONFIG_PTE_64BIT
467
476
li r13,_PAGE_PRESENT|_PAGE_BAP_SR
468
477
oris r13,r13,_PAGE_ACCESSED@h
469
-
#else
470
-
li r13,_PAGE_PRESENT|_PAGE_READ|_PAGE_ACCESSED
471
-
#endif
472
478
andc. r13,r13,r11 /* Check permission */
473
479
474
-
#ifdef CONFIG_PTE_64BIT
475
480
#ifdef CONFIG_SMP
476
481
subf r13,r11,r12 /* create false data dep */
477
482
lwzx r13,r11,r13 /* Get upper pte bits */
478
483
#else
479
484
lwz r13,0(r12) /* Get upper pte bits */
480
-
#endif
481
485
#endif
482
486
483
487
bne 2f /* Bail if permission/valid mismatch */
···
536
552
537
553
FIND_PTE
538
554
/* Make up the required permissions for kernel code */
539
-
#ifdef CONFIG_PTE_64BIT
540
555
li r13,_PAGE_PRESENT | _PAGE_BAP_SX
541
556
oris r13,r13,_PAGE_ACCESSED@h
542
-
#else
543
-
li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
544
-
#endif
545
557
b 4f
546
558
547
559
/* Get the PGD for the current thread */
···
553
573
554
574
FIND_PTE
555
575
/* Make up the required permissions for user code */
556
-
#ifdef CONFIG_PTE_64BIT
557
576
li r13,_PAGE_PRESENT | _PAGE_BAP_UX
558
577
oris r13,r13,_PAGE_ACCESSED@h
559
-
#else
560
-
li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
561
-
#endif
562
578
563
579
4:
564
580
andc. r13,r13,r11 /* Check permission */
565
581
566
-
#ifdef CONFIG_PTE_64BIT
567
582
#ifdef CONFIG_SMP
568
583
subf r13,r11,r12 /* create false data dep */
569
584
lwzx r13,r11,r13 /* Get upper pte bits */
570
585
#else
571
586
lwz r13,0(r12) /* Get upper pte bits */
572
-
#endif
573
587
#endif
574
588
575
589
bne 2f /* Bail if permission mismatch */
···
657
683
* r10 - tsize encoding (if HUGETLB_PAGE) or available to use
658
684
* r11 - TLB (info from Linux PTE)
659
685
* r12 - available to use
660
-
* r13 - upper bits of PTE (if PTE_64BIT) or available to use
686
+
* r13 - upper bits of PTE
661
687
* CR5 - results of addr >= PAGE_OFFSET
662
688
* MAS0, MAS1 - loaded with proper value when we get here
663
689
* MAS2, MAS3 - will need additional info from Linux PTE
···
725
751
* here we (properly should) assume have the appropriate value.
726
752
*/
727
753
finish_tlb_load_cont:
728
-
#ifdef CONFIG_PTE_64BIT
729
754
rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
730
755
andi. r10, r11, _PAGE_DIRTY
731
756
bne 1f
···
737
764
srwi r10, r13, 12 /* grab RPN[12:31] */
738
765
mtspr SPRN_MAS7, r10
739
766
END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
740
-
#else
741
-
li r10, (_PAGE_EXEC | _PAGE_READ)
742
-
mr r13, r11
743
-
rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
744
-
and r12, r11, r10
745
-
mcrf cr0, cr5 /* Test for user page */
746
-
slwi r10, r12, 1
747
-
or r10, r10, r12
748
-
rlwinm r10, r10, 0, ~_PAGE_EXEC /* Clear SX on user pages */
749
-
isellt r12, r10, r12
750
-
rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
751
-
mtspr SPRN_MAS3, r13
752
-
#endif
753
767
754
768
mfspr r12, SPRN_MAS2
755
-
#ifdef CONFIG_PTE_64BIT
756
769
rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
757
-
#else
758
-
rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
759
-
#endif
760
770
#ifdef CONFIG_HUGETLB_PAGE
761
771
beq 6, 3f /* don't mask if page isn't huge */
762
772
li r13, 1
+2
-1
arch/powerpc/kernel/prom_init.c
+2
-1
arch/powerpc/kernel/prom_init.c
···
2893
2893
for (node = 0; prom_next_node(&node); ) {
2894
2894
type[0] = '\0';
2895
2895
prom_getprop(node, "device_type", type, sizeof(type));
2896
-
if (prom_strcmp(type, "escc") && prom_strcmp(type, "i2s"))
2896
+
if (prom_strcmp(type, "escc") && prom_strcmp(type, "i2s") &&
2897
+
prom_strcmp(type, "media-bay"))
2897
2898
continue;
2898
2899
2899
2900
if (prom_getproplen(node, "#size-cells") != PROM_ERROR)
+22
-4
arch/powerpc/kernel/trace/ftrace.c
+22
-4
arch/powerpc/kernel/trace/ftrace.c
···
37
37
if (addr >= (unsigned long)__exittext_begin && addr < (unsigned long)__exittext_end)
38
38
return 0;
39
39
40
-
if (IS_ENABLED(CONFIG_ARCH_USING_PATCHABLE_FUNCTION_ENTRY) &&
41
-
!IS_ENABLED(CONFIG_PPC_FTRACE_OUT_OF_LINE)) {
42
-
addr += MCOUNT_INSN_SIZE;
43
-
if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS))
40
+
if (IS_ENABLED(CONFIG_ARCH_USING_PATCHABLE_FUNCTION_ENTRY)) {
41
+
if (!IS_ENABLED(CONFIG_PPC_FTRACE_OUT_OF_LINE)) {
44
42
addr += MCOUNT_INSN_SIZE;
43
+
if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_CALL_OPS))
44
+
addr += MCOUNT_INSN_SIZE;
45
+
} else if (IS_ENABLED(CONFIG_CC_IS_CLANG) && IS_ENABLED(CONFIG_PPC64)) {
46
+
/*
47
+
* addr points to global entry point though the NOP was emitted at local
48
+
* entry point due to https://github.com/llvm/llvm-project/issues/163706
49
+
* Handle that here with ppc_function_entry() for kernel symbols while
50
+
* adjusting module addresses in the else case, by looking for the below
51
+
* module global entry point sequence:
52
+
* ld r2, -8(r12)
53
+
* add r2, r2, r12
54
+
*/
55
+
if (is_kernel_text(addr) || is_kernel_inittext(addr))
56
+
addr = ppc_function_entry((void *)addr);
57
+
else if ((ppc_inst_val(ppc_inst_read((u32 *)addr)) ==
58
+
PPC_RAW_LD(_R2, _R12, -8)) &&
59
+
(ppc_inst_val(ppc_inst_read((u32 *)(addr+4))) ==
60
+
PPC_RAW_ADD(_R2, _R2, _R12)))
61
+
addr += 8;
62
+
}
45
63
}
46
64
47
65
return addr;
+9
-8
arch/powerpc/kexec/core.c
+9
-8
arch/powerpc/kexec/core.c
···
23
23
#include <asm/firmware.h>
24
24
25
25
#define cpu_to_be_ulong __PASTE(cpu_to_be, BITS_PER_LONG)
26
+
#define __be_word __PASTE(__be, BITS_PER_LONG)
26
27
27
28
#ifdef CONFIG_CRASH_DUMP
28
29
void machine_crash_shutdown(struct pt_regs *regs)
···
147
146
}
148
147
149
148
/* Values we need to export to the second kernel via the device tree. */
150
-
static phys_addr_t crashk_base;
151
-
static phys_addr_t crashk_size;
152
-
static unsigned long long mem_limit;
149
+
static __be_word crashk_base;
150
+
static __be_word crashk_size;
151
+
static __be_word mem_limit;
153
152
154
153
static struct property crashk_base_prop = {
155
154
.name = "linux,crashkernel-base",
156
-
.length = sizeof(phys_addr_t),
155
+
.length = sizeof(__be_word),
157
156
.value = &crashk_base
158
157
};
159
158
160
159
static struct property crashk_size_prop = {
161
160
.name = "linux,crashkernel-size",
162
-
.length = sizeof(phys_addr_t),
161
+
.length = sizeof(__be_word),
163
162
.value = &crashk_size,
164
163
};
165
164
166
165
static struct property memory_limit_prop = {
167
166
.name = "linux,memory-limit",
168
-
.length = sizeof(unsigned long long),
167
+
.length = sizeof(__be_word),
169
168
.value = &mem_limit,
170
169
};
171
170
···
194
193
}
195
194
#endif /* CONFIG_CRASH_RESERVE */
196
195
197
-
static phys_addr_t kernel_end;
196
+
static __be_word kernel_end;
198
197
199
198
static struct property kernel_end_prop = {
200
199
.name = "linux,kernel-end",
201
-
.length = sizeof(phys_addr_t),
200
+
.length = sizeof(__be_word),
202
201
.value = &kernel_end,
203
202
};
204
203
+13
-1
arch/powerpc/kexec/file_load_64.c
+13
-1
arch/powerpc/kexec/file_load_64.c
···
450
450
kbuf->buffer = headers;
451
451
kbuf->mem = KEXEC_BUF_MEM_UNKNOWN;
452
452
kbuf->bufsz = headers_sz;
453
+
454
+
/*
455
+
* Account for extra space required to accommodate additional memory
456
+
* ranges in elfcorehdr due to memory hotplug events.
457
+
*/
453
458
kbuf->memsz = headers_sz + kdump_extra_elfcorehdr_size(cmem);
454
459
kbuf->top_down = false;
455
460
···
465
460
}
466
461
467
462
image->elf_load_addr = kbuf->mem;
468
-
image->elf_headers_sz = headers_sz;
463
+
464
+
/*
465
+
* If CONFIG_CRASH_HOTPLUG is enabled, the elfcorehdr kexec segment
466
+
* memsz can be larger than bufsz. Always initialize elf_headers_sz
467
+
* with memsz. This ensures the correct size is reserved for elfcorehdr
468
+
* memory in the FDT prepared for kdump.
469
+
*/
470
+
image->elf_headers_sz = kbuf->memsz;
469
471
image->elf_headers = headers;
470
472
out:
471
473
kfree(cmem);
-5
arch/powerpc/net/bpf_jit.h
-5
arch/powerpc/net/bpf_jit.h
···
81
81
82
82
#ifdef CONFIG_PPC64
83
83
84
-
/* for gpr non volatile registers BPG_REG_6 to 10 */
85
-
#define BPF_PPC_STACK_SAVE (6 * 8)
86
-
87
84
/* If dummy pass (!image), account for maximum possible instructions */
88
85
#define PPC_LI64(d, i) do { \
89
86
if (!image) \
···
216
219
int bpf_add_extable_entry(struct bpf_prog *fp, u32 *image, u32 *fimage, int pass,
217
220
struct codegen_context *ctx, int insn_idx,
218
221
int jmp_off, int dst_reg, u32 code);
219
-
220
-
int bpf_jit_stack_tailcallinfo_offset(struct codegen_context *ctx);
221
222
#endif
222
223
223
224
#endif
+56
-71
arch/powerpc/net/bpf_jit_comp.c
+56
-71
arch/powerpc/net/bpf_jit_comp.c
···
450
450
451
451
bool bpf_jit_supports_kfunc_call(void)
452
452
{
453
-
return true;
453
+
return IS_ENABLED(CONFIG_PPC64);
454
454
}
455
455
456
456
bool bpf_jit_supports_arena(void)
···
638
638
* for the traced function (BPF subprog/callee) to fetch it.
639
639
*/
640
640
static void bpf_trampoline_setup_tail_call_info(u32 *image, struct codegen_context *ctx,
641
-
int func_frame_offset,
642
-
int bpf_dummy_frame_size, int r4_off)
641
+
int bpf_frame_size, int r4_off)
643
642
{
644
643
if (IS_ENABLED(CONFIG_PPC64)) {
645
-
/* See Generated stack layout */
646
-
int tailcallinfo_offset = BPF_PPC_TAILCALL;
647
-
648
-
/*
649
-
* func_frame_offset = ...(1)
650
-
* bpf_dummy_frame_size + trampoline_frame_size
651
-
*/
652
-
EMIT(PPC_RAW_LD(_R4, _R1, func_frame_offset));
653
-
EMIT(PPC_RAW_LD(_R3, _R4, -tailcallinfo_offset));
644
+
EMIT(PPC_RAW_LD(_R4, _R1, bpf_frame_size));
645
+
/* Refer to trampoline's Generated stack layout */
646
+
EMIT(PPC_RAW_LD(_R3, _R4, -BPF_PPC_TAILCALL));
654
647
655
648
/*
656
649
* Setting the tail_call_info in trampoline's frame
···
651
658
*/
652
659
EMIT(PPC_RAW_CMPLWI(_R3, MAX_TAIL_CALL_CNT));
653
660
PPC_BCC_CONST_SHORT(COND_GT, 8);
654
-
EMIT(PPC_RAW_ADDI(_R3, _R4, bpf_jit_stack_tailcallinfo_offset(ctx)));
661
+
EMIT(PPC_RAW_ADDI(_R3, _R4, -BPF_PPC_TAILCALL));
662
+
655
663
/*
656
-
* From ...(1) above:
657
-
* trampoline_frame_bottom = ...(2)
658
-
* func_frame_offset - bpf_dummy_frame_size
659
-
*
660
-
* Using ...(2) derived above:
661
-
* trampoline_tail_call_info_offset = ...(3)
662
-
* trampoline_frame_bottom - tailcallinfo_offset
663
-
*
664
-
* From ...(3):
665
-
* Use trampoline_tail_call_info_offset to write reference of main's
666
-
* tail_call_info in trampoline frame.
664
+
* Trampoline's tail_call_info is at the same offset, as that of
665
+
* any bpf program, with reference to previous frame. Update the
666
+
* address of main's tail_call_info in trampoline frame.
667
667
*/
668
-
EMIT(PPC_RAW_STL(_R3, _R1, (func_frame_offset - bpf_dummy_frame_size)
669
-
- tailcallinfo_offset));
668
+
EMIT(PPC_RAW_STL(_R3, _R1, bpf_frame_size - BPF_PPC_TAILCALL));
670
669
} else {
671
670
/* See bpf_jit_stack_offsetof() and BPF_PPC_TC */
672
671
EMIT(PPC_RAW_LL(_R4, _R1, r4_off));
···
666
681
}
667
682
668
683
static void bpf_trampoline_restore_tail_call_cnt(u32 *image, struct codegen_context *ctx,
669
-
int func_frame_offset, int r4_off)
684
+
int bpf_frame_size, int r4_off)
670
685
{
671
686
if (IS_ENABLED(CONFIG_PPC32)) {
672
687
/*
···
677
692
}
678
693
}
679
694
680
-
static void bpf_trampoline_save_args(u32 *image, struct codegen_context *ctx, int func_frame_offset,
681
-
int nr_regs, int regs_off)
695
+
static void bpf_trampoline_save_args(u32 *image, struct codegen_context *ctx,
696
+
int bpf_frame_size, int nr_regs, int regs_off)
682
697
{
683
698
int param_save_area_offset;
684
699
685
-
param_save_area_offset = func_frame_offset; /* the two frames we alloted */
700
+
param_save_area_offset = bpf_frame_size;
686
701
param_save_area_offset += STACK_FRAME_MIN_SIZE; /* param save area is past frame header */
687
702
688
703
for (int i = 0; i < nr_regs; i++) {
···
705
720
706
721
/* Used when we call into the traced function. Replicate parameter save area */
707
722
static void bpf_trampoline_restore_args_stack(u32 *image, struct codegen_context *ctx,
708
-
int func_frame_offset, int nr_regs, int regs_off)
723
+
int bpf_frame_size, int nr_regs, int regs_off)
709
724
{
710
725
int param_save_area_offset;
711
726
712
-
param_save_area_offset = func_frame_offset; /* the two frames we alloted */
727
+
param_save_area_offset = bpf_frame_size;
713
728
param_save_area_offset += STACK_FRAME_MIN_SIZE; /* param save area is past frame header */
714
729
715
730
for (int i = 8; i < nr_regs; i++) {
···
726
741
void *func_addr)
727
742
{
728
743
int regs_off, nregs_off, ip_off, run_ctx_off, retval_off, nvr_off, alt_lr_off, r4_off = 0;
729
-
int i, ret, nr_regs, bpf_frame_size = 0, bpf_dummy_frame_size = 0, func_frame_offset;
730
744
struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
731
745
struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
732
746
struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
747
+
int i, ret, nr_regs, retaddr_off, bpf_frame_size = 0;
733
748
struct codegen_context codegen_ctx, *ctx;
734
749
u32 *image = (u32 *)rw_image;
735
750
ppc_inst_t branch_insn;
···
755
770
* Generated stack layout:
756
771
*
757
772
* func prev back chain [ back chain ]
758
-
* [ ]
759
-
* bpf prog redzone/tailcallcnt [ ... ] 64 bytes (64-bit powerpc)
760
-
* [ ] --
761
-
* LR save area [ r0 save (64-bit) ] | header
762
-
* [ r0 save (32-bit) ] |
763
-
* dummy frame for unwind [ back chain 1 ] --
764
773
* [ tail_call_info ] optional - 64-bit powerpc
765
774
* [ padding ] align stack frame
766
775
* r4_off [ r4 (tailcallcnt) ] optional - 32-bit powerpc
767
776
* alt_lr_off [ real lr (ool stub)] optional - actual lr
777
+
* retaddr_off [ return address ]
768
778
* [ r26 ]
769
779
* nvr_off [ r25 ] nvr save area
770
780
* retval_off [ return value ]
771
781
* [ reg argN ]
772
782
* [ ... ]
773
-
* regs_off [ reg_arg1 ] prog ctx context
774
-
* nregs_off [ args count ]
775
-
* ip_off [ traced function ]
783
+
* regs_off [ reg_arg1 ] prog_ctx
784
+
* nregs_off [ args count ] ((u64 *)prog_ctx)[-1]
785
+
* ip_off [ traced function ] ((u64 *)prog_ctx)[-2]
776
786
* [ ... ]
777
787
* run_ctx_off [ bpf_tramp_run_ctx ]
778
788
* [ reg argN ]
···
823
843
nvr_off = bpf_frame_size;
824
844
bpf_frame_size += 2 * SZL;
825
845
846
+
/* Save area for return address */
847
+
retaddr_off = bpf_frame_size;
848
+
bpf_frame_size += SZL;
849
+
826
850
/* Optional save area for actual LR in case of ool ftrace */
827
851
if (IS_ENABLED(CONFIG_PPC_FTRACE_OUT_OF_LINE)) {
828
852
alt_lr_off = bpf_frame_size;
···
853
869
/* Padding to align stack frame, if any */
854
870
bpf_frame_size = round_up(bpf_frame_size, SZL * 2);
855
871
856
-
/* Dummy frame size for proper unwind - includes 64-bytes red zone for 64-bit powerpc */
857
-
bpf_dummy_frame_size = STACK_FRAME_MIN_SIZE + 64;
858
-
859
-
/* Offset to the traced function's stack frame */
860
-
func_frame_offset = bpf_dummy_frame_size + bpf_frame_size;
861
-
862
-
/* Create dummy frame for unwind, store original return value */
872
+
/* Store original return value */
863
873
EMIT(PPC_RAW_STL(_R0, _R1, PPC_LR_STKOFF));
864
-
/* Protect red zone where tail call count goes */
865
-
EMIT(PPC_RAW_STLU(_R1, _R1, -bpf_dummy_frame_size));
866
874
867
875
/* Create our stack frame */
868
876
EMIT(PPC_RAW_STLU(_R1, _R1, -bpf_frame_size));
···
869
893
if (IS_ENABLED(CONFIG_PPC32) && nr_regs < 2)
870
894
EMIT(PPC_RAW_STL(_R4, _R1, r4_off));
871
895
872
-
bpf_trampoline_save_args(image, ctx, func_frame_offset, nr_regs, regs_off);
896
+
bpf_trampoline_save_args(image, ctx, bpf_frame_size, nr_regs, regs_off);
873
897
874
-
/* Save our return address */
898
+
/* Save our LR/return address */
875
899
EMIT(PPC_RAW_MFLR(_R3));
876
900
if (IS_ENABLED(CONFIG_PPC_FTRACE_OUT_OF_LINE))
877
901
EMIT(PPC_RAW_STL(_R3, _R1, alt_lr_off));
878
902
else
879
-
EMIT(PPC_RAW_STL(_R3, _R1, bpf_frame_size + PPC_LR_STKOFF));
903
+
EMIT(PPC_RAW_STL(_R3, _R1, retaddr_off));
880
904
881
905
/*
882
-
* Save ip address of the traced function.
883
-
* We could recover this from LR, but we will need to address for OOL trampoline,
884
-
* and optional GEP area.
906
+
* Derive IP address of the traced function.
907
+
* In case of CONFIG_PPC_FTRACE_OUT_OF_LINE or BPF program, LR points to the instruction
908
+
* after the 'bl' instruction in the OOL stub. Refer to ftrace_init_ool_stub() and
909
+
* bpf_arch_text_poke() for OOL stub of kernel functions and bpf programs respectively.
910
+
* Relevant stub sequence:
911
+
*
912
+
* bl <tramp>
913
+
* LR (R3) => mtlr r0
914
+
* b <func_addr+4>
915
+
*
916
+
* Recover kernel function/bpf program address from the unconditional
917
+
* branch instruction at the end of OOL stub.
885
918
*/
886
919
if (IS_ENABLED(CONFIG_PPC_FTRACE_OUT_OF_LINE) || flags & BPF_TRAMP_F_IP_ARG) {
887
920
EMIT(PPC_RAW_LWZ(_R4, _R3, 4));
888
921
EMIT(PPC_RAW_SLWI(_R4, _R4, 6));
889
922
EMIT(PPC_RAW_SRAWI(_R4, _R4, 6));
890
923
EMIT(PPC_RAW_ADD(_R3, _R3, _R4));
891
-
EMIT(PPC_RAW_ADDI(_R3, _R3, 4));
892
924
}
893
925
894
926
if (flags & BPF_TRAMP_F_IP_ARG)
895
927
EMIT(PPC_RAW_STL(_R3, _R1, ip_off));
896
928
897
-
if (IS_ENABLED(CONFIG_PPC_FTRACE_OUT_OF_LINE))
898
-
/* Fake our LR for unwind */
899
-
EMIT(PPC_RAW_STL(_R3, _R1, bpf_frame_size + PPC_LR_STKOFF));
929
+
if (IS_ENABLED(CONFIG_PPC_FTRACE_OUT_OF_LINE)) {
930
+
/* Fake our LR for BPF_TRAMP_F_CALL_ORIG case */
931
+
EMIT(PPC_RAW_ADDI(_R3, _R3, 4));
932
+
EMIT(PPC_RAW_STL(_R3, _R1, retaddr_off));
933
+
}
900
934
901
935
/* Save function arg count -- see bpf_get_func_arg_cnt() */
902
936
EMIT(PPC_RAW_LI(_R3, nr_regs));
···
944
958
/* Call the traced function */
945
959
if (flags & BPF_TRAMP_F_CALL_ORIG) {
946
960
/*
947
-
* The address in LR save area points to the correct point in the original function
961
+
* retaddr on trampoline stack points to the correct point in the original function
948
962
* with both PPC_FTRACE_OUT_OF_LINE as well as with traditional ftrace instruction
949
963
* sequence
950
964
*/
951
-
EMIT(PPC_RAW_LL(_R3, _R1, bpf_frame_size + PPC_LR_STKOFF));
965
+
EMIT(PPC_RAW_LL(_R3, _R1, retaddr_off));
952
966
EMIT(PPC_RAW_MTCTR(_R3));
953
967
954
968
/* Replicate tail_call_cnt before calling the original BPF prog */
955
969
if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
956
-
bpf_trampoline_setup_tail_call_info(image, ctx, func_frame_offset,
957
-
bpf_dummy_frame_size, r4_off);
970
+
bpf_trampoline_setup_tail_call_info(image, ctx, bpf_frame_size, r4_off);
958
971
959
972
/* Restore args */
960
-
bpf_trampoline_restore_args_stack(image, ctx, func_frame_offset, nr_regs, regs_off);
973
+
bpf_trampoline_restore_args_stack(image, ctx, bpf_frame_size, nr_regs, regs_off);
961
974
962
975
/* Restore TOC for 64-bit */
963
976
if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V2) && !IS_ENABLED(CONFIG_PPC_KERNEL_PCREL))
···
970
985
971
986
/* Restore updated tail_call_cnt */
972
987
if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
973
-
bpf_trampoline_restore_tail_call_cnt(image, ctx, func_frame_offset, r4_off);
988
+
bpf_trampoline_restore_tail_call_cnt(image, ctx, bpf_frame_size, r4_off);
974
989
975
990
/* Reserve space to patch branch instruction to skip fexit progs */
976
991
if (ro_image) /* image is NULL for dummy pass */
···
1022
1037
EMIT(PPC_RAW_LD(_R2, _R1, 24));
1023
1038
if (flags & BPF_TRAMP_F_SKIP_FRAME) {
1024
1039
/* Skip the traced function and return to parent */
1025
-
EMIT(PPC_RAW_ADDI(_R1, _R1, func_frame_offset));
1040
+
EMIT(PPC_RAW_ADDI(_R1, _R1, bpf_frame_size));
1026
1041
EMIT(PPC_RAW_LL(_R0, _R1, PPC_LR_STKOFF));
1027
1042
EMIT(PPC_RAW_MTLR(_R0));
1028
1043
EMIT(PPC_RAW_BLR());
···
1030
1045
if (IS_ENABLED(CONFIG_PPC_FTRACE_OUT_OF_LINE)) {
1031
1046
EMIT(PPC_RAW_LL(_R0, _R1, alt_lr_off));
1032
1047
EMIT(PPC_RAW_MTLR(_R0));
1033
-
EMIT(PPC_RAW_ADDI(_R1, _R1, func_frame_offset));
1048
+
EMIT(PPC_RAW_ADDI(_R1, _R1, bpf_frame_size));
1034
1049
EMIT(PPC_RAW_LL(_R0, _R1, PPC_LR_STKOFF));
1035
1050
EMIT(PPC_RAW_BLR());
1036
1051
} else {
1037
-
EMIT(PPC_RAW_LL(_R0, _R1, bpf_frame_size + PPC_LR_STKOFF));
1052
+
EMIT(PPC_RAW_LL(_R0, _R1, retaddr_off));
1038
1053
EMIT(PPC_RAW_MTCTR(_R0));
1039
-
EMIT(PPC_RAW_ADDI(_R1, _R1, func_frame_offset));
1054
+
EMIT(PPC_RAW_ADDI(_R1, _R1, bpf_frame_size));
1040
1055
EMIT(PPC_RAW_LL(_R0, _R1, PPC_LR_STKOFF));
1041
1056
EMIT(PPC_RAW_MTLR(_R0));
1042
1057
EMIT(PPC_RAW_BCTR());
+143
-38
arch/powerpc/net/bpf_jit_comp64.c
+143
-38
arch/powerpc/net/bpf_jit_comp64.c
···
32
32
*
33
33
* [ prev sp ] <-------------
34
34
* [ tail_call_info ] 8 |
35
-
* [ nv gpr save area ] 6*8 + (12*8) |
35
+
* [ nv gpr save area ] (6 * 8) |
36
+
* [ addl. nv gpr save area] (12 * 8) | <--- exception boundary/callback program
36
37
* [ local_tmp_var ] 24 |
37
38
* fp (r31) --> [ ebpf stack space ] upto 512 |
38
39
* [ frame header ] 32/112 |
39
40
* sp (r1) ---> [ stack pointer ] --------------
40
41
*
41
-
* Additional (12*8) in 'nv gpr save area' only in case of
42
-
* exception boundary.
42
+
* Additional (12 * 8) in 'nv gpr save area' only in case of
43
+
* exception boundary/callback.
43
44
*/
45
+
46
+
/* BPF non-volatile registers save area size */
47
+
#define BPF_PPC_STACK_SAVE (6 * 8)
44
48
45
49
/* for bpf JIT code internal usage */
46
50
#define BPF_PPC_STACK_LOCALS 24
···
52
48
* for additional non volatile registers(r14-r25) to be saved
53
49
* at exception boundary
54
50
*/
55
-
#define BPF_PPC_EXC_STACK_SAVE (12*8)
51
+
#define BPF_PPC_EXC_STACK_SAVE (12 * 8)
56
52
57
53
/* stack frame excluding BPF stack, ensure this is quadword aligned */
58
54
#define BPF_PPC_STACKFRAME (STACK_FRAME_MIN_SIZE + \
···
129
125
* [ ... ] |
130
126
* sp (r1) ---> [ stack pointer ] --------------
131
127
* [ tail_call_info ] 8
132
-
* [ nv gpr save area ] 6*8 + (12*8)
128
+
* [ nv gpr save area ] (6 * 8)
129
+
* [ addl. nv gpr save area] (12 * 8) <--- exception boundary/callback program
133
130
* [ local_tmp_var ] 24
134
131
* [ unused red zone ] 224
135
132
*
136
-
* Additional (12*8) in 'nv gpr save area' only in case of
137
-
* exception boundary.
133
+
* Additional (12 * 8) in 'nv gpr save area' only in case of
134
+
* exception boundary/callback.
138
135
*/
139
136
static int bpf_jit_stack_local(struct codegen_context *ctx)
140
137
{
···
153
148
}
154
149
}
155
150
156
-
int bpf_jit_stack_tailcallinfo_offset(struct codegen_context *ctx)
151
+
static int bpf_jit_stack_tailcallinfo_offset(struct codegen_context *ctx)
157
152
{
158
153
return bpf_jit_stack_local(ctx) + BPF_PPC_STACK_LOCALS + BPF_PPC_STACK_SAVE;
159
154
}
···
242
237
243
238
if (bpf_has_stack_frame(ctx) && !ctx->exception_cb) {
244
239
/*
245
-
* exception_cb uses boundary frame after stack walk.
246
-
* It can simply use redzone, this optimization reduces
247
-
* stack walk loop by one level.
248
-
*
249
240
* We need a stack frame, but we don't necessarily need to
250
241
* save/restore LR unless we call other functions
251
242
*/
···
285
284
* program(main prog) as third arg
286
285
*/
287
286
EMIT(PPC_RAW_MR(_R1, _R5));
287
+
/*
288
+
* Exception callback reuses the stack frame of exception boundary.
289
+
* But BPF stack depth of exception callback and exception boundary
290
+
* don't have to be same. If BPF stack depth is different, adjust the
291
+
* stack frame size considering BPF stack depth of exception callback.
292
+
* The non-volatile register save area remains unchanged. These non-
293
+
* volatile registers are restored in exception callback's epilogue.
294
+
*/
295
+
EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), _R5, 0));
296
+
EMIT(PPC_RAW_SUB(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_1), _R1));
297
+
EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2),
298
+
-BPF_PPC_EXC_STACKFRAME));
299
+
EMIT(PPC_RAW_CMPLDI(bpf_to_ppc(TMP_REG_2), ctx->stack_size));
300
+
PPC_BCC_CONST_SHORT(COND_EQ, 12);
301
+
EMIT(PPC_RAW_MR(_R1, bpf_to_ppc(TMP_REG_1)));
302
+
EMIT(PPC_RAW_STDU(_R1, _R1, -(BPF_PPC_EXC_STACKFRAME + ctx->stack_size)));
288
303
}
289
304
290
305
/*
···
499
482
return 0;
500
483
}
501
484
485
+
static int zero_extend(u32 *image, struct codegen_context *ctx, u32 src_reg, u32 dst_reg, u32 size)
486
+
{
487
+
switch (size) {
488
+
case 1:
489
+
/* zero-extend 8 bits into 64 bits */
490
+
EMIT(PPC_RAW_RLDICL(dst_reg, src_reg, 0, 56));
491
+
return 0;
492
+
case 2:
493
+
/* zero-extend 16 bits into 64 bits */
494
+
EMIT(PPC_RAW_RLDICL(dst_reg, src_reg, 0, 48));
495
+
return 0;
496
+
case 4:
497
+
/* zero-extend 32 bits into 64 bits */
498
+
EMIT(PPC_RAW_RLDICL(dst_reg, src_reg, 0, 32));
499
+
fallthrough;
500
+
case 8:
501
+
/* Nothing to do */
502
+
return 0;
503
+
default:
504
+
return -1;
505
+
}
506
+
}
507
+
508
+
static int sign_extend(u32 *image, struct codegen_context *ctx, u32 src_reg, u32 dst_reg, u32 size)
509
+
{
510
+
switch (size) {
511
+
case 1:
512
+
/* sign-extend 8 bits into 64 bits */
513
+
EMIT(PPC_RAW_EXTSB(dst_reg, src_reg));
514
+
return 0;
515
+
case 2:
516
+
/* sign-extend 16 bits into 64 bits */
517
+
EMIT(PPC_RAW_EXTSH(dst_reg, src_reg));
518
+
return 0;
519
+
case 4:
520
+
/* sign-extend 32 bits into 64 bits */
521
+
EMIT(PPC_RAW_EXTSW(dst_reg, src_reg));
522
+
fallthrough;
523
+
case 8:
524
+
/* Nothing to do */
525
+
return 0;
526
+
default:
527
+
return -1;
528
+
}
529
+
}
530
+
531
+
/*
532
+
* Handle powerpc ABI expectations from caller:
533
+
* - Unsigned arguments are zero-extended.
534
+
* - Signed arguments are sign-extended.
535
+
*/
536
+
static int prepare_for_kfunc_call(const struct bpf_prog *fp, u32 *image,
537
+
struct codegen_context *ctx,
538
+
const struct bpf_insn *insn)
539
+
{
540
+
const struct btf_func_model *m = bpf_jit_find_kfunc_model(fp, insn);
541
+
int i;
542
+
543
+
if (!m)
544
+
return -1;
545
+
546
+
for (i = 0; i < m->nr_args; i++) {
547
+
/* Note that BPF ABI only allows up to 5 args for kfuncs */
548
+
u32 reg = bpf_to_ppc(BPF_REG_1 + i), size = m->arg_size[i];
549
+
550
+
if (!(m->arg_flags[i] & BTF_FMODEL_SIGNED_ARG)) {
551
+
if (zero_extend(image, ctx, reg, reg, size))
552
+
return -1;
553
+
} else {
554
+
if (sign_extend(image, ctx, reg, reg, size))
555
+
return -1;
556
+
}
557
+
}
558
+
559
+
return 0;
560
+
}
561
+
502
562
static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
503
563
{
504
564
/*
···
616
522
617
523
/*
618
524
* tail_call_info++; <- Actual value of tcc here
525
+
* Writeback this updated value only if tailcall succeeds.
619
526
*/
620
527
EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), 1));
528
+
529
+
/* prog = array->ptrs[index]; */
530
+
EMIT(PPC_RAW_MULI(bpf_to_ppc(TMP_REG_2), b2p_index, 8));
531
+
EMIT(PPC_RAW_ADD(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2), b2p_bpf_array));
532
+
EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2),
533
+
offsetof(struct bpf_array, ptrs)));
534
+
535
+
/*
536
+
* if (prog == NULL)
537
+
* goto out;
538
+
*/
539
+
EMIT(PPC_RAW_CMPLDI(bpf_to_ppc(TMP_REG_2), 0));
540
+
PPC_BCC_SHORT(COND_EQ, out);
541
+
542
+
/* goto *(prog->bpf_func + prologue_size); */
543
+
EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2),
544
+
offsetof(struct bpf_prog, bpf_func)));
545
+
EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_2), bpf_to_ppc(TMP_REG_2),
546
+
FUNCTION_DESCR_SIZE + bpf_tailcall_prologue_size));
547
+
EMIT(PPC_RAW_MTCTR(bpf_to_ppc(TMP_REG_2)));
621
548
622
549
/*
623
550
* Before writing updated tail_call_info, distinguish if current frame
···
653
538
EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_2), _R1, bpf_jit_stack_tailcallinfo_offset(ctx)));
654
539
/* Writeback updated value to tail_call_info */
655
540
EMIT(PPC_RAW_STD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_2), 0));
656
-
657
-
/* prog = array->ptrs[index]; */
658
-
EMIT(PPC_RAW_MULI(bpf_to_ppc(TMP_REG_1), b2p_index, 8));
659
-
EMIT(PPC_RAW_ADD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), b2p_bpf_array));
660
-
EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), offsetof(struct bpf_array, ptrs)));
661
-
662
-
/*
663
-
* if (prog == NULL)
664
-
* goto out;
665
-
*/
666
-
EMIT(PPC_RAW_CMPLDI(bpf_to_ppc(TMP_REG_1), 0));
667
-
PPC_BCC_SHORT(COND_EQ, out);
668
-
669
-
/* goto *(prog->bpf_func + prologue_size); */
670
-
EMIT(PPC_RAW_LD(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1), offsetof(struct bpf_prog, bpf_func)));
671
-
EMIT(PPC_RAW_ADDI(bpf_to_ppc(TMP_REG_1), bpf_to_ppc(TMP_REG_1),
672
-
FUNCTION_DESCR_SIZE + bpf_tailcall_prologue_size));
673
-
EMIT(PPC_RAW_MTCTR(bpf_to_ppc(TMP_REG_1)));
674
541
675
542
/* tear down stack, restore NVRs, ... */
676
543
bpf_jit_emit_common_epilogue(image, ctx);
···
1220
1123
/* special mov32 for zext */
1221
1124
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 0, 31));
1222
1125
break;
1223
-
} else if (off == 8) {
1224
-
EMIT(PPC_RAW_EXTSB(dst_reg, src_reg));
1225
-
} else if (off == 16) {
1226
-
EMIT(PPC_RAW_EXTSH(dst_reg, src_reg));
1227
-
} else if (off == 32) {
1228
-
EMIT(PPC_RAW_EXTSW(dst_reg, src_reg));
1229
-
} else if (dst_reg != src_reg)
1230
-
EMIT(PPC_RAW_MR(dst_reg, src_reg));
1126
+
}
1127
+
if (off == 0) {
1128
+
/* MOV */
1129
+
if (dst_reg != src_reg)
1130
+
EMIT(PPC_RAW_MR(dst_reg, src_reg));
1131
+
} else {
1132
+
/* MOVSX: dst = (s8,s16,s32)src (off = 8,16,32) */
1133
+
if (sign_extend(image, ctx, src_reg, dst_reg, off / 8))
1134
+
return -1;
1135
+
}
1231
1136
goto bpf_alu32_trunc;
1232
1137
case BPF_ALU | BPF_MOV | BPF_K: /* (u32) dst = imm */
1233
1138
case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = (s64) imm */
···
1696
1597
&func_addr, &func_addr_fixed);
1697
1598
if (ret < 0)
1698
1599
return ret;
1600
+
1601
+
/* Take care of powerpc ABI requirements before kfunc call */
1602
+
if (insn[i].src_reg == BPF_PSEUDO_KFUNC_CALL) {
1603
+
if (prepare_for_kfunc_call(fp, image, ctx, &insn[i]))
1604
+
return -1;
1605
+
}
1699
1606
1700
1607
ret = bpf_jit_emit_func_call_rel(image, fimage, ctx, func_addr);
1701
1608
if (ret)
+2
-2
arch/powerpc/platforms/83xx/km83xx.c
+2
-2
arch/powerpc/platforms/83xx/km83xx.c
+2
-2
arch/powerpc/platforms/Kconfig.cputype
+2
-2
arch/powerpc/platforms/Kconfig.cputype
···
276
276
config PPC_E500
277
277
select FSL_EMB_PERFMON
278
278
bool
279
-
select ARCH_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64
279
+
select ARCH_SUPPORTS_HUGETLBFS
280
280
select PPC_SMP_MUXED_IPI
281
281
select PPC_DOORBELL
282
282
select PPC_KUEP
···
337
337
config PTE_64BIT
338
338
bool
339
339
depends on 44x || PPC_E500 || PPC_86xx
340
-
default y if PHYS_64BIT
340
+
default y if PPC_E500 || PHYS_64BIT
341
341
342
342
config PHYS_64BIT
343
343
bool 'Large physical address support' if PPC_E500 || PPC_86xx
+1
-1
arch/powerpc/platforms/pseries/msi.c
+1
-1
arch/powerpc/platforms/pseries/msi.c
+2
-2
arch/powerpc/tools/ftrace-gen-ool-stubs.sh
+2
-2
arch/powerpc/tools/ftrace-gen-ool-stubs.sh
···
15
15
RELOCATION=R_PPC_ADDR32
16
16
fi
17
17
18
-
num_ool_stubs_total=$($objdump -r -j __patchable_function_entries "$vmlinux_o" |
18
+
num_ool_stubs_total=$($objdump -r -j __patchable_function_entries -d "$vmlinux_o" |
19
19
grep -c "$RELOCATION")
20
-
num_ool_stubs_inittext=$($objdump -r -j __patchable_function_entries "$vmlinux_o" |
20
+
num_ool_stubs_inittext=$($objdump -r -j __patchable_function_entries -d "$vmlinux_o" |
21
21
grep -e ".init.text" -e ".text.startup" | grep -c "$RELOCATION")
22
22
num_ool_stubs_text=$((num_ool_stubs_total - num_ool_stubs_inittext))
23
23
arch/powerpc/tools/gcc-check-fpatchable-function-entry.sh
arch/powerpc/tools/check-fpatchable-function-entry.sh
arch/powerpc/tools/gcc-check-fpatchable-function-entry.sh
arch/powerpc/tools/check-fpatchable-function-entry.sh