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Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm

Pull arm fixes from Russell King:
"A number of fixes for the PJ4/iwmmxt changes which arm-soc forced me
to take during the merge window. This stuff should have been better
tested and sorted out *before* the merge window"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8042/1: iwmmxt: allow to build iWMMXt on Marvell PJ4B
ARM: 8041/1: pj4: fix cpu_is_pj4 check
ARM: 8040/1: pj4: properly detect existence of iWMMXt coprocessor
ARM: 8039/1: pj4: enable iWMMXt only if CONFIG_IWMMXT is set
ARM: 8038/1: iwmmxt: explicitly check for supported architectures

+56 -15
+3 -3
arch/arm/Kconfig
··· 1111 1111 default 8 1112 1112 1113 1113 config IWMMXT 1114 - bool "Enable iWMMXt support" if !CPU_PJ4 1115 - depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1116 - default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 1114 + bool "Enable iWMMXt support" 1115 + depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 1116 + default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 1117 1117 help 1118 1118 Enable support for iWMMXt context switching at run time if 1119 1119 running on a CPU that supports it.
+7 -7
arch/arm/include/asm/cputype.h
··· 222 222 #endif 223 223 224 224 /* 225 - * Marvell's PJ4 core is based on V7 version. It has some modification 226 - * for coprocessor setting. For this reason, we need a way to distinguish 227 - * it. 225 + * Marvell's PJ4 and PJ4B cores are based on V7 version, 226 + * but require a specical sequence for enabling coprocessors. 227 + * For this reason, we need a way to distinguish them. 228 228 */ 229 - #ifndef CONFIG_CPU_PJ4 230 - #define cpu_is_pj4() 0 231 - #else 229 + #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B) 232 230 static inline int cpu_is_pj4(void) 233 231 { 234 232 unsigned int id; 235 233 236 234 id = read_cpuid_id(); 237 - if ((id & 0xfffffff0) == 0x562f5840) 235 + if ((id & 0xff0fff00) == 0x560f5800) 238 236 return 1; 239 237 240 238 return 0; 241 239 } 240 + #else 241 + #define cpu_is_pj4() 0 242 242 #endif 243 243 #endif
+1
arch/arm/kernel/Makefile
··· 79 79 obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o 80 80 obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o 81 81 obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o 82 + obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o 82 83 obj-$(CONFIG_IWMMXT) += iwmmxt.o 83 84 obj-$(CONFIG_PERF_EVENTS) += perf_regs.o 84 85 obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o
+6 -2
arch/arm/kernel/iwmmxt.S
··· 19 19 #include <asm/thread_info.h> 20 20 #include <asm/asm-offsets.h> 21 21 22 - #if defined(CONFIG_CPU_PJ4) 22 + #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B) 23 23 #define PJ4(code...) code 24 24 #define XSC(code...) 25 - #else 25 + #elif defined(CONFIG_CPU_MOHAWK) || \ 26 + defined(CONFIG_CPU_XSC3) || \ 27 + defined(CONFIG_CPU_XSCALE) 26 28 #define PJ4(code...) 27 29 #define XSC(code...) code 30 + #else 31 + #error "Unsupported iWMMXt architecture" 28 32 #endif 29 33 30 34 #define MMX_WR0 (0x00)
+39 -3
arch/arm/kernel/pj4-cp0.c
··· 45 45 return NOTIFY_DONE; 46 46 } 47 47 48 - static struct notifier_block iwmmxt_notifier_block = { 48 + static struct notifier_block __maybe_unused iwmmxt_notifier_block = { 49 49 .notifier_call = iwmmxt_do, 50 50 }; 51 51 ··· 72 72 : "=r" (temp) : "r" (value)); 73 73 } 74 74 75 + static int __init pj4_get_iwmmxt_version(void) 76 + { 77 + u32 cp_access, wcid; 78 + 79 + cp_access = pj4_cp_access_read(); 80 + pj4_cp_access_write(cp_access | 0xf); 81 + 82 + /* check if coprocessor 0 and 1 are available */ 83 + if ((pj4_cp_access_read() & 0xf) != 0xf) { 84 + pj4_cp_access_write(cp_access); 85 + return -ENODEV; 86 + } 87 + 88 + /* read iWMMXt coprocessor id register p1, c0 */ 89 + __asm__ __volatile__ ("mrc p1, 0, %0, c0, c0, 0\n" : "=r" (wcid)); 90 + 91 + pj4_cp_access_write(cp_access); 92 + 93 + /* iWMMXt v1 */ 94 + if ((wcid & 0xffffff00) == 0x56051000) 95 + return 1; 96 + /* iWMMXt v2 */ 97 + if ((wcid & 0xffffff00) == 0x56052000) 98 + return 2; 99 + 100 + return -EINVAL; 101 + } 75 102 76 103 /* 77 104 * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy ··· 106 79 */ 107 80 static int __init pj4_cp0_init(void) 108 81 { 109 - u32 cp_access; 82 + u32 __maybe_unused cp_access; 83 + int vers; 110 84 111 85 if (!cpu_is_pj4()) 112 86 return 0; 113 87 88 + vers = pj4_get_iwmmxt_version(); 89 + if (vers < 0) 90 + return 0; 91 + 92 + #ifndef CONFIG_IWMMXT 93 + pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n"); 94 + #else 114 95 cp_access = pj4_cp_access_read() & ~0xf; 115 96 pj4_cp_access_write(cp_access); 116 97 117 - printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n"); 98 + pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers); 118 99 elf_hwcap |= HWCAP_IWMMXT; 119 100 thread_register_notifier(&iwmmxt_notifier_block); 101 + #endif 120 102 121 103 return 0; 122 104 }