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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge branch 'support-some-features-for-the-hibmcge-driver'
Jijie Shao says:
====================
Support some features for the HIBMCGE driver
In this patch series, The HIBMCGE driver implements some functions
such as dump register, unicast MAC address filtering, debugfs and reset.
====================
Link: https://patch.msgid.link/20241216040532.1566229-1-shaojijie@huawei.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+811
-28
+2
-1
drivers/net/ethernet/hisilicon/hibmcge/Makefile
+2
-1
drivers/net/ethernet/hisilicon/hibmcge/Makefile
+29
drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h
+29
drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h
···
4
4
#ifndef __HBG_COMMON_H
5
5
#define __HBG_COMMON_H
6
6
7
+
#include <linux/ethtool.h>
7
8
#include <linux/netdevice.h>
8
9
#include <linux/pci.h>
9
10
#include "hbg_reg.h"
···
34
33
35
34
enum hbg_nic_state {
36
35
HBG_NIC_STATE_EVENT_HANDLING = 0,
36
+
HBG_NIC_STATE_RESETTING,
37
+
HBG_NIC_STATE_RESET_FAIL,
38
+
};
39
+
40
+
enum hbg_reset_type {
41
+
HBG_RESET_TYPE_NONE = 0,
42
+
HBG_RESET_TYPE_FLR,
43
+
HBG_RESET_TYPE_FUNCTION,
37
44
};
38
45
39
46
struct hbg_buffer {
···
93
84
u32 vlan_layers;
94
85
u32 max_mtu;
95
86
u32 min_mtu;
87
+
u32 uc_mac_num;
96
88
97
89
u32 max_frame_len;
98
90
u32 rx_buf_size;
···
124
114
u32 duplex;
125
115
u32 autoneg;
126
116
u32 link_status;
117
+
u32 pause_autoneg;
118
+
};
119
+
120
+
struct hbg_mac_table_entry {
121
+
u8 addr[ETH_ALEN];
122
+
};
123
+
124
+
struct hbg_mac_filter {
125
+
struct hbg_mac_table_entry *mac_table;
126
+
u32 table_max_len;
127
+
bool enabled;
128
+
};
129
+
130
+
/* saved for restore after rest */
131
+
struct hbg_user_def {
132
+
struct ethtool_pauseparam pause_param;
127
133
};
128
134
129
135
struct hbg_priv {
···
152
126
struct hbg_vector vectors;
153
127
struct hbg_ring tx_ring;
154
128
struct hbg_ring rx_ring;
129
+
struct hbg_mac_filter filter;
130
+
enum hbg_reset_type reset_type;
131
+
struct hbg_user_def user_def;
155
132
};
156
133
157
134
#endif
+160
drivers/net/ethernet/hisilicon/hibmcge/hbg_debugfs.c
+160
drivers/net/ethernet/hisilicon/hibmcge/hbg_debugfs.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
// Copyright (c) 2024 Hisilicon Limited.
3
+
4
+
#include <linux/debugfs.h>
5
+
#include <linux/device.h>
6
+
#include <linux/etherdevice.h>
7
+
#include <linux/seq_file.h>
8
+
#include <linux/string_choices.h>
9
+
#include "hbg_common.h"
10
+
#include "hbg_debugfs.h"
11
+
#include "hbg_hw.h"
12
+
#include "hbg_irq.h"
13
+
#include "hbg_txrx.h"
14
+
15
+
static struct dentry *hbg_dbgfs_root;
16
+
17
+
struct hbg_dbg_info {
18
+
const char *name;
19
+
int (*read)(struct seq_file *seq, void *data);
20
+
};
21
+
22
+
#define state_str_true_false(p, s) str_true_false(test_bit(s, &(p)->state))
23
+
24
+
static void hbg_dbg_ring(struct hbg_priv *priv, struct hbg_ring *ring,
25
+
struct seq_file *s)
26
+
{
27
+
u32 irq_mask = ring->dir == HBG_DIR_TX ? HBG_INT_MSK_TX_B :
28
+
HBG_INT_MSK_RX_B;
29
+
30
+
seq_printf(s, "ring used num: %u\n",
31
+
hbg_get_queue_used_num(ring));
32
+
seq_printf(s, "ring max num: %u\n", ring->len);
33
+
seq_printf(s, "ring head: %u, tail: %u\n", ring->head, ring->tail);
34
+
seq_printf(s, "fifo used num: %u\n",
35
+
hbg_hw_get_fifo_used_num(priv, ring->dir));
36
+
seq_printf(s, "fifo max num: %u\n",
37
+
hbg_get_spec_fifo_max_num(priv, ring->dir));
38
+
seq_printf(s, "irq enabled: %s\n",
39
+
str_true_false(hbg_hw_irq_is_enabled(priv, irq_mask)));
40
+
}
41
+
42
+
static int hbg_dbg_tx_ring(struct seq_file *s, void *unused)
43
+
{
44
+
struct net_device *netdev = dev_get_drvdata(s->private);
45
+
struct hbg_priv *priv = netdev_priv(netdev);
46
+
47
+
hbg_dbg_ring(priv, &priv->tx_ring, s);
48
+
return 0;
49
+
}
50
+
51
+
static int hbg_dbg_rx_ring(struct seq_file *s, void *unused)
52
+
{
53
+
struct net_device *netdev = dev_get_drvdata(s->private);
54
+
struct hbg_priv *priv = netdev_priv(netdev);
55
+
56
+
hbg_dbg_ring(priv, &priv->rx_ring, s);
57
+
return 0;
58
+
}
59
+
60
+
static int hbg_dbg_irq_info(struct seq_file *s, void *unused)
61
+
{
62
+
struct net_device *netdev = dev_get_drvdata(s->private);
63
+
struct hbg_priv *priv = netdev_priv(netdev);
64
+
struct hbg_irq_info *info;
65
+
u32 i;
66
+
67
+
for (i = 0; i < priv->vectors.info_array_len; i++) {
68
+
info = &priv->vectors.info_array[i];
69
+
seq_printf(s,
70
+
"%-20s: enabled: %-5s, logged: %-5s, count: %llu\n",
71
+
info->name,
72
+
str_true_false(hbg_hw_irq_is_enabled(priv,
73
+
info->mask)),
74
+
str_true_false(info->need_print),
75
+
info->count);
76
+
}
77
+
78
+
return 0;
79
+
}
80
+
81
+
static int hbg_dbg_mac_table(struct seq_file *s, void *unused)
82
+
{
83
+
struct net_device *netdev = dev_get_drvdata(s->private);
84
+
struct hbg_priv *priv = netdev_priv(netdev);
85
+
struct hbg_mac_filter *filter;
86
+
u32 i;
87
+
88
+
filter = &priv->filter;
89
+
seq_printf(s, "mac addr max count: %u\n", filter->table_max_len);
90
+
seq_printf(s, "filter enabled: %s\n", str_true_false(filter->enabled));
91
+
92
+
for (i = 0; i < filter->table_max_len; i++) {
93
+
if (is_zero_ether_addr(filter->mac_table[i].addr))
94
+
continue;
95
+
96
+
seq_printf(s, "[%u] %pM\n", i, filter->mac_table[i].addr);
97
+
}
98
+
99
+
return 0;
100
+
}
101
+
102
+
static const char * const reset_type_str[] = {"None", "FLR", "Function"};
103
+
104
+
static int hbg_dbg_nic_state(struct seq_file *s, void *unused)
105
+
{
106
+
struct net_device *netdev = dev_get_drvdata(s->private);
107
+
struct hbg_priv *priv = netdev_priv(netdev);
108
+
109
+
seq_printf(s, "event handling state: %s\n",
110
+
state_str_true_false(priv, HBG_NIC_STATE_EVENT_HANDLING));
111
+
seq_printf(s, "resetting state: %s\n",
112
+
state_str_true_false(priv, HBG_NIC_STATE_RESETTING));
113
+
seq_printf(s, "reset fail state: %s\n",
114
+
state_str_true_false(priv, HBG_NIC_STATE_RESET_FAIL));
115
+
seq_printf(s, "last reset type: %s\n",
116
+
reset_type_str[priv->reset_type]);
117
+
118
+
return 0;
119
+
}
120
+
121
+
static const struct hbg_dbg_info hbg_dbg_infos[] = {
122
+
{ "tx_ring", hbg_dbg_tx_ring },
123
+
{ "rx_ring", hbg_dbg_rx_ring },
124
+
{ "irq_info", hbg_dbg_irq_info },
125
+
{ "mac_table", hbg_dbg_mac_table },
126
+
{ "nic_state", hbg_dbg_nic_state },
127
+
};
128
+
129
+
static void hbg_debugfs_uninit(void *data)
130
+
{
131
+
debugfs_remove_recursive((struct dentry *)data);
132
+
}
133
+
134
+
void hbg_debugfs_init(struct hbg_priv *priv)
135
+
{
136
+
const char *name = pci_name(priv->pdev);
137
+
struct device *dev = &priv->pdev->dev;
138
+
struct dentry *root;
139
+
u32 i;
140
+
141
+
root = debugfs_create_dir(name, hbg_dbgfs_root);
142
+
143
+
for (i = 0; i < ARRAY_SIZE(hbg_dbg_infos); i++)
144
+
debugfs_create_devm_seqfile(dev, hbg_dbg_infos[i].name,
145
+
root, hbg_dbg_infos[i].read);
146
+
147
+
/* Ignore the failure because debugfs is not a key feature. */
148
+
devm_add_action_or_reset(dev, hbg_debugfs_uninit, root);
149
+
}
150
+
151
+
void hbg_debugfs_register(void)
152
+
{
153
+
hbg_dbgfs_root = debugfs_create_dir("hibmcge", NULL);
154
+
}
155
+
156
+
void hbg_debugfs_unregister(void)
157
+
{
158
+
debugfs_remove_recursive(hbg_dbgfs_root);
159
+
hbg_dbgfs_root = NULL;
160
+
}
+12
drivers/net/ethernet/hisilicon/hibmcge/hbg_debugfs.h
+12
drivers/net/ethernet/hisilicon/hibmcge/hbg_debugfs.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/* Copyright (c) 2024 Hisilicon Limited. */
3
+
4
+
#ifndef __HBG_DEBUGFS_H
5
+
#define __HBG_DEBUGFS_H
6
+
7
+
void hbg_debugfs_register(void);
8
+
void hbg_debugfs_unregister(void);
9
+
10
+
void hbg_debugfs_init(struct hbg_priv *priv);
11
+
12
+
#endif
+134
drivers/net/ethernet/hisilicon/hibmcge/hbg_err.c
+134
drivers/net/ethernet/hisilicon/hibmcge/hbg_err.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
// Copyright (c) 2024 Hisilicon Limited.
3
+
4
+
#include <linux/etherdevice.h>
5
+
#include <linux/netdevice.h>
6
+
#include <linux/phy.h>
7
+
#include <linux/rtnetlink.h>
8
+
#include "hbg_common.h"
9
+
#include "hbg_err.h"
10
+
#include "hbg_hw.h"
11
+
12
+
static void hbg_restore_mac_table(struct hbg_priv *priv)
13
+
{
14
+
struct hbg_mac_filter *filter = &priv->filter;
15
+
u64 addr;
16
+
u32 i;
17
+
18
+
for (i = 0; i < filter->table_max_len; i++)
19
+
if (!is_zero_ether_addr(filter->mac_table[i].addr)) {
20
+
addr = ether_addr_to_u64(filter->mac_table[i].addr);
21
+
hbg_hw_set_uc_addr(priv, addr, i);
22
+
}
23
+
24
+
hbg_hw_set_mac_filter_enable(priv, priv->filter.enabled);
25
+
}
26
+
27
+
static void hbg_restore_user_def_settings(struct hbg_priv *priv)
28
+
{
29
+
struct ethtool_pauseparam *pause_param = &priv->user_def.pause_param;
30
+
31
+
hbg_restore_mac_table(priv);
32
+
hbg_hw_set_mtu(priv, priv->netdev->mtu);
33
+
hbg_hw_set_pause_enable(priv, pause_param->tx_pause,
34
+
pause_param->rx_pause);
35
+
}
36
+
37
+
int hbg_rebuild(struct hbg_priv *priv)
38
+
{
39
+
int ret;
40
+
41
+
ret = hbg_hw_init(priv);
42
+
if (ret)
43
+
return ret;
44
+
45
+
hbg_restore_user_def_settings(priv);
46
+
return 0;
47
+
}
48
+
49
+
static int hbg_reset_prepare(struct hbg_priv *priv, enum hbg_reset_type type)
50
+
{
51
+
int ret;
52
+
53
+
ASSERT_RTNL();
54
+
55
+
if (netif_running(priv->netdev)) {
56
+
dev_warn(&priv->pdev->dev,
57
+
"failed to reset because port is up\n");
58
+
return -EBUSY;
59
+
}
60
+
61
+
priv->reset_type = type;
62
+
set_bit(HBG_NIC_STATE_RESETTING, &priv->state);
63
+
clear_bit(HBG_NIC_STATE_RESET_FAIL, &priv->state);
64
+
ret = hbg_hw_event_notify(priv, HBG_HW_EVENT_RESET);
65
+
if (ret) {
66
+
set_bit(HBG_NIC_STATE_RESET_FAIL, &priv->state);
67
+
clear_bit(HBG_NIC_STATE_RESETTING, &priv->state);
68
+
}
69
+
70
+
return ret;
71
+
}
72
+
73
+
static int hbg_reset_done(struct hbg_priv *priv, enum hbg_reset_type type)
74
+
{
75
+
int ret;
76
+
77
+
if (!test_bit(HBG_NIC_STATE_RESETTING, &priv->state) ||
78
+
type != priv->reset_type)
79
+
return 0;
80
+
81
+
ASSERT_RTNL();
82
+
83
+
clear_bit(HBG_NIC_STATE_RESETTING, &priv->state);
84
+
ret = hbg_rebuild(priv);
85
+
if (ret) {
86
+
set_bit(HBG_NIC_STATE_RESET_FAIL, &priv->state);
87
+
dev_err(&priv->pdev->dev, "failed to rebuild after reset\n");
88
+
return ret;
89
+
}
90
+
91
+
dev_info(&priv->pdev->dev, "reset done\n");
92
+
return ret;
93
+
}
94
+
95
+
/* must be protected by rtnl lock */
96
+
int hbg_reset(struct hbg_priv *priv)
97
+
{
98
+
int ret;
99
+
100
+
ASSERT_RTNL();
101
+
ret = hbg_reset_prepare(priv, HBG_RESET_TYPE_FUNCTION);
102
+
if (ret)
103
+
return ret;
104
+
105
+
return hbg_reset_done(priv, HBG_RESET_TYPE_FUNCTION);
106
+
}
107
+
108
+
static void hbg_pci_err_reset_prepare(struct pci_dev *pdev)
109
+
{
110
+
struct net_device *netdev = pci_get_drvdata(pdev);
111
+
struct hbg_priv *priv = netdev_priv(netdev);
112
+
113
+
rtnl_lock();
114
+
hbg_reset_prepare(priv, HBG_RESET_TYPE_FLR);
115
+
}
116
+
117
+
static void hbg_pci_err_reset_done(struct pci_dev *pdev)
118
+
{
119
+
struct net_device *netdev = pci_get_drvdata(pdev);
120
+
struct hbg_priv *priv = netdev_priv(netdev);
121
+
122
+
hbg_reset_done(priv, HBG_RESET_TYPE_FLR);
123
+
rtnl_unlock();
124
+
}
125
+
126
+
static const struct pci_error_handlers hbg_pci_err_handler = {
127
+
.reset_prepare = hbg_pci_err_reset_prepare,
128
+
.reset_done = hbg_pci_err_reset_done,
129
+
};
130
+
131
+
void hbg_set_pci_err_handler(struct pci_driver *pdrv)
132
+
{
133
+
pdrv->err_handler = &hbg_pci_err_handler;
134
+
}
+13
drivers/net/ethernet/hisilicon/hibmcge/hbg_err.h
+13
drivers/net/ethernet/hisilicon/hibmcge/hbg_err.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/* Copyright (c) 2024 Hisilicon Limited. */
3
+
4
+
#ifndef __HBG_ERR_H
5
+
#define __HBG_ERR_H
6
+
7
+
#include <linux/pci.h>
8
+
9
+
void hbg_set_pci_err_handler(struct pci_driver *pdrv);
10
+
int hbg_reset(struct hbg_priv *priv);
11
+
int hbg_rebuild(struct hbg_priv *priv);
12
+
13
+
#endif
+181
drivers/net/ethernet/hisilicon/hibmcge/hbg_ethtool.c
+181
drivers/net/ethernet/hisilicon/hibmcge/hbg_ethtool.c
···
3
3
4
4
#include <linux/ethtool.h>
5
5
#include <linux/phy.h>
6
+
#include <linux/rtnetlink.h>
7
+
#include "hbg_common.h"
8
+
#include "hbg_err.h"
6
9
#include "hbg_ethtool.h"
10
+
#include "hbg_hw.h"
11
+
12
+
enum hbg_reg_dump_type {
13
+
HBG_DUMP_REG_TYPE_SPEC = 0,
14
+
HBG_DUMP_REG_TYPE_MDIO,
15
+
HBG_DUMP_REG_TYPE_GMAC,
16
+
HBG_DUMP_REG_TYPE_PCU,
17
+
};
18
+
19
+
struct hbg_reg_info {
20
+
u32 type;
21
+
u32 offset;
22
+
u32 val;
23
+
};
24
+
25
+
#define HBG_DUMP_SPEC_I(offset) {HBG_DUMP_REG_TYPE_SPEC, offset, 0}
26
+
#define HBG_DUMP_MDIO_I(offset) {HBG_DUMP_REG_TYPE_MDIO, offset, 0}
27
+
#define HBG_DUMP_GMAC_I(offset) {HBG_DUMP_REG_TYPE_GMAC, offset, 0}
28
+
#define HBG_DUMP_PCU_I(offset) {HBG_DUMP_REG_TYPE_PCU, offset, 0}
29
+
30
+
static const struct hbg_reg_info hbg_dump_reg_infos[] = {
31
+
/* dev specs */
32
+
HBG_DUMP_SPEC_I(HBG_REG_SPEC_VALID_ADDR),
33
+
HBG_DUMP_SPEC_I(HBG_REG_EVENT_REQ_ADDR),
34
+
HBG_DUMP_SPEC_I(HBG_REG_MAC_ID_ADDR),
35
+
HBG_DUMP_SPEC_I(HBG_REG_PHY_ID_ADDR),
36
+
HBG_DUMP_SPEC_I(HBG_REG_MAC_ADDR_ADDR),
37
+
HBG_DUMP_SPEC_I(HBG_REG_MAC_ADDR_HIGH_ADDR),
38
+
HBG_DUMP_SPEC_I(HBG_REG_UC_MAC_NUM_ADDR),
39
+
HBG_DUMP_SPEC_I(HBG_REG_MDIO_FREQ_ADDR),
40
+
HBG_DUMP_SPEC_I(HBG_REG_MAX_MTU_ADDR),
41
+
HBG_DUMP_SPEC_I(HBG_REG_MIN_MTU_ADDR),
42
+
HBG_DUMP_SPEC_I(HBG_REG_TX_FIFO_NUM_ADDR),
43
+
HBG_DUMP_SPEC_I(HBG_REG_RX_FIFO_NUM_ADDR),
44
+
HBG_DUMP_SPEC_I(HBG_REG_VLAN_LAYERS_ADDR),
45
+
46
+
/* mdio */
47
+
HBG_DUMP_MDIO_I(HBG_REG_MDIO_COMMAND_ADDR),
48
+
HBG_DUMP_MDIO_I(HBG_REG_MDIO_ADDR_ADDR),
49
+
HBG_DUMP_MDIO_I(HBG_REG_MDIO_WDATA_ADDR),
50
+
HBG_DUMP_MDIO_I(HBG_REG_MDIO_RDATA_ADDR),
51
+
HBG_DUMP_MDIO_I(HBG_REG_MDIO_STA_ADDR),
52
+
53
+
/* gmac */
54
+
HBG_DUMP_GMAC_I(HBG_REG_DUPLEX_TYPE_ADDR),
55
+
HBG_DUMP_GMAC_I(HBG_REG_FD_FC_TYPE_ADDR),
56
+
HBG_DUMP_GMAC_I(HBG_REG_FC_TX_TIMER_ADDR),
57
+
HBG_DUMP_GMAC_I(HBG_REG_FD_FC_ADDR_LOW_ADDR),
58
+
HBG_DUMP_GMAC_I(HBG_REG_FD_FC_ADDR_HIGH_ADDR),
59
+
HBG_DUMP_GMAC_I(HBG_REG_MAX_FRAME_SIZE_ADDR),
60
+
HBG_DUMP_GMAC_I(HBG_REG_PORT_MODE_ADDR),
61
+
HBG_DUMP_GMAC_I(HBG_REG_PORT_ENABLE_ADDR),
62
+
HBG_DUMP_GMAC_I(HBG_REG_PAUSE_ENABLE_ADDR),
63
+
HBG_DUMP_GMAC_I(HBG_REG_AN_NEG_STATE_ADDR),
64
+
HBG_DUMP_GMAC_I(HBG_REG_TRANSMIT_CTRL_ADDR),
65
+
HBG_DUMP_GMAC_I(HBG_REG_REC_FILT_CTRL_ADDR),
66
+
HBG_DUMP_GMAC_I(HBG_REG_LINE_LOOP_BACK_ADDR),
67
+
HBG_DUMP_GMAC_I(HBG_REG_CF_CRC_STRIP_ADDR),
68
+
HBG_DUMP_GMAC_I(HBG_REG_MODE_CHANGE_EN_ADDR),
69
+
HBG_DUMP_GMAC_I(HBG_REG_LOOP_REG_ADDR),
70
+
HBG_DUMP_GMAC_I(HBG_REG_RECV_CTRL_ADDR),
71
+
HBG_DUMP_GMAC_I(HBG_REG_VLAN_CODE_ADDR),
72
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_LOW_0_ADDR),
73
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_HIGH_0_ADDR),
74
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_LOW_1_ADDR),
75
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_HIGH_1_ADDR),
76
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_LOW_2_ADDR),
77
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_HIGH_2_ADDR),
78
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_LOW_3_ADDR),
79
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_HIGH_3_ADDR),
80
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_LOW_4_ADDR),
81
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_HIGH_4_ADDR),
82
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_LOW_5_ADDR),
83
+
HBG_DUMP_GMAC_I(HBG_REG_STATION_ADDR_HIGH_5_ADDR),
84
+
85
+
/* pcu */
86
+
HBG_DUMP_PCU_I(HBG_REG_TX_FIFO_THRSLD_ADDR),
87
+
HBG_DUMP_PCU_I(HBG_REG_RX_FIFO_THRSLD_ADDR),
88
+
HBG_DUMP_PCU_I(HBG_REG_CFG_FIFO_THRSLD_ADDR),
89
+
HBG_DUMP_PCU_I(HBG_REG_CF_INTRPT_MSK_ADDR),
90
+
HBG_DUMP_PCU_I(HBG_REG_CF_INTRPT_STAT_ADDR),
91
+
HBG_DUMP_PCU_I(HBG_REG_CF_INTRPT_CLR_ADDR),
92
+
HBG_DUMP_PCU_I(HBG_REG_TX_BUS_ERR_ADDR_ADDR),
93
+
HBG_DUMP_PCU_I(HBG_REG_RX_BUS_ERR_ADDR_ADDR),
94
+
HBG_DUMP_PCU_I(HBG_REG_MAX_FRAME_LEN_ADDR),
95
+
HBG_DUMP_PCU_I(HBG_REG_DEBUG_ST_MCH_ADDR),
96
+
HBG_DUMP_PCU_I(HBG_REG_FIFO_CURR_STATUS_ADDR),
97
+
HBG_DUMP_PCU_I(HBG_REG_FIFO_HIST_STATUS_ADDR),
98
+
HBG_DUMP_PCU_I(HBG_REG_CF_CFF_DATA_NUM_ADDR),
99
+
HBG_DUMP_PCU_I(HBG_REG_CF_TX_PAUSE_ADDR),
100
+
HBG_DUMP_PCU_I(HBG_REG_RX_CFF_ADDR_ADDR),
101
+
HBG_DUMP_PCU_I(HBG_REG_RX_BUF_SIZE_ADDR),
102
+
HBG_DUMP_PCU_I(HBG_REG_BUS_CTRL_ADDR),
103
+
HBG_DUMP_PCU_I(HBG_REG_RX_CTRL_ADDR),
104
+
HBG_DUMP_PCU_I(HBG_REG_RX_PKT_MODE_ADDR),
105
+
HBG_DUMP_PCU_I(HBG_REG_DBG_ST0_ADDR),
106
+
HBG_DUMP_PCU_I(HBG_REG_DBG_ST1_ADDR),
107
+
HBG_DUMP_PCU_I(HBG_REG_DBG_ST2_ADDR),
108
+
HBG_DUMP_PCU_I(HBG_REG_BUS_RST_EN_ADDR),
109
+
HBG_DUMP_PCU_I(HBG_REG_CF_IND_TXINT_MSK_ADDR),
110
+
HBG_DUMP_PCU_I(HBG_REG_CF_IND_TXINT_STAT_ADDR),
111
+
HBG_DUMP_PCU_I(HBG_REG_CF_IND_TXINT_CLR_ADDR),
112
+
HBG_DUMP_PCU_I(HBG_REG_CF_IND_RXINT_MSK_ADDR),
113
+
HBG_DUMP_PCU_I(HBG_REG_CF_IND_RXINT_STAT_ADDR),
114
+
HBG_DUMP_PCU_I(HBG_REG_CF_IND_RXINT_CLR_ADDR),
115
+
};
116
+
117
+
static const u32 hbg_dump_type_base_array[] = {
118
+
[HBG_DUMP_REG_TYPE_SPEC] = 0,
119
+
[HBG_DUMP_REG_TYPE_MDIO] = HBG_REG_MDIO_BASE,
120
+
[HBG_DUMP_REG_TYPE_GMAC] = HBG_REG_SGMII_BASE,
121
+
[HBG_DUMP_REG_TYPE_PCU] = HBG_REG_SGMII_BASE,
122
+
};
123
+
124
+
static int hbg_ethtool_get_regs_len(struct net_device *netdev)
125
+
{
126
+
return ARRAY_SIZE(hbg_dump_reg_infos) * sizeof(struct hbg_reg_info);
127
+
}
128
+
129
+
static void hbg_ethtool_get_regs(struct net_device *netdev,
130
+
struct ethtool_regs *regs, void *data)
131
+
{
132
+
struct hbg_priv *priv = netdev_priv(netdev);
133
+
struct hbg_reg_info *info;
134
+
u32 i, offset = 0;
135
+
136
+
regs->version = 0;
137
+
for (i = 0; i < ARRAY_SIZE(hbg_dump_reg_infos); i++) {
138
+
info = data + offset;
139
+
140
+
*info = hbg_dump_reg_infos[i];
141
+
info->val = hbg_reg_read(priv, info->offset);
142
+
info->offset -= hbg_dump_type_base_array[info->type];
143
+
144
+
offset += sizeof(*info);
145
+
}
146
+
}
147
+
148
+
static void hbg_ethtool_get_pauseparam(struct net_device *net_dev,
149
+
struct ethtool_pauseparam *param)
150
+
{
151
+
struct hbg_priv *priv = netdev_priv(net_dev);
152
+
153
+
param->autoneg = priv->mac.pause_autoneg;
154
+
hbg_hw_get_pause_enable(priv, ¶m->tx_pause, ¶m->rx_pause);
155
+
}
156
+
157
+
static int hbg_ethtool_set_pauseparam(struct net_device *net_dev,
158
+
struct ethtool_pauseparam *param)
159
+
{
160
+
struct hbg_priv *priv = netdev_priv(net_dev);
161
+
162
+
priv->mac.pause_autoneg = param->autoneg;
163
+
phy_set_asym_pause(priv->mac.phydev, param->rx_pause, param->tx_pause);
164
+
165
+
if (!param->autoneg)
166
+
hbg_hw_set_pause_enable(priv, param->tx_pause, param->rx_pause);
167
+
168
+
priv->user_def.pause_param = *param;
169
+
return 0;
170
+
}
171
+
172
+
static int hbg_ethtool_reset(struct net_device *netdev, u32 *flags)
173
+
{
174
+
struct hbg_priv *priv = netdev_priv(netdev);
175
+
176
+
if (*flags != ETH_RESET_DEDICATED)
177
+
return -EOPNOTSUPP;
178
+
179
+
*flags = 0;
180
+
return hbg_reset(priv);
181
+
}
7
182
8
183
static const struct ethtool_ops hbg_ethtool_ops = {
9
184
.get_link = ethtool_op_get_link,
10
185
.get_link_ksettings = phy_ethtool_get_link_ksettings,
11
186
.set_link_ksettings = phy_ethtool_set_link_ksettings,
187
+
.get_regs_len = hbg_ethtool_get_regs_len,
188
+
.get_regs = hbg_ethtool_get_regs,
189
+
.get_pauseparam = hbg_ethtool_get_pauseparam,
190
+
.set_pauseparam = hbg_ethtool_set_pauseparam,
191
+
.reset = hbg_ethtool_reset,
192
+
.nway_reset = phy_ethtool_nway_reset,
12
193
};
13
194
14
195
void hbg_ethtool_set_ops(struct net_device *netdev)
+44
-4
drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c
+44
-4
drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c
···
3
3
4
4
#include <linux/etherdevice.h>
5
5
#include <linux/ethtool.h>
6
+
#include <linux/if_vlan.h>
6
7
#include <linux/iopoll.h>
7
8
#include <linux/minmax.h>
8
9
#include "hbg_common.h"
···
68
67
specs->vlan_layers = hbg_reg_read(priv, HBG_REG_VLAN_LAYERS_ADDR);
69
68
specs->rx_fifo_num = hbg_reg_read(priv, HBG_REG_RX_FIFO_NUM_ADDR);
70
69
specs->tx_fifo_num = hbg_reg_read(priv, HBG_REG_TX_FIFO_NUM_ADDR);
70
+
specs->uc_mac_num = hbg_reg_read(priv, HBG_REG_UC_MAC_NUM_ADDR);
71
+
71
72
mac_addr = hbg_reg_read64(priv, HBG_REG_MAC_ADDR_ADDR);
72
73
u64_to_ether_addr(mac_addr, (u8 *)specs->mac_addr.sa_data);
73
74
···
138
135
hbg_reg_write(priv, HBG_REG_CF_INTRPT_MSK_ADDR, value);
139
136
}
140
137
141
-
void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr)
138
+
void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr, u32 index)
142
139
{
143
-
hbg_reg_write64(priv, HBG_REG_STATION_ADDR_LOW_2_ADDR, mac_addr);
140
+
u32 addr;
141
+
142
+
/* mac addr is u64, so the addr offset is 0x8 */
143
+
addr = HBG_REG_STATION_ADDR_LOW_2_ADDR + (index * 0x8);
144
+
hbg_reg_write64(priv, addr, mac_addr);
144
145
}
145
146
146
147
static void hbg_hw_set_pcu_max_frame_len(struct hbg_priv *priv,
···
168
161
169
162
void hbg_hw_set_mtu(struct hbg_priv *priv, u16 mtu)
170
163
{
171
-
hbg_hw_set_pcu_max_frame_len(priv, mtu);
172
-
hbg_hw_set_mac_max_frame_len(priv, mtu);
164
+
u32 frame_len;
165
+
166
+
frame_len = mtu + VLAN_HLEN * priv->dev_specs.vlan_layers +
167
+
ETH_HLEN + ETH_FCS_LEN;
168
+
169
+
hbg_hw_set_pcu_max_frame_len(priv, frame_len);
170
+
hbg_hw_set_mac_max_frame_len(priv, frame_len);
173
171
}
174
172
175
173
void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable)
···
217
205
HBG_REG_PORT_MODE_M, speed);
218
206
hbg_reg_write_field(priv, HBG_REG_DUPLEX_TYPE_ADDR,
219
207
HBG_REG_DUPLEX_B, duplex);
208
+
}
209
+
210
+
/* only support uc filter */
211
+
void hbg_hw_set_mac_filter_enable(struct hbg_priv *priv, u32 enable)
212
+
{
213
+
hbg_reg_write_field(priv, HBG_REG_REC_FILT_CTRL_ADDR,
214
+
HBG_REG_REC_FILT_CTRL_UC_MATCH_EN_B, enable);
215
+
}
216
+
217
+
void hbg_hw_set_pause_enable(struct hbg_priv *priv, u32 tx_en, u32 rx_en)
218
+
{
219
+
hbg_reg_write_field(priv, HBG_REG_PAUSE_ENABLE_ADDR,
220
+
HBG_REG_PAUSE_ENABLE_TX_B, tx_en);
221
+
hbg_reg_write_field(priv, HBG_REG_PAUSE_ENABLE_ADDR,
222
+
HBG_REG_PAUSE_ENABLE_RX_B, rx_en);
223
+
}
224
+
225
+
void hbg_hw_get_pause_enable(struct hbg_priv *priv, u32 *tx_en, u32 *rx_en)
226
+
{
227
+
*tx_en = hbg_reg_read_field(priv, HBG_REG_PAUSE_ENABLE_ADDR,
228
+
HBG_REG_PAUSE_ENABLE_TX_B);
229
+
*rx_en = hbg_reg_read_field(priv, HBG_REG_PAUSE_ENABLE_ADDR,
230
+
HBG_REG_PAUSE_ENABLE_RX_B);
231
+
}
232
+
233
+
void hbg_hw_set_rx_pause_mac_addr(struct hbg_priv *priv, u64 mac_addr)
234
+
{
235
+
hbg_reg_write64(priv, HBG_REG_FD_FC_ADDR_LOW_ADDR, mac_addr);
220
236
}
221
237
222
238
static void hbg_hw_init_transmit_ctrl(struct hbg_priv *priv)
+5
-1
drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h
+5
-1
drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h
···
51
51
void hbg_hw_irq_enable(struct hbg_priv *priv, u32 mask, bool enable);
52
52
void hbg_hw_set_mtu(struct hbg_priv *priv, u16 mtu);
53
53
void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable);
54
-
void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr);
54
+
void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr, u32 index);
55
55
u32 hbg_hw_get_fifo_used_num(struct hbg_priv *priv, enum hbg_dir dir);
56
56
void hbg_hw_set_tx_desc(struct hbg_priv *priv, struct hbg_tx_desc *tx_desc);
57
57
void hbg_hw_fill_buffer(struct hbg_priv *priv, u32 buffer_dma_addr);
58
+
void hbg_hw_set_mac_filter_enable(struct hbg_priv *priv, u32 enable);
59
+
void hbg_hw_set_pause_enable(struct hbg_priv *priv, u32 tx_en, u32 rx_en);
60
+
void hbg_hw_get_pause_enable(struct hbg_priv *priv, u32 *tx_en, u32 *rx_en);
61
+
void hbg_hw_set_rx_pause_mac_addr(struct hbg_priv *priv, u64 mac_addr);
58
62
59
63
#endif
+177
-22
drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c
+177
-22
drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c
···
6
6
#include <linux/netdevice.h>
7
7
#include <linux/pci.h>
8
8
#include "hbg_common.h"
9
+
#include "hbg_err.h"
9
10
#include "hbg_ethtool.h"
10
11
#include "hbg_hw.h"
11
12
#include "hbg_irq.h"
12
13
#include "hbg_mdio.h"
13
14
#include "hbg_txrx.h"
14
-
15
-
static void hbg_change_mtu(struct hbg_priv *priv, int new_mtu);
15
+
#include "hbg_debugfs.h"
16
16
17
17
static void hbg_all_irq_enable(struct hbg_priv *priv, bool enabled)
18
18
{
···
55
55
return ret;
56
56
57
57
/* After reset, regs need to be reconfigured */
58
-
hbg_hw_init(priv);
59
-
hbg_hw_set_uc_addr(priv, ether_addr_to_u64(priv->netdev->dev_addr));
60
-
hbg_change_mtu(priv, priv->netdev->mtu);
61
-
62
-
return 0;
58
+
return hbg_rebuild(priv);
63
59
}
64
60
65
61
static int hbg_net_stop(struct net_device *netdev)
···
70
74
return hbg_hw_txrx_clear(priv);
71
75
}
72
76
77
+
static void hbg_update_promisc_mode(struct net_device *netdev, bool overflow)
78
+
{
79
+
struct hbg_priv *priv = netdev_priv(netdev);
80
+
81
+
/* Only when not table_overflow, and netdev->flags not set IFF_PROMISC,
82
+
* The MAC filter will be enabled.
83
+
* Otherwise the filter will be disabled.
84
+
*/
85
+
priv->filter.enabled = !(overflow || (netdev->flags & IFF_PROMISC));
86
+
hbg_hw_set_mac_filter_enable(priv, priv->filter.enabled);
87
+
}
88
+
89
+
static void hbg_set_mac_to_mac_table(struct hbg_priv *priv,
90
+
u32 index, const u8 *addr)
91
+
{
92
+
if (addr) {
93
+
ether_addr_copy(priv->filter.mac_table[index].addr, addr);
94
+
hbg_hw_set_uc_addr(priv, ether_addr_to_u64(addr), index);
95
+
} else {
96
+
eth_zero_addr(priv->filter.mac_table[index].addr);
97
+
hbg_hw_set_uc_addr(priv, 0, index);
98
+
}
99
+
}
100
+
101
+
static int hbg_get_index_from_mac_table(struct hbg_priv *priv,
102
+
const u8 *addr, u32 *index)
103
+
{
104
+
u32 i;
105
+
106
+
for (i = 0; i < priv->filter.table_max_len; i++)
107
+
if (ether_addr_equal(priv->filter.mac_table[i].addr, addr)) {
108
+
*index = i;
109
+
return 0;
110
+
}
111
+
112
+
return -EINVAL;
113
+
}
114
+
115
+
static int hbg_add_mac_to_filter(struct hbg_priv *priv, const u8 *addr)
116
+
{
117
+
u32 index;
118
+
119
+
/* already exists */
120
+
if (!hbg_get_index_from_mac_table(priv, addr, &index))
121
+
return 0;
122
+
123
+
for (index = 0; index < priv->filter.table_max_len; index++)
124
+
if (is_zero_ether_addr(priv->filter.mac_table[index].addr)) {
125
+
hbg_set_mac_to_mac_table(priv, index, addr);
126
+
return 0;
127
+
}
128
+
129
+
return -ENOSPC;
130
+
}
131
+
132
+
static void hbg_del_mac_from_filter(struct hbg_priv *priv, const u8 *addr)
133
+
{
134
+
u32 index;
135
+
136
+
/* not exists */
137
+
if (hbg_get_index_from_mac_table(priv, addr, &index))
138
+
return;
139
+
140
+
hbg_set_mac_to_mac_table(priv, index, NULL);
141
+
}
142
+
143
+
static int hbg_uc_sync(struct net_device *netdev, const unsigned char *addr)
144
+
{
145
+
struct hbg_priv *priv = netdev_priv(netdev);
146
+
147
+
return hbg_add_mac_to_filter(priv, addr);
148
+
}
149
+
150
+
static int hbg_uc_unsync(struct net_device *netdev, const unsigned char *addr)
151
+
{
152
+
struct hbg_priv *priv = netdev_priv(netdev);
153
+
154
+
if (ether_addr_equal(netdev->dev_addr, (u8 *)addr))
155
+
return 0;
156
+
157
+
hbg_del_mac_from_filter(priv, addr);
158
+
return 0;
159
+
}
160
+
161
+
static void hbg_net_set_rx_mode(struct net_device *netdev)
162
+
{
163
+
int ret;
164
+
165
+
ret = __dev_uc_sync(netdev, hbg_uc_sync, hbg_uc_unsync);
166
+
167
+
/* If ret != 0, overflow has occurred */
168
+
hbg_update_promisc_mode(netdev, !!ret);
169
+
}
170
+
73
171
static int hbg_net_set_mac_address(struct net_device *netdev, void *addr)
74
172
{
75
173
struct hbg_priv *priv = netdev_priv(netdev);
76
174
u8 *mac_addr;
175
+
bool exists;
176
+
u32 index;
77
177
78
178
mac_addr = ((struct sockaddr *)addr)->sa_data;
79
179
80
180
if (!is_valid_ether_addr(mac_addr))
81
181
return -EADDRNOTAVAIL;
82
182
83
-
hbg_hw_set_uc_addr(priv, ether_addr_to_u64(mac_addr));
183
+
/* The index of host mac is always 0.
184
+
* If new mac address already exists,
185
+
* delete the existing mac address and
186
+
* add it to the position with index 0.
187
+
*/
188
+
exists = !hbg_get_index_from_mac_table(priv, mac_addr, &index);
189
+
hbg_set_mac_to_mac_table(priv, 0, mac_addr);
190
+
if (exists)
191
+
hbg_set_mac_to_mac_table(priv, index, NULL);
192
+
193
+
hbg_hw_set_rx_pause_mac_addr(priv, ether_addr_to_u64(mac_addr));
84
194
dev_addr_set(netdev, mac_addr);
85
-
86
195
return 0;
87
-
}
88
-
89
-
static void hbg_change_mtu(struct hbg_priv *priv, int new_mtu)
90
-
{
91
-
u32 frame_len;
92
-
93
-
frame_len = new_mtu + VLAN_HLEN * priv->dev_specs.vlan_layers +
94
-
ETH_HLEN + ETH_FCS_LEN;
95
-
hbg_hw_set_mtu(priv, frame_len);
96
196
}
97
197
98
198
static int hbg_net_change_mtu(struct net_device *netdev, int new_mtu)
···
198
106
if (netif_running(netdev))
199
107
return -EBUSY;
200
108
201
-
hbg_change_mtu(priv, new_mtu);
109
+
hbg_hw_set_mtu(priv, new_mtu);
202
110
WRITE_ONCE(netdev->mtu, new_mtu);
203
111
204
112
dev_dbg(&priv->pdev->dev,
···
234
142
.ndo_set_mac_address = hbg_net_set_mac_address,
235
143
.ndo_change_mtu = hbg_net_change_mtu,
236
144
.ndo_tx_timeout = hbg_net_tx_timeout,
145
+
.ndo_set_rx_mode = hbg_net_set_rx_mode,
237
146
};
147
+
148
+
static int hbg_mac_filter_init(struct hbg_priv *priv)
149
+
{
150
+
struct hbg_dev_specs *dev_specs = &priv->dev_specs;
151
+
struct hbg_mac_filter *filter = &priv->filter;
152
+
struct hbg_mac_table_entry *tmp_table;
153
+
154
+
tmp_table = devm_kcalloc(&priv->pdev->dev, dev_specs->uc_mac_num,
155
+
sizeof(*tmp_table), GFP_KERNEL);
156
+
if (!tmp_table)
157
+
return -ENOMEM;
158
+
159
+
filter->mac_table = tmp_table;
160
+
filter->table_max_len = dev_specs->uc_mac_num;
161
+
filter->enabled = true;
162
+
163
+
hbg_hw_set_mac_filter_enable(priv, filter->enabled);
164
+
return 0;
165
+
}
166
+
167
+
static void hbg_init_user_def(struct hbg_priv *priv)
168
+
{
169
+
struct ethtool_pauseparam *pause_param = &priv->user_def.pause_param;
170
+
171
+
priv->mac.pause_autoneg = HBG_STATUS_ENABLE;
172
+
173
+
pause_param->autoneg = priv->mac.pause_autoneg;
174
+
hbg_hw_get_pause_enable(priv, &pause_param->tx_pause,
175
+
&pause_param->rx_pause);
176
+
}
238
177
239
178
static int hbg_init(struct hbg_priv *priv)
240
179
{
···
283
160
if (ret)
284
161
return ret;
285
162
286
-
return hbg_mdio_init(priv);
163
+
ret = hbg_mdio_init(priv);
164
+
if (ret)
165
+
return ret;
166
+
167
+
ret = hbg_mac_filter_init(priv);
168
+
if (ret)
169
+
return ret;
170
+
171
+
hbg_debugfs_init(priv);
172
+
hbg_init_user_def(priv);
173
+
return 0;
287
174
}
288
175
289
176
static int hbg_pci_init(struct pci_dev *pdev)
···
349
216
if (ret)
350
217
return ret;
351
218
219
+
netdev->priv_flags |= IFF_UNICAST_FLT;
220
+
352
221
netdev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS;
353
222
netdev->max_mtu = priv->dev_specs.max_mtu;
354
223
netdev->min_mtu = priv->dev_specs.min_mtu;
355
224
netdev->netdev_ops = &hbg_netdev_ops;
356
225
netdev->watchdog_timeo = 5 * HZ;
357
226
358
-
hbg_change_mtu(priv, ETH_DATA_LEN);
227
+
hbg_hw_set_mtu(priv, ETH_DATA_LEN);
359
228
hbg_net_set_mac_address(priv->netdev, &priv->dev_specs.mac_addr);
360
229
hbg_ethtool_set_ops(netdev);
361
230
···
380
245
.id_table = hbg_pci_tbl,
381
246
.probe = hbg_probe,
382
247
};
383
-
module_pci_driver(hbg_driver);
248
+
249
+
static int __init hbg_module_init(void)
250
+
{
251
+
int ret;
252
+
253
+
hbg_debugfs_register();
254
+
hbg_set_pci_err_handler(&hbg_driver);
255
+
ret = pci_register_driver(&hbg_driver);
256
+
if (ret)
257
+
hbg_debugfs_unregister();
258
+
259
+
return ret;
260
+
}
261
+
module_init(hbg_module_init);
262
+
263
+
static void __exit hbg_module_exit(void)
264
+
{
265
+
pci_unregister_driver(&hbg_driver);
266
+
hbg_debugfs_unregister();
267
+
}
268
+
module_exit(hbg_module_exit);
384
269
385
270
MODULE_LICENSE("GPL");
386
271
MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
+15
drivers/net/ethernet/hisilicon/hibmcge/hbg_mdio.c
+15
drivers/net/ethernet/hisilicon/hibmcge/hbg_mdio.c
···
114
114
hbg_mdio_set_command(mac, cmd);
115
115
}
116
116
117
+
static void hbg_flowctrl_cfg(struct hbg_priv *priv)
118
+
{
119
+
struct phy_device *phydev = priv->mac.phydev;
120
+
bool rx_pause;
121
+
bool tx_pause;
122
+
123
+
if (!priv->mac.pause_autoneg)
124
+
return;
125
+
126
+
phy_get_pause(phydev, &tx_pause, &rx_pause);
127
+
hbg_hw_set_pause_enable(priv, tx_pause, rx_pause);
128
+
}
129
+
117
130
static void hbg_phy_adjust_link(struct net_device *netdev)
118
131
{
119
132
struct hbg_priv *priv = netdev_priv(netdev);
···
153
140
priv->mac.duplex = phydev->duplex;
154
141
priv->mac.autoneg = phydev->autoneg;
155
142
hbg_hw_adjust_link(priv, speed, phydev->duplex);
143
+
hbg_flowctrl_cfg(priv);
156
144
}
157
145
158
146
priv->mac.link_status = phydev->link;
···
182
168
return ret;
183
169
184
170
phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
171
+
phy_support_asym_pause(phydev);
185
172
phy_attached_info(phydev);
186
173
187
174
return 0;
+39
drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h
+39
drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h
···
10
10
#define HBG_REG_MAC_ID_ADDR 0x0008
11
11
#define HBG_REG_PHY_ID_ADDR 0x000C
12
12
#define HBG_REG_MAC_ADDR_ADDR 0x0010
13
+
#define HBG_REG_MAC_ADDR_HIGH_ADDR 0x0014
14
+
#define HBG_REG_UC_MAC_NUM_ADDR 0x0018
13
15
#define HBG_REG_MDIO_FREQ_ADDR 0x0024
14
16
#define HBG_REG_MAX_MTU_ADDR 0x0028
15
17
#define HBG_REG_MIN_MTU_ADDR 0x002C
···
30
28
#define HBG_REG_MDIO_COMMAND_OP_M GENMASK(11, 10)
31
29
#define HBG_REG_MDIO_COMMAND_PRTAD_M GENMASK(9, 5)
32
30
#define HBG_REG_MDIO_COMMAND_DEVAD_M GENMASK(4, 0)
31
+
#define HBG_REG_MDIO_ADDR_ADDR (HBG_REG_MDIO_BASE + 0x0004)
33
32
#define HBG_REG_MDIO_WDATA_ADDR (HBG_REG_MDIO_BASE + 0x0008)
34
33
#define HBG_REG_MDIO_WDATA_M GENMASK(15, 0)
35
34
#define HBG_REG_MDIO_RDATA_ADDR (HBG_REG_MDIO_BASE + 0x000C)
···
39
36
/* GMAC */
40
37
#define HBG_REG_SGMII_BASE 0x10000
41
38
#define HBG_REG_DUPLEX_TYPE_ADDR (HBG_REG_SGMII_BASE + 0x0008)
39
+
#define HBG_REG_FD_FC_TYPE_ADDR (HBG_REG_SGMII_BASE + 0x000C)
40
+
#define HBG_REG_FC_TX_TIMER_ADDR (HBG_REG_SGMII_BASE + 0x001C)
41
+
#define HBG_REG_FD_FC_ADDR_LOW_ADDR (HBG_REG_SGMII_BASE + 0x0020)
42
+
#define HBG_REG_FD_FC_ADDR_HIGH_ADDR (HBG_REG_SGMII_BASE + 0x0024)
42
43
#define HBG_REG_DUPLEX_B BIT(0)
43
44
#define HBG_REG_MAX_FRAME_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x003C)
44
45
#define HBG_REG_PORT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x0040)
···
50
43
#define HBG_REG_PORT_ENABLE_ADDR (HBG_REG_SGMII_BASE + 0x0044)
51
44
#define HBG_REG_PORT_ENABLE_RX_B BIT(1)
52
45
#define HBG_REG_PORT_ENABLE_TX_B BIT(2)
46
+
#define HBG_REG_PAUSE_ENABLE_ADDR (HBG_REG_SGMII_BASE + 0x0048)
47
+
#define HBG_REG_PAUSE_ENABLE_RX_B BIT(0)
48
+
#define HBG_REG_PAUSE_ENABLE_TX_B BIT(1)
49
+
#define HBG_REG_AN_NEG_STATE_ADDR (HBG_REG_SGMII_BASE + 0x0058)
53
50
#define HBG_REG_TRANSMIT_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x0060)
54
51
#define HBG_REG_TRANSMIT_CTRL_PAD_EN_B BIT(7)
55
52
#define HBG_REG_TRANSMIT_CTRL_CRC_ADD_B BIT(6)
56
53
#define HBG_REG_TRANSMIT_CTRL_AN_EN_B BIT(5)
54
+
#define HBG_REG_REC_FILT_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x0064)
55
+
#define HBG_REG_REC_FILT_CTRL_UC_MATCH_EN_B BIT(0)
56
+
#define HBG_REG_LINE_LOOP_BACK_ADDR (HBG_REG_SGMII_BASE + 0x01A8)
57
57
#define HBG_REG_CF_CRC_STRIP_ADDR (HBG_REG_SGMII_BASE + 0x01B0)
58
58
#define HBG_REG_CF_CRC_STRIP_B BIT(0)
59
59
#define HBG_REG_MODE_CHANGE_EN_ADDR (HBG_REG_SGMII_BASE + 0x01B4)
60
60
#define HBG_REG_MODE_CHANGE_EN_B BIT(0)
61
+
#define HBG_REG_LOOP_REG_ADDR (HBG_REG_SGMII_BASE + 0x01DC)
61
62
#define HBG_REG_RECV_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x01E0)
62
63
#define HBG_REG_RECV_CTRL_STRIP_PAD_EN_B BIT(3)
64
+
#define HBG_REG_VLAN_CODE_ADDR (HBG_REG_SGMII_BASE + 0x01E8)
65
+
#define HBG_REG_STATION_ADDR_LOW_0_ADDR (HBG_REG_SGMII_BASE + 0x0200)
66
+
#define HBG_REG_STATION_ADDR_HIGH_0_ADDR (HBG_REG_SGMII_BASE + 0x0204)
67
+
#define HBG_REG_STATION_ADDR_LOW_1_ADDR (HBG_REG_SGMII_BASE + 0x0208)
68
+
#define HBG_REG_STATION_ADDR_HIGH_1_ADDR (HBG_REG_SGMII_BASE + 0x020C)
63
69
#define HBG_REG_STATION_ADDR_LOW_2_ADDR (HBG_REG_SGMII_BASE + 0x0210)
64
70
#define HBG_REG_STATION_ADDR_HIGH_2_ADDR (HBG_REG_SGMII_BASE + 0x0214)
71
+
#define HBG_REG_STATION_ADDR_LOW_3_ADDR (HBG_REG_SGMII_BASE + 0x0218)
72
+
#define HBG_REG_STATION_ADDR_HIGH_3_ADDR (HBG_REG_SGMII_BASE + 0x021C)
73
+
#define HBG_REG_STATION_ADDR_LOW_4_ADDR (HBG_REG_SGMII_BASE + 0x0220)
74
+
#define HBG_REG_STATION_ADDR_HIGH_4_ADDR (HBG_REG_SGMII_BASE + 0x0224)
75
+
#define HBG_REG_STATION_ADDR_LOW_5_ADDR (HBG_REG_SGMII_BASE + 0x0228)
76
+
#define HBG_REG_STATION_ADDR_HIGH_5_ADDR (HBG_REG_SGMII_BASE + 0x022C)
65
77
66
78
/* PCU */
79
+
#define HBG_REG_TX_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0420)
80
+
#define HBG_REG_RX_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0424)
81
+
#define HBG_REG_CFG_FIFO_THRSLD_ADDR (HBG_REG_SGMII_BASE + 0x0428)
67
82
#define HBG_REG_CF_INTRPT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x042C)
68
83
#define HBG_INT_MSK_WE_ERR_B BIT(31)
69
84
#define HBG_INT_MSK_RBREQ_ERR_B BIT(30)
···
107
78
#define HBG_INT_MSK_RX_B BIT(0) /* just used in driver */
108
79
#define HBG_REG_CF_INTRPT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0434)
109
80
#define HBG_REG_CF_INTRPT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x0438)
81
+
#define HBG_REG_TX_BUS_ERR_ADDR_ADDR (HBG_REG_SGMII_BASE + 0x043C)
82
+
#define HBG_REG_RX_BUS_ERR_ADDR_ADDR (HBG_REG_SGMII_BASE + 0x0440)
110
83
#define HBG_REG_MAX_FRAME_LEN_ADDR (HBG_REG_SGMII_BASE + 0x0444)
111
84
#define HBG_REG_MAX_FRAME_LEN_M GENMASK(15, 0)
85
+
#define HBG_REG_DEBUG_ST_MCH_ADDR (HBG_REG_SGMII_BASE + 0x0450)
86
+
#define HBG_REG_FIFO_CURR_STATUS_ADDR (HBG_REG_SGMII_BASE + 0x0454)
87
+
#define HBG_REG_FIFO_HIST_STATUS_ADDR (HBG_REG_SGMII_BASE + 0x0458)
112
88
#define HBG_REG_CF_CFF_DATA_NUM_ADDR (HBG_REG_SGMII_BASE + 0x045C)
113
89
#define HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M GENMASK(8, 0)
114
90
#define HBG_REG_CF_CFF_DATA_NUM_ADDR_RX_M GENMASK(24, 16)
91
+
#define HBG_REG_CF_TX_PAUSE_ADDR (HBG_REG_SGMII_BASE + 0x0470)
115
92
#define HBG_REG_TX_CFF_ADDR_0_ADDR (HBG_REG_SGMII_BASE + 0x0488)
116
93
#define HBG_REG_TX_CFF_ADDR_1_ADDR (HBG_REG_SGMII_BASE + 0x048C)
117
94
#define HBG_REG_TX_CFF_ADDR_2_ADDR (HBG_REG_SGMII_BASE + 0x0490)
···
136
101
#define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE2_M GENMASK(3, 0)
137
102
#define HBG_REG_RX_PKT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x04F4)
138
103
#define HBG_REG_RX_PKT_MODE_PARSE_MODE_M GENMASK(22, 21)
104
+
#define HBG_REG_DBG_ST0_ADDR (HBG_REG_SGMII_BASE + 0x05E4)
105
+
#define HBG_REG_DBG_ST1_ADDR (HBG_REG_SGMII_BASE + 0x05E8)
106
+
#define HBG_REG_DBG_ST2_ADDR (HBG_REG_SGMII_BASE + 0x05EC)
107
+
#define HBG_REG_BUS_RST_EN_ADDR (HBG_REG_SGMII_BASE + 0x0688)
139
108
#define HBG_REG_CF_IND_TXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x0694)
140
109
#define HBG_REG_IND_INTR_MASK_B BIT(0)
141
110
#define HBG_REG_CF_IND_TXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0698)