Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info
The if-else monster is so unmaintainable that one case is repeated
twice. Get rid of it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611092/
[add missing entry to a615 catalog to resolve conflict]
Signed-off-by: Rob Clark <robdclark@chromium.org>
authored by
Konrad Dybcio
and committed by
Rob Clark
2bbb5fe3
1b3975ef
+21
-19
+15
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+15
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
···
636
636
.a6xx = &(const struct a6xx_info) {
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.hwcg = a612_hwcg,
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.protect = &a630_protect,
639
+
.prim_fifo_threshold = 0x00080000,
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640
},
640
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/*
641
642
* There are (at least) three SoCs implementing A610: SM6125
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a615_hwcg,
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.protect = &a630_protect,
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+
.prim_fifo_threshold = 0x0018000,
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},
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.speedbins = ADRENO_SPEEDBINS(
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672
/*
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a615_hwcg,
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.protect = &a630_protect,
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+
.prim_fifo_threshold = 0x00180000,
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},
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.speedbins = ADRENO_SPEEDBINS(
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{ 0, 0 },
···
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.init = a6xx_gpu_init,
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.a6xx = &(const struct a6xx_info) {
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.protect = &a630_protect,
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+
.prim_fifo_threshold = 0x00180000,
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},
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.speedbins = ADRENO_SPEEDBINS(
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{ 0, 0 },
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a615_hwcg,
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.protect = &a630_protect,
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+
.prim_fifo_threshold = 0x00018000,
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742
},
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.speedbins = ADRENO_SPEEDBINS(
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{ 0, 0 },
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a615_hwcg,
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.protect = &a630_protect,
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+
.prim_fifo_threshold = 0x00018000,
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},
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.speedbins = ADRENO_SPEEDBINS(
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{ 0, 0 },
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a615_hwcg,
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.protect = &a630_protect,
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+
.prim_fifo_threshold = 0x00018000,
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786
},
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.speedbins = ADRENO_SPEEDBINS(
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{ 0, 0 },
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a630_hwcg,
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.protect = &a630_protect,
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+
.prim_fifo_threshold = 0x00180000,
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},
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}, {
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.chip_ids = ADRENO_CHIP_IDS(0x06040001),
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a640_hwcg,
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828
.protect = &a630_protect,
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+
.prim_fifo_threshold = 0x00180000,
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},
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831
.speedbins = ADRENO_SPEEDBINS(
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{ 0, 0 },
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a650_hwcg,
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.protect = &a650_protect,
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+
.prim_fifo_threshold = 0x00300200,
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},
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.address_space_size = SZ_16G,
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.speedbins = ADRENO_SPEEDBINS(
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a660_hwcg,
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.protect = &a660_protect,
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+
.prim_fifo_threshold = 0x00300200,
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},
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.address_space_size = SZ_16G,
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}, {
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a660_hwcg,
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.protect = &a660_protect,
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+
.prim_fifo_threshold = 0x00200200,
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},
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.address_space_size = SZ_16G,
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.speedbins = ADRENO_SPEEDBINS(
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a640_hwcg,
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918
.protect = &a630_protect,
919
+
.prim_fifo_threshold = 0x00200200,
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},
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}, {
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.chip_ids = ADRENO_CHIP_IDS(0x06090000),
···
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.a6xx = &(const struct a6xx_info) {
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.hwcg = a690_hwcg,
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935
.protect = &a690_protect,
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+
.prim_fifo_threshold = 0x00800200,
949
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},
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.address_space_size = SZ_16G,
951
939
}
···
1207
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.a6xx = &(const struct a6xx_info) {
1208
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.hwcg = a702_hwcg,
1209
1195
.protect = &a650_protect,
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+
.prim_fifo_threshold = 0x0000c000,
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},
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.speedbins = ADRENO_SPEEDBINS(
1212
1199
{ 0, 0 },
+5
-19
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+5
-19
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
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} else if (!adreno_is_a7xx(adreno_gpu))
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gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
983
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984
-
/* Setting the primFifo thresholds default values,
985
-
* and vccCacheSkipDis=1 bit (0x200) for A640 and newer
986
-
*/
987
-
if (adreno_is_a702(adreno_gpu))
988
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0000c000);
989
-
else if (adreno_is_a690(adreno_gpu))
990
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200);
991
-
else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
992
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
993
-
else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
994
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
995
-
else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
996
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
997
-
else if (adreno_is_a619(adreno_gpu))
998
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000);
999
-
else if (adreno_is_a610(adreno_gpu))
1000
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000);
1001
-
else if (!adreno_is_a7xx(adreno_gpu))
1002
-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
984
+
985
+
/* Set the default primFifo threshold values */
986
+
if (adreno_gpu->info->a6xx->prim_fifo_threshold)
987
+
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL,
988
+
adreno_gpu->info->a6xx->prim_fifo_threshold);
1003
989
1004
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/* Set the AHB default slave response to "ERROR" */
1005
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gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);