Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'ib-mfd-net-pinctrl-v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Lee Jones says:
====================
Immutable branch between MFD, Net and Pinctrl due for the v6.0 merge window
* tag 'ib-mfd-net-pinctrl-v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd:
mfd: ocelot: Add support for the vsc7512 chip via spi
dt-bindings: mfd: ocelot: Add bindings for VSC7512
resource: add define macro for register address resources
pinctrl: microchip-sgpio: add ability to be used in a non-mmio configuration
pinctrl: microchip-sgpio: allow sgpio driver to be used as a module
pinctrl: ocelot: add ability to be used in a non-mmio configuration
net: mdio: mscc-miim: add ability to be used in a non-mmio configuration
mfd: ocelot: Add helper to get regmap from a resource
====================
Link: https://lore.kernel.org/r/YxrjyHcceLOFlT/c@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+795
-49
+160
Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
+160
Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Ocelot Externally-Controlled Ethernet Switch
8
+
9
+
maintainers:
10
+
- Colin Foster <colin.foster@in-advantage.com>
11
+
12
+
description: |
13
+
The Ocelot ethernet switch family contains chips that have an internal CPU
14
+
(VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
15
+
the option to be controlled externally, which is the purpose of this driver.
16
+
17
+
The switch family is a multi-port networking switch that supports many
18
+
interfaces. Additionally, the device can perform pin control, MDIO buses, and
19
+
external GPIO expanders.
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- mscc,vsc7512
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
"#address-cells":
30
+
const: 1
31
+
32
+
"#size-cells":
33
+
const: 1
34
+
35
+
spi-max-frequency:
36
+
maxItems: 1
37
+
38
+
patternProperties:
39
+
"^pinctrl@[0-9a-f]+$":
40
+
type: object
41
+
$ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
42
+
43
+
"^gpio@[0-9a-f]+$":
44
+
type: object
45
+
$ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
46
+
properties:
47
+
compatible:
48
+
enum:
49
+
- mscc,ocelot-sgpio
50
+
51
+
"^mdio@[0-9a-f]+$":
52
+
type: object
53
+
$ref: /schemas/net/mscc,miim.yaml
54
+
properties:
55
+
compatible:
56
+
enum:
57
+
- mscc,ocelot-miim
58
+
59
+
required:
60
+
- compatible
61
+
- reg
62
+
- '#address-cells'
63
+
- '#size-cells'
64
+
- spi-max-frequency
65
+
66
+
additionalProperties: false
67
+
68
+
examples:
69
+
- |
70
+
ocelot_clock: ocelot-clock {
71
+
compatible = "fixed-clock";
72
+
#clock-cells = <0>;
73
+
clock-frequency = <125000000>;
74
+
};
75
+
76
+
spi {
77
+
#address-cells = <1>;
78
+
#size-cells = <0>;
79
+
80
+
soc@0 {
81
+
compatible = "mscc,vsc7512";
82
+
spi-max-frequency = <2500000>;
83
+
reg = <0>;
84
+
#address-cells = <1>;
85
+
#size-cells = <1>;
86
+
87
+
mdio@7107009c {
88
+
compatible = "mscc,ocelot-miim";
89
+
#address-cells = <1>;
90
+
#size-cells = <0>;
91
+
reg = <0x7107009c 0x24>;
92
+
93
+
sw_phy0: ethernet-phy@0 {
94
+
reg = <0x0>;
95
+
};
96
+
};
97
+
98
+
mdio@710700c0 {
99
+
compatible = "mscc,ocelot-miim";
100
+
pinctrl-names = "default";
101
+
pinctrl-0 = <&miim1_pins>;
102
+
#address-cells = <1>;
103
+
#size-cells = <0>;
104
+
reg = <0x710700c0 0x24>;
105
+
106
+
sw_phy4: ethernet-phy@4 {
107
+
reg = <0x4>;
108
+
};
109
+
};
110
+
111
+
gpio: pinctrl@71070034 {
112
+
compatible = "mscc,ocelot-pinctrl";
113
+
gpio-controller;
114
+
#gpio-cells = <2>;
115
+
gpio-ranges = <&gpio 0 0 22>;
116
+
reg = <0x71070034 0x6c>;
117
+
118
+
sgpio_pins: sgpio-pins {
119
+
pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
120
+
function = "sg0";
121
+
};
122
+
123
+
miim1_pins: miim1-pins {
124
+
pins = "GPIO_14", "GPIO_15";
125
+
function = "miim";
126
+
};
127
+
};
128
+
129
+
gpio@710700f8 {
130
+
compatible = "mscc,ocelot-sgpio";
131
+
#address-cells = <1>;
132
+
#size-cells = <0>;
133
+
bus-frequency = <12500000>;
134
+
clocks = <&ocelot_clock>;
135
+
microchip,sgpio-port-ranges = <0 15>;
136
+
pinctrl-names = "default";
137
+
pinctrl-0 = <&sgpio_pins>;
138
+
reg = <0x710700f8 0x100>;
139
+
140
+
sgpio_in0: gpio@0 {
141
+
compatible = "microchip,sparx5-sgpio-bank";
142
+
reg = <0>;
143
+
gpio-controller;
144
+
#gpio-cells = <3>;
145
+
ngpios = <64>;
146
+
};
147
+
148
+
sgpio_out1: gpio@1 {
149
+
compatible = "microchip,sparx5-sgpio-bank";
150
+
reg = <1>;
151
+
gpio-controller;
152
+
#gpio-cells = <3>;
153
+
ngpios = <64>;
154
+
};
155
+
};
156
+
};
157
+
};
158
+
159
+
...
160
+
+7
MAINTAINERS
+7
MAINTAINERS
···
14746
14746
F: net/dsa/tag_ocelot_8021q.c
14747
14747
F: tools/testing/selftests/drivers/net/ocelot/*
14748
14748
14749
+
OCELOT EXTERNAL SWITCH CONTROL
14750
+
M: Colin Foster <colin.foster@in-advantage.com>
14751
+
S: Supported
14752
+
F: Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
14753
+
F: drivers/mfd/ocelot*
14754
+
F: include/linux/mfd/ocelot.h
14755
+
14749
14756
OCXL (Open Coherent Accelerator Processor Interface OpenCAPI) DRIVER
14750
14757
M: Frederic Barrat <fbarrat@linux.ibm.com>
14751
14758
M: Andrew Donnellan <ajd@linux.ibm.com>
+21
drivers/mfd/Kconfig
+21
drivers/mfd/Kconfig
···
963
963
This driver can also be built as a module. If so the module
964
964
will be called menf21bmc.
965
965
966
+
config MFD_OCELOT
967
+
tristate "Microsemi Ocelot External Control Support"
968
+
depends on SPI_MASTER
969
+
select MFD_CORE
970
+
select REGMAP_SPI
971
+
help
972
+
Ocelot is a family of networking chips that support multiple ethernet
973
+
and fibre interfaces. In addition to networking, they contain several
974
+
other functions, including pinctrl, MDIO, and communication with
975
+
external chips. While some chips have an internal processor capable of
976
+
running an OS, others don't. All chips can be controlled externally
977
+
through different interfaces, including SPI, I2C, and PCIe.
978
+
979
+
Say yes here to add support for Ocelot chips (VSC7511, VSC7512,
980
+
VSC7513, VSC7514) controlled externally.
981
+
982
+
To compile this driver as a module, choose M here: the module will be
983
+
called ocelot-soc.
984
+
985
+
If unsure, say N.
986
+
966
987
config EZX_PCAP
967
988
bool "Motorola EZXPCAP Support"
968
989
depends on SPI_MASTER
+3
drivers/mfd/Makefile
+3
drivers/mfd/Makefile
+161
drivers/mfd/ocelot-core.c
+161
drivers/mfd/ocelot-core.c
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
/*
3
+
* Core driver for the Ocelot chip family.
4
+
*
5
+
* The VSC7511, 7512, 7513, and 7514 can be controlled internally via an
6
+
* on-chip MIPS processor, or externally via SPI, I2C, PCIe. This core driver is
7
+
* intended to be the bus-agnostic glue between, for example, the SPI bus and
8
+
* the child devices.
9
+
*
10
+
* Copyright 2021-2022 Innovative Advantage Inc.
11
+
*
12
+
* Author: Colin Foster <colin.foster@in-advantage.com>
13
+
*/
14
+
15
+
#include <linux/bits.h>
16
+
#include <linux/device.h>
17
+
#include <linux/export.h>
18
+
#include <linux/iopoll.h>
19
+
#include <linux/ioport.h>
20
+
#include <linux/kernel.h>
21
+
#include <linux/mfd/core.h>
22
+
#include <linux/mfd/ocelot.h>
23
+
#include <linux/module.h>
24
+
#include <linux/regmap.h>
25
+
#include <linux/types.h>
26
+
27
+
#include <soc/mscc/ocelot.h>
28
+
29
+
#include "ocelot.h"
30
+
31
+
#define REG_GCB_SOFT_RST 0x0008
32
+
33
+
#define BIT_SOFT_CHIP_RST BIT(0)
34
+
35
+
#define VSC7512_MIIM0_RES_START 0x7107009c
36
+
#define VSC7512_MIIM1_RES_START 0x710700c0
37
+
#define VSC7512_MIIM_RES_SIZE 0x024
38
+
39
+
#define VSC7512_PHY_RES_START 0x710700f0
40
+
#define VSC7512_PHY_RES_SIZE 0x004
41
+
42
+
#define VSC7512_GPIO_RES_START 0x71070034
43
+
#define VSC7512_GPIO_RES_SIZE 0x06c
44
+
45
+
#define VSC7512_SIO_CTRL_RES_START 0x710700f8
46
+
#define VSC7512_SIO_CTRL_RES_SIZE 0x100
47
+
48
+
#define VSC7512_GCB_RST_SLEEP_US 100
49
+
#define VSC7512_GCB_RST_TIMEOUT_US 100000
50
+
51
+
static int ocelot_gcb_chip_rst_status(struct ocelot_ddata *ddata)
52
+
{
53
+
int val, err;
54
+
55
+
err = regmap_read(ddata->gcb_regmap, REG_GCB_SOFT_RST, &val);
56
+
if (err)
57
+
return err;
58
+
59
+
return val;
60
+
}
61
+
62
+
int ocelot_chip_reset(struct device *dev)
63
+
{
64
+
struct ocelot_ddata *ddata = dev_get_drvdata(dev);
65
+
int ret, val;
66
+
67
+
/*
68
+
* Reset the entire chip here to put it into a completely known state.
69
+
* Other drivers may want to reset their own subsystems. The register
70
+
* self-clears, so one write is all that is needed and wait for it to
71
+
* clear.
72
+
*/
73
+
ret = regmap_write(ddata->gcb_regmap, REG_GCB_SOFT_RST, BIT_SOFT_CHIP_RST);
74
+
if (ret)
75
+
return ret;
76
+
77
+
return readx_poll_timeout(ocelot_gcb_chip_rst_status, ddata, val, !val,
78
+
VSC7512_GCB_RST_SLEEP_US, VSC7512_GCB_RST_TIMEOUT_US);
79
+
}
80
+
EXPORT_SYMBOL_NS(ocelot_chip_reset, MFD_OCELOT);
81
+
82
+
static const struct resource vsc7512_miim0_resources[] = {
83
+
DEFINE_RES_REG_NAMED(VSC7512_MIIM0_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim0"),
84
+
DEFINE_RES_REG_NAMED(VSC7512_PHY_RES_START, VSC7512_PHY_RES_SIZE, "gcb_phy"),
85
+
};
86
+
87
+
static const struct resource vsc7512_miim1_resources[] = {
88
+
DEFINE_RES_REG_NAMED(VSC7512_MIIM1_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim1"),
89
+
};
90
+
91
+
static const struct resource vsc7512_pinctrl_resources[] = {
92
+
DEFINE_RES_REG_NAMED(VSC7512_GPIO_RES_START, VSC7512_GPIO_RES_SIZE, "gcb_gpio"),
93
+
};
94
+
95
+
static const struct resource vsc7512_sgpio_resources[] = {
96
+
DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"),
97
+
};
98
+
99
+
static const struct mfd_cell vsc7512_devs[] = {
100
+
{
101
+
.name = "ocelot-pinctrl",
102
+
.of_compatible = "mscc,ocelot-pinctrl",
103
+
.num_resources = ARRAY_SIZE(vsc7512_pinctrl_resources),
104
+
.resources = vsc7512_pinctrl_resources,
105
+
}, {
106
+
.name = "ocelot-sgpio",
107
+
.of_compatible = "mscc,ocelot-sgpio",
108
+
.num_resources = ARRAY_SIZE(vsc7512_sgpio_resources),
109
+
.resources = vsc7512_sgpio_resources,
110
+
}, {
111
+
.name = "ocelot-miim0",
112
+
.of_compatible = "mscc,ocelot-miim",
113
+
.of_reg = VSC7512_MIIM0_RES_START,
114
+
.use_of_reg = true,
115
+
.num_resources = ARRAY_SIZE(vsc7512_miim0_resources),
116
+
.resources = vsc7512_miim0_resources,
117
+
}, {
118
+
.name = "ocelot-miim1",
119
+
.of_compatible = "mscc,ocelot-miim",
120
+
.of_reg = VSC7512_MIIM1_RES_START,
121
+
.use_of_reg = true,
122
+
.num_resources = ARRAY_SIZE(vsc7512_miim1_resources),
123
+
.resources = vsc7512_miim1_resources,
124
+
},
125
+
};
126
+
127
+
static void ocelot_core_try_add_regmap(struct device *dev,
128
+
const struct resource *res)
129
+
{
130
+
if (dev_get_regmap(dev, res->name))
131
+
return;
132
+
133
+
ocelot_spi_init_regmap(dev, res);
134
+
}
135
+
136
+
static void ocelot_core_try_add_regmaps(struct device *dev,
137
+
const struct mfd_cell *cell)
138
+
{
139
+
int i;
140
+
141
+
for (i = 0; i < cell->num_resources; i++)
142
+
ocelot_core_try_add_regmap(dev, &cell->resources[i]);
143
+
}
144
+
145
+
int ocelot_core_init(struct device *dev)
146
+
{
147
+
int i, ndevs;
148
+
149
+
ndevs = ARRAY_SIZE(vsc7512_devs);
150
+
151
+
for (i = 0; i < ndevs; i++)
152
+
ocelot_core_try_add_regmaps(dev, &vsc7512_devs[i]);
153
+
154
+
return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs, ndevs, NULL, 0, NULL);
155
+
}
156
+
EXPORT_SYMBOL_NS(ocelot_core_init, MFD_OCELOT);
157
+
158
+
MODULE_DESCRIPTION("Externally Controlled Ocelot Chip Driver");
159
+
MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
160
+
MODULE_LICENSE("GPL");
161
+
MODULE_IMPORT_NS(MFD_OCELOT_SPI);
+299
drivers/mfd/ocelot-spi.c
+299
drivers/mfd/ocelot-spi.c
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
/*
3
+
* SPI core driver for the Ocelot chip family.
4
+
*
5
+
* This driver will handle everything necessary to allow for communication over
6
+
* SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions
7
+
* are to prepare the chip's SPI interface for a specific bus speed, and a host
8
+
* processor's endianness. This will create and distribute regmaps for any
9
+
* children.
10
+
*
11
+
* Copyright 2021-2022 Innovative Advantage Inc.
12
+
*
13
+
* Author: Colin Foster <colin.foster@in-advantage.com>
14
+
*/
15
+
16
+
#include <linux/device.h>
17
+
#include <linux/err.h>
18
+
#include <linux/errno.h>
19
+
#include <linux/export.h>
20
+
#include <linux/ioport.h>
21
+
#include <linux/mod_devicetable.h>
22
+
#include <linux/module.h>
23
+
#include <linux/regmap.h>
24
+
#include <linux/spi/spi.h>
25
+
#include <linux/types.h>
26
+
#include <linux/units.h>
27
+
28
+
#include "ocelot.h"
29
+
30
+
#define REG_DEV_CPUORG_IF_CTRL 0x0000
31
+
#define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
32
+
33
+
#define CFGSTAT_IF_NUM_VCORE (0 << 24)
34
+
#define CFGSTAT_IF_NUM_VRAP (1 << 24)
35
+
#define CFGSTAT_IF_NUM_SI (2 << 24)
36
+
#define CFGSTAT_IF_NUM_MIIM (3 << 24)
37
+
38
+
#define VSC7512_DEVCPU_ORG_RES_START 0x71000000
39
+
#define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
40
+
41
+
#define VSC7512_CHIP_REGS_RES_START 0x71070000
42
+
#define VSC7512_CHIP_REGS_RES_SIZE 0x14
43
+
44
+
static const struct resource vsc7512_dev_cpuorg_resource =
45
+
DEFINE_RES_REG_NAMED(VSC7512_DEVCPU_ORG_RES_START,
46
+
VSC7512_DEVCPU_ORG_RES_SIZE,
47
+
"devcpu_org");
48
+
49
+
static const struct resource vsc7512_gcb_resource =
50
+
DEFINE_RES_REG_NAMED(VSC7512_CHIP_REGS_RES_START,
51
+
VSC7512_CHIP_REGS_RES_SIZE,
52
+
"devcpu_gcb_chip_regs");
53
+
54
+
static int ocelot_spi_initialize(struct device *dev)
55
+
{
56
+
struct ocelot_ddata *ddata = dev_get_drvdata(dev);
57
+
u32 val, check;
58
+
int err;
59
+
60
+
val = OCELOT_SPI_BYTE_ORDER;
61
+
62
+
/*
63
+
* The SPI address must be big-endian, but we want the payload to match
64
+
* our CPU. These are two bits (0 and 1) but they're repeated such that
65
+
* the write from any configuration will be valid. The four
66
+
* configurations are:
67
+
*
68
+
* 0b00: little-endian, MSB first
69
+
* | 111111 | 22221111 | 33222222 |
70
+
* | 76543210 | 54321098 | 32109876 | 10987654 |
71
+
*
72
+
* 0b01: big-endian, MSB first
73
+
* | 33222222 | 22221111 | 111111 | |
74
+
* | 10987654 | 32109876 | 54321098 | 76543210 |
75
+
*
76
+
* 0b10: little-endian, LSB first
77
+
* | 111111 | 11112222 | 22222233 |
78
+
* | 01234567 | 89012345 | 67890123 | 45678901 |
79
+
*
80
+
* 0b11: big-endian, LSB first
81
+
* | 22222233 | 11112222 | 111111 | |
82
+
* | 45678901 | 67890123 | 89012345 | 01234567 |
83
+
*/
84
+
err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CTRL, val);
85
+
if (err)
86
+
return err;
87
+
88
+
/*
89
+
* Apply the number of padding bytes between a read request and the data
90
+
* payload. Some registers have access times of up to 1us, so if the
91
+
* first payload bit is shifted out too quickly, the read will fail.
92
+
*/
93
+
val = ddata->spi_padding_bytes;
94
+
err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, val);
95
+
if (err)
96
+
return err;
97
+
98
+
/*
99
+
* After we write the interface configuration, read it back here. This
100
+
* will verify several different things. The first is that the number of
101
+
* padding bytes actually got written correctly. These are found in bits
102
+
* 0:3.
103
+
*
104
+
* The second is that bit 16 is cleared. Bit 16 is IF_CFGSTAT:IF_STAT,
105
+
* and will be set if the register access is too fast. This would be in
106
+
* the condition that the number of padding bytes is insufficient for
107
+
* the SPI bus frequency.
108
+
*
109
+
* The last check is for bits 31:24, which define the interface by which
110
+
* the registers are being accessed. Since we're accessing them via the
111
+
* serial interface, it must return IF_NUM_SI.
112
+
*/
113
+
check = val | CFGSTAT_IF_NUM_SI;
114
+
115
+
err = regmap_read(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, &val);
116
+
if (err)
117
+
return err;
118
+
119
+
if (check != val)
120
+
return -ENODEV;
121
+
122
+
return 0;
123
+
}
124
+
125
+
static const struct regmap_config ocelot_spi_regmap_config = {
126
+
.reg_bits = 24,
127
+
.reg_stride = 4,
128
+
.reg_downshift = 2,
129
+
.val_bits = 32,
130
+
131
+
.write_flag_mask = 0x80,
132
+
133
+
.use_single_write = true,
134
+
.can_multi_write = false,
135
+
136
+
.reg_format_endian = REGMAP_ENDIAN_BIG,
137
+
.val_format_endian = REGMAP_ENDIAN_NATIVE,
138
+
};
139
+
140
+
static int ocelot_spi_regmap_bus_read(void *context, const void *reg, size_t reg_size,
141
+
void *val, size_t val_size)
142
+
{
143
+
struct spi_transfer xfers[3] = {0};
144
+
struct device *dev = context;
145
+
struct ocelot_ddata *ddata;
146
+
struct spi_device *spi;
147
+
struct spi_message msg;
148
+
unsigned int index = 0;
149
+
150
+
ddata = dev_get_drvdata(dev);
151
+
spi = to_spi_device(dev);
152
+
153
+
xfers[index].tx_buf = reg;
154
+
xfers[index].len = reg_size;
155
+
index++;
156
+
157
+
if (ddata->spi_padding_bytes) {
158
+
xfers[index].len = ddata->spi_padding_bytes;
159
+
xfers[index].tx_buf = ddata->dummy_buf;
160
+
xfers[index].dummy_data = 1;
161
+
index++;
162
+
}
163
+
164
+
xfers[index].rx_buf = val;
165
+
xfers[index].len = val_size;
166
+
index++;
167
+
168
+
spi_message_init_with_transfers(&msg, xfers, index);
169
+
170
+
return spi_sync(spi, &msg);
171
+
}
172
+
173
+
static int ocelot_spi_regmap_bus_write(void *context, const void *data, size_t count)
174
+
{
175
+
struct device *dev = context;
176
+
struct spi_device *spi = to_spi_device(dev);
177
+
178
+
return spi_write(spi, data, count);
179
+
}
180
+
181
+
static const struct regmap_bus ocelot_spi_regmap_bus = {
182
+
.write = ocelot_spi_regmap_bus_write,
183
+
.read = ocelot_spi_regmap_bus_read,
184
+
};
185
+
186
+
struct regmap *ocelot_spi_init_regmap(struct device *dev, const struct resource *res)
187
+
{
188
+
struct regmap_config regmap_config;
189
+
190
+
memcpy(®map_config, &ocelot_spi_regmap_config, sizeof(regmap_config));
191
+
192
+
regmap_config.name = res->name;
193
+
regmap_config.max_register = resource_size(res) - 1;
194
+
regmap_config.reg_base = res->start;
195
+
196
+
return devm_regmap_init(dev, &ocelot_spi_regmap_bus, dev, ®map_config);
197
+
}
198
+
EXPORT_SYMBOL_NS(ocelot_spi_init_regmap, MFD_OCELOT_SPI);
199
+
200
+
static int ocelot_spi_probe(struct spi_device *spi)
201
+
{
202
+
struct device *dev = &spi->dev;
203
+
struct ocelot_ddata *ddata;
204
+
struct regmap *r;
205
+
int err;
206
+
207
+
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
208
+
if (!ddata)
209
+
return -ENOMEM;
210
+
211
+
spi_set_drvdata(spi, ddata);
212
+
213
+
if (spi->max_speed_hz <= 500000) {
214
+
ddata->spi_padding_bytes = 0;
215
+
} else {
216
+
/*
217
+
* Calculation taken from the manual for IF_CFGSTAT:IF_CFG.
218
+
* Register access time is 1us, so we need to configure and send
219
+
* out enough padding bytes between the read request and data
220
+
* transmission that lasts at least 1 microsecond.
221
+
*/
222
+
ddata->spi_padding_bytes = 1 + (spi->max_speed_hz / HZ_PER_MHZ + 2) / 8;
223
+
224
+
ddata->dummy_buf = devm_kzalloc(dev, ddata->spi_padding_bytes, GFP_KERNEL);
225
+
if (!ddata->dummy_buf)
226
+
return -ENOMEM;
227
+
}
228
+
229
+
spi->bits_per_word = 8;
230
+
231
+
err = spi_setup(spi);
232
+
if (err)
233
+
return dev_err_probe(&spi->dev, err, "Error performing SPI setup\n");
234
+
235
+
r = ocelot_spi_init_regmap(dev, &vsc7512_dev_cpuorg_resource);
236
+
if (IS_ERR(r))
237
+
return PTR_ERR(r);
238
+
239
+
ddata->cpuorg_regmap = r;
240
+
241
+
r = ocelot_spi_init_regmap(dev, &vsc7512_gcb_resource);
242
+
if (IS_ERR(r))
243
+
return PTR_ERR(r);
244
+
245
+
ddata->gcb_regmap = r;
246
+
247
+
/*
248
+
* The chip must be set up for SPI before it gets initialized and reset.
249
+
* This must be done before calling init, and after a chip reset is
250
+
* performed.
251
+
*/
252
+
err = ocelot_spi_initialize(dev);
253
+
if (err)
254
+
return dev_err_probe(dev, err, "Error initializing SPI bus\n");
255
+
256
+
err = ocelot_chip_reset(dev);
257
+
if (err)
258
+
return dev_err_probe(dev, err, "Error resetting device\n");
259
+
260
+
/*
261
+
* A chip reset will clear the SPI configuration, so it needs to be done
262
+
* again before we can access any registers.
263
+
*/
264
+
err = ocelot_spi_initialize(dev);
265
+
if (err)
266
+
return dev_err_probe(dev, err, "Error initializing SPI bus after reset\n");
267
+
268
+
err = ocelot_core_init(dev);
269
+
if (err)
270
+
return dev_err_probe(dev, err, "Error initializing Ocelot core\n");
271
+
272
+
return 0;
273
+
}
274
+
275
+
static const struct spi_device_id ocelot_spi_ids[] = {
276
+
{ "vsc7512", 0 },
277
+
{ }
278
+
};
279
+
280
+
static const struct of_device_id ocelot_spi_of_match[] = {
281
+
{ .compatible = "mscc,vsc7512" },
282
+
{ }
283
+
};
284
+
MODULE_DEVICE_TABLE(of, ocelot_spi_of_match);
285
+
286
+
static struct spi_driver ocelot_spi_driver = {
287
+
.driver = {
288
+
.name = "ocelot-soc",
289
+
.of_match_table = ocelot_spi_of_match,
290
+
},
291
+
.id_table = ocelot_spi_ids,
292
+
.probe = ocelot_spi_probe,
293
+
};
294
+
module_spi_driver(ocelot_spi_driver);
295
+
296
+
MODULE_DESCRIPTION("SPI Controlled Ocelot Chip Driver");
297
+
MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
298
+
MODULE_LICENSE("Dual MIT/GPL");
299
+
MODULE_IMPORT_NS(MFD_OCELOT);
+49
drivers/mfd/ocelot.h
+49
drivers/mfd/ocelot.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
+
/* Copyright 2021, 2022 Innovative Advantage Inc. */
3
+
4
+
#ifndef _MFD_OCELOT_H
5
+
#define _MFD_OCELOT_H
6
+
7
+
#include <linux/kconfig.h>
8
+
9
+
struct device;
10
+
struct regmap;
11
+
struct resource;
12
+
13
+
/**
14
+
* struct ocelot_ddata - Private data for an external Ocelot chip
15
+
* @gcb_regmap: General Configuration Block regmap. Used for
16
+
* operations like chip reset.
17
+
* @cpuorg_regmap: CPU Device Origin Block regmap. Used for operations
18
+
* like SPI bus configuration.
19
+
* @spi_padding_bytes: Number of padding bytes that must be thrown out before
20
+
* read data gets returned. This is calculated during
21
+
* initialization based on bus speed.
22
+
* @dummy_buf: Zero-filled buffer of spi_padding_bytes size. The dummy
23
+
* bytes that will be sent out between the address and
24
+
* data of a SPI read operation.
25
+
*/
26
+
struct ocelot_ddata {
27
+
struct regmap *gcb_regmap;
28
+
struct regmap *cpuorg_regmap;
29
+
int spi_padding_bytes;
30
+
void *dummy_buf;
31
+
};
32
+
33
+
int ocelot_chip_reset(struct device *dev);
34
+
int ocelot_core_init(struct device *dev);
35
+
36
+
/* SPI-specific routines that won't be necessary for other interfaces */
37
+
struct regmap *ocelot_spi_init_regmap(struct device *dev,
38
+
const struct resource *res);
39
+
40
+
#define OCELOT_SPI_BYTE_ORDER_LE 0x00000000
41
+
#define OCELOT_SPI_BYTE_ORDER_BE 0x81818181
42
+
43
+
#ifdef __LITTLE_ENDIAN
44
+
#define OCELOT_SPI_BYTE_ORDER OCELOT_SPI_BYTE_ORDER_LE
45
+
#else
46
+
#define OCELOT_SPI_BYTE_ORDER OCELOT_SPI_BYTE_ORDER_BE
47
+
#endif
48
+
49
+
#endif
+12
-30
drivers/net/mdio/mdio-mscc-miim.c
+12
-30
drivers/net/mdio/mdio-mscc-miim.c
···
12
12
#include <linux/iopoll.h>
13
13
#include <linux/kernel.h>
14
14
#include <linux/mdio/mdio-mscc-miim.h>
15
+
#include <linux/mfd/ocelot.h>
15
16
#include <linux/module.h>
16
17
#include <linux/of_mdio.h>
17
18
#include <linux/phy.h>
···
271
270
272
271
static int mscc_miim_probe(struct platform_device *pdev)
273
272
{
274
-
struct regmap *mii_regmap, *phy_regmap = NULL;
275
273
struct device_node *np = pdev->dev.of_node;
274
+
struct regmap *mii_regmap, *phy_regmap;
276
275
struct device *dev = &pdev->dev;
277
-
void __iomem *regs, *phy_regs;
278
276
struct mscc_miim_dev *miim;
279
-
struct resource *res;
280
277
struct mii_bus *bus;
281
278
int ret;
282
279
283
-
regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
284
-
if (IS_ERR(regs)) {
285
-
dev_err(dev, "Unable to map MIIM registers\n");
286
-
return PTR_ERR(regs);
287
-
}
288
-
289
-
mii_regmap = devm_regmap_init_mmio(dev, regs, &mscc_miim_regmap_config);
290
-
291
-
if (IS_ERR(mii_regmap)) {
292
-
dev_err(dev, "Unable to create MIIM regmap\n");
293
-
return PTR_ERR(mii_regmap);
294
-
}
280
+
mii_regmap = ocelot_regmap_from_resource(pdev, 0,
281
+
&mscc_miim_regmap_config);
282
+
if (IS_ERR(mii_regmap))
283
+
return dev_err_probe(dev, PTR_ERR(mii_regmap),
284
+
"Unable to create MIIM regmap\n");
295
285
296
286
/* This resource is optional */
297
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
298
-
if (res) {
299
-
phy_regs = devm_ioremap_resource(dev, res);
300
-
if (IS_ERR(phy_regs)) {
301
-
dev_err(dev, "Unable to map internal phy registers\n");
302
-
return PTR_ERR(phy_regs);
303
-
}
304
-
305
-
phy_regmap = devm_regmap_init_mmio(dev, phy_regs,
306
-
&mscc_miim_phy_regmap_config);
307
-
if (IS_ERR(phy_regmap)) {
308
-
dev_err(dev, "Unable to create phy register regmap\n");
309
-
return PTR_ERR(phy_regmap);
310
-
}
311
-
}
287
+
phy_regmap = ocelot_regmap_from_resource_optional(pdev, 1,
288
+
&mscc_miim_phy_regmap_config);
289
+
if (IS_ERR(phy_regmap))
290
+
return dev_err_probe(dev, PTR_ERR(phy_regmap),
291
+
"Unable to create phy register regmap\n");
312
292
313
293
ret = mscc_miim_setup(dev, &bus, "mscc_miim", mii_regmap, 0);
314
294
if (ret < 0) {
+4
-1
drivers/pinctrl/Kconfig
+4
-1
drivers/pinctrl/Kconfig
···
292
292
corresponding interrupt-controller.
293
293
294
294
config PINCTRL_MICROCHIP_SGPIO
295
-
bool "Pinctrl driver for Microsemi/Microchip Serial GPIO"
295
+
tristate "Pinctrl driver for Microsemi/Microchip Serial GPIO"
296
296
depends on OF
297
297
depends on HAS_IOMEM
298
298
select GPIOLIB
···
309
309
device. The primary purpose of the SIO controller is to
310
310
connect control signals from SFP modules and to act as an
311
311
LED controller.
312
+
313
+
If compiled as a module, the module name will be
314
+
pinctrl-microchip-sgpio.
312
315
313
316
config PINCTRL_OCELOT
314
317
tristate "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
+7
-7
drivers/pinctrl/pinctrl-microchip-sgpio.c
+7
-7
drivers/pinctrl/pinctrl-microchip-sgpio.c
···
12
12
#include <linux/clk.h>
13
13
#include <linux/gpio/driver.h>
14
14
#include <linux/io.h>
15
+
#include <linux/mfd/ocelot.h>
15
16
#include <linux/mod_devicetable.h>
16
17
#include <linux/module.h>
17
18
#include <linux/pinctrl/pinmux.h>
···
905
904
struct reset_control *reset;
906
905
struct sgpio_priv *priv;
907
906
struct clk *clk;
908
-
u32 __iomem *regs;
909
907
u32 val;
910
908
struct regmap_config regmap_config = {
911
909
.reg_bits = 32,
···
937
937
return -EINVAL;
938
938
}
939
939
940
-
regs = devm_platform_ioremap_resource(pdev, 0);
941
-
if (IS_ERR(regs))
942
-
return PTR_ERR(regs);
943
-
944
-
priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config);
940
+
priv->regs = ocelot_regmap_from_resource(pdev, 0, ®map_config);
945
941
if (IS_ERR(priv->regs))
946
942
return PTR_ERR(priv->regs);
947
943
···
995
999
/* sentinel */
996
1000
}
997
1001
};
1002
+
MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match);
998
1003
999
1004
static struct platform_driver microchip_sgpio_pinctrl_driver = {
1000
1005
.driver = {
···
1005
1008
},
1006
1009
.probe = microchip_sgpio_probe,
1007
1010
};
1008
-
builtin_platform_driver(microchip_sgpio_pinctrl_driver);
1011
+
module_platform_driver(microchip_sgpio_pinctrl_driver);
1012
+
1013
+
MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver");
1014
+
MODULE_LICENSE("GPL");
+5
-11
drivers/pinctrl/pinctrl-ocelot.c
+5
-11
drivers/pinctrl/pinctrl-ocelot.c
···
10
10
#include <linux/gpio/driver.h>
11
11
#include <linux/interrupt.h>
12
12
#include <linux/io.h>
13
+
#include <linux/mfd/ocelot.h>
13
14
#include <linux/of_device.h>
14
15
#include <linux/of_irq.h>
15
16
#include <linux/of_platform.h>
···
1976
1975
struct ocelot_pinctrl *info;
1977
1976
struct reset_control *reset;
1978
1977
struct regmap *pincfg;
1979
-
void __iomem *base;
1980
1978
int ret;
1981
1979
struct regmap_config regmap_config = {
1982
1980
.reg_bits = 32,
···
2004
2004
"Failed to get reset\n");
2005
2005
reset_control_reset(reset);
2006
2006
2007
-
base = devm_ioremap_resource(dev,
2008
-
platform_get_resource(pdev, IORESOURCE_MEM, 0));
2009
-
if (IS_ERR(base))
2010
-
return PTR_ERR(base);
2011
-
2012
2007
info->stride = 1 + (info->desc->npins - 1) / 32;
2013
2008
2014
2009
regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
2015
2010
2016
-
info->map = devm_regmap_init_mmio(dev, base, ®map_config);
2017
-
if (IS_ERR(info->map)) {
2018
-
dev_err(dev, "Failed to create regmap\n");
2019
-
return PTR_ERR(info->map);
2020
-
}
2011
+
info->map = ocelot_regmap_from_resource(pdev, 0, ®map_config);
2012
+
if (IS_ERR(info->map))
2013
+
return dev_err_probe(dev, PTR_ERR(info->map),
2014
+
"Failed to create regmap\n");
2021
2015
dev_set_drvdata(dev, info->map);
2022
2016
info->dev = dev;
2023
2017
+5
include/linux/ioport.h
+5
include/linux/ioport.h
···
172
172
#define DEFINE_RES_MEM(_start, _size) \
173
173
DEFINE_RES_MEM_NAMED((_start), (_size), NULL)
174
174
175
+
#define DEFINE_RES_REG_NAMED(_start, _size, _name) \
176
+
DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_REG)
177
+
#define DEFINE_RES_REG(_start, _size) \
178
+
DEFINE_RES_REG_NAMED((_start), (_size), NULL)
179
+
175
180
#define DEFINE_RES_IRQ_NAMED(_irq, _name) \
176
181
DEFINE_RES_NAMED((_irq), 1, (_name), IORESOURCE_IRQ)
177
182
#define DEFINE_RES_IRQ(_irq) \
+62
include/linux/mfd/ocelot.h
+62
include/linux/mfd/ocelot.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
+
/* Copyright 2022 Innovative Advantage Inc. */
3
+
4
+
#ifndef _LINUX_MFD_OCELOT_H
5
+
#define _LINUX_MFD_OCELOT_H
6
+
7
+
#include <linux/err.h>
8
+
#include <linux/errno.h>
9
+
#include <linux/ioport.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/regmap.h>
12
+
#include <linux/types.h>
13
+
14
+
struct resource;
15
+
16
+
static inline struct regmap *
17
+
ocelot_regmap_from_resource_optional(struct platform_device *pdev,
18
+
unsigned int index,
19
+
const struct regmap_config *config)
20
+
{
21
+
struct device *dev = &pdev->dev;
22
+
struct resource *res;
23
+
void __iomem *regs;
24
+
25
+
/*
26
+
* Don't use _get_and_ioremap_resource() here, since that will invoke
27
+
* prints of "invalid resource" which will simply add confusion.
28
+
*/
29
+
res = platform_get_resource(pdev, IORESOURCE_MEM, index);
30
+
if (res) {
31
+
regs = devm_ioremap_resource(dev, res);
32
+
if (IS_ERR(regs))
33
+
return ERR_CAST(regs);
34
+
return devm_regmap_init_mmio(dev, regs, config);
35
+
}
36
+
37
+
/*
38
+
* Fall back to using REG and getting the resource from the parent
39
+
* device, which is possible in an MFD configuration
40
+
*/
41
+
if (dev->parent) {
42
+
res = platform_get_resource(pdev, IORESOURCE_REG, index);
43
+
if (!res)
44
+
return NULL;
45
+
46
+
return dev_get_regmap(dev->parent, res->name);
47
+
}
48
+
49
+
return NULL;
50
+
}
51
+
52
+
static inline struct regmap *
53
+
ocelot_regmap_from_resource(struct platform_device *pdev, unsigned int index,
54
+
const struct regmap_config *config)
55
+
{
56
+
struct regmap *map;
57
+
58
+
map = ocelot_regmap_from_resource_optional(pdev, index, config);
59
+
return map ?: ERR_PTR(-ENOENT);
60
+
}
61
+
62
+
#endif