Merge branch 'pm-powercap' · tjh.dev/kernel@2bd33eb

+41 -522

drivers/powercap/intel_rapl_common.c

··· 24 24 #include <linux/suspend.h> 25 25 #include <linux/sysfs.h> 26 26 #include <linux/types.h> 27 + #include <linux/units.h> 27 28 28 29 #include <asm/cpu_device_id.h> 29 30 #include <asm/intel-family.h> 30 - #include <asm/iosf_mbi.h> 31 31 #include <asm/msr.h> 32 32 33 - /* bitmasks for RAPL MSRs, used by primitive access functions */ 34 - #define ENERGY_STATUS_MASK 0xffffffff 33 + #define ENERGY_STATUS_MASK GENMASK(31, 0) 35 34 36 - #define POWER_LIMIT1_MASK 0x7FFF 37 - #define POWER_LIMIT1_ENABLE BIT(15) 38 - #define POWER_LIMIT1_CLAMP BIT(16) 35 + #define POWER_UNIT_OFFSET 0x00 36 + #define POWER_UNIT_MASK GENMASK(3, 0) 39 37 40 - #define POWER_LIMIT2_MASK (0x7FFFULL<<32) 41 - #define POWER_LIMIT2_ENABLE BIT_ULL(47) 42 - #define POWER_LIMIT2_CLAMP BIT_ULL(48) 43 - #define POWER_HIGH_LOCK BIT_ULL(63) 44 - #define POWER_LOW_LOCK BIT(31) 38 + #define ENERGY_UNIT_OFFSET 0x08 39 + #define ENERGY_UNIT_MASK GENMASK(12, 8) 45 40 46 - #define POWER_LIMIT4_MASK 0x1FFF 47 - 48 - #define TIME_WINDOW1_MASK (0x7FULL<<17) 49 - #define TIME_WINDOW2_MASK (0x7FULL<<49) 50 - 51 - #define POWER_UNIT_OFFSET 0 52 - #define POWER_UNIT_MASK 0x0F 53 - 54 - #define ENERGY_UNIT_OFFSET 0x08 55 - #define ENERGY_UNIT_MASK 0x1F00 56 - 57 - #define TIME_UNIT_OFFSET 0x10 58 - #define TIME_UNIT_MASK 0xF0000 59 - 60 - #define POWER_INFO_MAX_MASK (0x7fffULL<<32) 61 - #define POWER_INFO_MIN_MASK (0x7fffULL<<16) 62 - #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48) 63 - #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff 64 - 65 - #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff 66 - #define PP_POLICY_MASK 0x1F 67 - 68 - /* 69 - * SPR has different layout for Psys Domain PowerLimit registers. 70 - * There are 17 bits of PL1 and PL2 instead of 15 bits. 71 - * The Enable bits and TimeWindow bits are also shifted as a result. 72 - */ 73 - #define PSYS_POWER_LIMIT1_MASK 0x1FFFF 74 - #define PSYS_POWER_LIMIT1_ENABLE BIT(17) 75 - 76 - #define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32) 77 - #define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) 78 - 79 - #define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19) 80 - #define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51) 81 - 82 - /* bitmasks for RAPL TPMI, used by primitive access functions */ 83 - #define TPMI_POWER_LIMIT_MASK 0x3FFFF 84 - #define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62) 85 - #define TPMI_TIME_WINDOW_MASK (0x7FULL<<18) 86 - #define TPMI_INFO_SPEC_MASK 0x3FFFF 87 - #define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18) 88 - #define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36) 89 - #define TPMI_INFO_MAX_TIME_WIN_MASK (0x7FULL << 54) 41 + #define TIME_UNIT_OFFSET 0x10 42 + #define TIME_UNIT_MASK GENMASK(19, 16) 90 43 91 44 /* Non HW constants */ 92 - #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ 93 - #define RAPL_PRIMITIVE_DUMMY BIT(2) 45 + #define RAPL_PRIMITIVE_DUMMY BIT(2) 94 46 95 - #define TIME_WINDOW_MAX_MSEC 40000 96 - #define TIME_WINDOW_MIN_MSEC 250 97 - #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ 98 - enum unit_type { 99 - ARBITRARY_UNIT, /* no translation */ 100 - POWER_UNIT, 101 - ENERGY_UNIT, 102 - TIME_UNIT, 103 - }; 47 + #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ 104 48 105 49 /* per domain data, some are optional */ 106 - #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) 50 + #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) 107 51 108 - #define DOMAIN_STATE_INACTIVE BIT(0) 109 - #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) 52 + #define PACKAGE_PLN_INT_SAVED BIT(0) 53 + 54 + #define RAPL_EVENT_MASK GENMASK(7, 0) 110 55 111 56 static const char *pl_names[NR_POWER_LIMITS] = { 112 57 [POWER_LIMIT1] = "long_term", ··· 149 204 #define power_zone_to_rapl_domain(_zone) \ 150 205 container_of(_zone, struct rapl_domain, power_zone) 151 206 152 - struct rapl_defaults { 153 - u8 floor_freq_reg_addr; 154 - int (*check_unit)(struct rapl_domain *rd); 155 - void (*set_floor_freq)(struct rapl_domain *rd, bool mode); 156 - u64 (*compute_time_window)(struct rapl_domain *rd, u64 val, 157 - bool to_raw); 158 - unsigned int dram_domain_energy_unit; 159 - unsigned int psys_domain_energy_unit; 160 - bool spr_psys_bits; 161 - }; 162 - static struct rapl_defaults *defaults_msr; 163 - static const struct rapl_defaults defaults_tpmi; 164 - 165 - static struct rapl_defaults *get_defaults(struct rapl_package *rp) 207 + static const struct rapl_defaults *get_defaults(struct rapl_package *rp) 166 208 { 167 209 return rp->priv->defaults; 168 210 } 169 - 170 - /* Sideband MBI registers */ 171 - #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2) 172 - #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf) 173 - 174 - #define PACKAGE_PLN_INT_SAVED BIT(0) 175 - #define MAX_PRIM_NAME (32) 176 - 177 - /* per domain data. used to describe individual knobs such that access function 178 - * can be consolidated into one instead of many inline functions. 179 - */ 180 - struct rapl_primitive_info { 181 - const char *name; 182 - u64 mask; 183 - int shift; 184 - enum rapl_domain_reg_id id; 185 - enum unit_type unit; 186 - u32 flag; 187 - }; 188 - 189 - #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ 190 - .name = #p, \ 191 - .mask = m, \ 192 - .shift = s, \ 193 - .id = i, \ 194 - .unit = u, \ 195 - .flag = f \ 196 - } 197 211 198 212 static void rapl_init_domains(struct rapl_package *rp); 199 213 static int rapl_read_data_raw(struct rapl_domain *rd, ··· 245 341 static int set_domain_enable(struct powercap_zone *power_zone, bool mode) 246 342 { 247 343 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); 248 - struct rapl_defaults *defaults = get_defaults(rd->rp); 344 + const struct rapl_defaults *defaults = get_defaults(rd->rp); 249 345 u64 val; 250 346 int ret; 251 347 ··· 534 630 u64 value, int to_raw) 535 631 { 536 632 u64 units = 1; 537 - struct rapl_defaults *defaults = get_defaults(rd->rp); 633 + const struct rapl_defaults *defaults = get_defaults(rd->rp); 538 634 u64 scale = 1; 539 635 540 636 switch (type) { ··· 560 656 return div64_u64(value, scale); 561 657 } 562 658 563 - /* RAPL primitives for MSR and MMIO I/F */ 564 - static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = { 565 - /* name, mask, shift, msr index, unit divisor */ 566 - [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0, 567 - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 568 - [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32, 569 - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 570 - [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0, 571 - RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 572 - [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, 573 - RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 574 - [FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31, 575 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 576 - [FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63, 577 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 578 - [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, 579 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 580 - [PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, 581 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 582 - [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, 583 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 584 - [PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, 585 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 586 - [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17, 587 - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 588 - [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49, 589 - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 590 - [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK, 591 - 0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 592 - [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, 593 - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 594 - [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, 595 - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 596 - [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48, 597 - RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 598 - [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, 599 - RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 600 - [PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0, 601 - RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), 602 - [PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0, 603 - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 604 - [PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK, 32, 605 - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 606 - [PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE, 17, 607 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 608 - [PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE, 49, 609 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 610 - [PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK, 19, 611 - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 612 - [PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK, 51, 613 - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 614 - /* non-hardware */ 615 - [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT, 616 - RAPL_PRIMITIVE_DERIVED), 617 - }; 618 - 619 - /* RAPL primitives for TPMI I/F */ 620 - static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] = { 621 - /* name, mask, shift, msr index, unit divisor */ 622 - [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0, 623 - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 624 - [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0, 625 - RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0), 626 - [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0, 627 - RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 628 - [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, 629 - RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 630 - [PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63, 631 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 632 - [PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63, 633 - RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), 634 - [PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63, 635 - RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), 636 - [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 637 - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 638 - [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 639 - RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), 640 - [PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 641 - RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), 642 - [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18, 643 - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 644 - [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18, 645 - RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0), 646 - [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0, 647 - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 648 - [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36, 649 - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 650 - [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18, 651 - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 652 - [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK, 54, 653 - RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 654 - [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, 655 - RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 656 - /* non-hardware */ 657 - [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, 658 - POWER_UNIT, RAPL_PRIMITIVE_DERIVED), 659 - }; 660 - 661 659 static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int prim) 662 660 { 663 661 struct rapl_primitive_info *rpi = rp->priv->rpi; ··· 572 766 573 767 static int rapl_config(struct rapl_package *rp) 574 768 { 575 - switch (rp->priv->type) { 576 - /* MMIO I/F shares the same register layout as MSR registers */ 577 - case RAPL_IF_MMIO: 578 - case RAPL_IF_MSR: 579 - rp->priv->defaults = (void *)defaults_msr; 580 - rp->priv->rpi = (void *)rpi_msr; 581 - break; 582 - case RAPL_IF_TPMI: 583 - rp->priv->defaults = (void *)&defaults_tpmi; 584 - rp->priv->rpi = (void *)rpi_tpmi; 585 - break; 586 - default: 587 - return -EINVAL; 588 - } 589 - 590 769 /* defaults_msr can be NULL on unsupported platforms */ 591 770 if (!rp->priv->defaults || !rp->priv->rpi) 592 771 return -ENODEV; ··· 582 791 static enum rapl_primitives 583 792 prim_fixups(struct rapl_domain *rd, enum rapl_primitives prim) 584 793 { 585 - struct rapl_defaults *defaults = get_defaults(rd->rp); 794 + const struct rapl_defaults *defaults = get_defaults(rd->rp); 586 795 587 796 if (!defaults->spr_psys_bits) 588 797 return prim; ··· 636 845 ra.reg = rd->regs[rpi->id]; 637 846 if (!ra.reg.val) 638 847 return -EINVAL; 639 - 640 - /* non-hardware data are collected by the polling thread */ 641 - if (rpi->flag & RAPL_PRIMITIVE_DERIVED) { 642 - *data = rd->rdd.primitives[prim]; 643 - return 0; 644 - } 645 848 646 849 ra.mask = rpi->mask; 647 850 ··· 721 936 * power unit : microWatts : Represented in milliWatts by default 722 937 * time unit : microseconds: Represented in seconds by default 723 938 */ 724 - static int rapl_check_unit_core(struct rapl_domain *rd) 939 + int rapl_default_check_unit(struct rapl_domain *rd) 725 940 { 726 941 struct reg_action ra; 727 942 u32 value; ··· 735 950 } 736 951 737 952 value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; 738 - rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); 953 + rd->energy_unit = (ENERGY_UNIT_SCALE * MICROJOULE_PER_JOULE) >> value; 739 954 740 955 value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; 741 - rd->power_unit = 1000000 / (1 << value); 956 + rd->power_unit = MICROWATT_PER_WATT >> value; 742 957 743 958 value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; 744 - rd->time_unit = 1000000 / (1 << value); 959 + rd->time_unit = USEC_PER_SEC >> value; 745 960 746 961 pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n", 747 962 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 748 963 749 964 return 0; 750 965 } 751 - 752 - static int rapl_check_unit_atom(struct rapl_domain *rd) 753 - { 754 - struct reg_action ra; 755 - u32 value; 756 - 757 - ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 758 - ra.mask = ~0; 759 - if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, false)) { 760 - pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 761 - ra.reg.val, rd->rp->name, rd->name); 762 - return -ENODEV; 763 - } 764 - 765 - value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; 766 - rd->energy_unit = ENERGY_UNIT_SCALE * 1 << value; 767 - 768 - value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; 769 - rd->power_unit = (1 << value) * 1000; 770 - 771 - value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; 772 - rd->time_unit = 1000000 / (1 << value); 773 - 774 - pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n", 775 - rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 776 - 777 - return 0; 778 - } 966 + EXPORT_SYMBOL_NS_GPL(rapl_default_check_unit, "INTEL_RAPL"); 779 967 780 968 static void power_limit_irq_save_cpu(void *info) 781 969 { ··· 814 1056 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); 815 1057 } 816 1058 817 - static void set_floor_freq_default(struct rapl_domain *rd, bool mode) 1059 + void rapl_default_set_floor_freq(struct rapl_domain *rd, bool mode) 818 1060 { 819 1061 int i; 820 1062 ··· 828 1070 rapl_write_pl_data(rd, i, PL_CLAMP, mode); 829 1071 } 830 1072 } 1073 + EXPORT_SYMBOL_NS_GPL(rapl_default_set_floor_freq, "INTEL_RAPL"); 831 1074 832 - static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) 833 - { 834 - static u32 power_ctrl_orig_val; 835 - struct rapl_defaults *defaults = get_defaults(rd->rp); 836 - u32 mdata; 837 - 838 - if (!defaults->floor_freq_reg_addr) { 839 - pr_err("Invalid floor frequency config register\n"); 840 - return; 841 - } 842 - 843 - if (!power_ctrl_orig_val) 844 - iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, 845 - defaults->floor_freq_reg_addr, 846 - &power_ctrl_orig_val); 847 - mdata = power_ctrl_orig_val; 848 - if (enable) { 849 - mdata &= ~(0x7f << 8); 850 - mdata |= 1 << 8; 851 - } 852 - iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, 853 - defaults->floor_freq_reg_addr, mdata); 854 - } 855 - 856 - static u64 rapl_compute_time_window_core(struct rapl_domain *rd, u64 value, 857 - bool to_raw) 1075 + u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bool to_raw) 858 1076 { 859 1077 u64 f, y; /* fraction and exp. used for time unit */ 860 1078 ··· 841 1107 if (!to_raw) { 842 1108 f = (value & 0x60) >> 5; 843 1109 y = value & 0x1f; 844 - value = (1 << y) * (4 + f) * rd->time_unit / 4; 1110 + value = (1ULL << y) * (4 + f) * rd->time_unit / 4; 845 1111 } else { 846 1112 if (value < rd->time_unit) 847 1113 return 0; ··· 856 1122 if (y > 0x1f) 857 1123 return 0x7f; 858 1124 859 - f = div64_u64(4 * (value - (1ULL << y)), 1ULL << y); 1125 + f = div64_u64(4 * (value - BIT_ULL(y)), BIT_ULL(y)); 860 1126 value = (y & 0x1f) | ((f & 0x3) << 5); 861 1127 } 862 1128 return value; 863 1129 } 864 - 865 - static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value, 866 - bool to_raw) 867 - { 868 - /* 869 - * Atom time unit encoding is straight forward val * time_unit, 870 - * where time_unit is default to 1 sec. Never 0. 871 - */ 872 - if (!to_raw) 873 - return (value) ? value * rd->time_unit : rd->time_unit; 874 - 875 - value = div64_u64(value, rd->time_unit); 876 - 877 - return value; 878 - } 879 - 880 - /* TPMI Unit register has different layout */ 881 - #define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET 882 - #define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK 883 - #define TPMI_ENERGY_UNIT_OFFSET 0x06 884 - #define TPMI_ENERGY_UNIT_MASK 0x7C0 885 - #define TPMI_TIME_UNIT_OFFSET 0x0C 886 - #define TPMI_TIME_UNIT_MASK 0xF000 887 - 888 - static int rapl_check_unit_tpmi(struct rapl_domain *rd) 889 - { 890 - struct reg_action ra; 891 - u32 value; 892 - 893 - ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 894 - ra.mask = ~0; 895 - if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, false)) { 896 - pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 897 - ra.reg.val, rd->rp->name, rd->name); 898 - return -ENODEV; 899 - } 900 - 901 - value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET; 902 - rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); 903 - 904 - value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET; 905 - rd->power_unit = 1000000 / (1 << value); 906 - 907 - value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET; 908 - rd->time_unit = 1000000 / (1 << value); 909 - 910 - pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n", 911 - rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 912 - 913 - return 0; 914 - } 915 - 916 - static const struct rapl_defaults defaults_tpmi = { 917 - .check_unit = rapl_check_unit_tpmi, 918 - /* Reuse existing logic, ignore the PL_CLAMP failures and enable all Power Limits */ 919 - .set_floor_freq = set_floor_freq_default, 920 - .compute_time_window = rapl_compute_time_window_core, 921 - }; 922 - 923 - static const struct rapl_defaults rapl_defaults_core = { 924 - .floor_freq_reg_addr = 0, 925 - .check_unit = rapl_check_unit_core, 926 - .set_floor_freq = set_floor_freq_default, 927 - .compute_time_window = rapl_compute_time_window_core, 928 - }; 929 - 930 - static const struct rapl_defaults rapl_defaults_hsw_server = { 931 - .check_unit = rapl_check_unit_core, 932 - .set_floor_freq = set_floor_freq_default, 933 - .compute_time_window = rapl_compute_time_window_core, 934 - .dram_domain_energy_unit = 15300, 935 - }; 936 - 937 - static const struct rapl_defaults rapl_defaults_spr_server = { 938 - .check_unit = rapl_check_unit_core, 939 - .set_floor_freq = set_floor_freq_default, 940 - .compute_time_window = rapl_compute_time_window_core, 941 - .psys_domain_energy_unit = 1000000000, 942 - .spr_psys_bits = true, 943 - }; 944 - 945 - static const struct rapl_defaults rapl_defaults_byt = { 946 - .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, 947 - .check_unit = rapl_check_unit_atom, 948 - .set_floor_freq = set_floor_freq_atom, 949 - .compute_time_window = rapl_compute_time_window_atom, 950 - }; 951 - 952 - static const struct rapl_defaults rapl_defaults_tng = { 953 - .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, 954 - .check_unit = rapl_check_unit_atom, 955 - .set_floor_freq = set_floor_freq_atom, 956 - .compute_time_window = rapl_compute_time_window_atom, 957 - }; 958 - 959 - static const struct rapl_defaults rapl_defaults_ann = { 960 - .floor_freq_reg_addr = 0, 961 - .check_unit = rapl_check_unit_atom, 962 - .set_floor_freq = NULL, 963 - .compute_time_window = rapl_compute_time_window_atom, 964 - }; 965 - 966 - static const struct rapl_defaults rapl_defaults_cht = { 967 - .floor_freq_reg_addr = 0, 968 - .check_unit = rapl_check_unit_atom, 969 - .set_floor_freq = NULL, 970 - .compute_time_window = rapl_compute_time_window_atom, 971 - }; 972 - 973 - static const struct rapl_defaults rapl_defaults_amd = { 974 - .check_unit = rapl_check_unit_core, 975 - }; 976 - 977 - static const struct x86_cpu_id rapl_ids[] __initconst = { 978 - X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), 979 - X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), 980 - 981 - X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core), 982 - X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core), 983 - 984 - X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core), 985 - X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core), 986 - X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core), 987 - X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server), 988 - 989 - X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core), 990 - X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core), 991 - X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core), 992 - X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server), 993 - 994 - X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core), 995 - X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core), 996 - X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server), 997 - X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), 998 - X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), 999 - X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), 1000 - X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core), 1001 - X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), 1002 - X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), 1003 - X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), 1004 - X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), 1005 - X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), 1006 - X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), 1007 - X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core), 1008 - X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), 1009 - X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), 1010 - X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core), 1011 - X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core), 1012 - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core), 1013 - X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core), 1014 - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core), 1015 - X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), 1016 - X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core), 1017 - X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core), 1018 - X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core), 1019 - X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), 1020 - X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), 1021 - X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), 1022 - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core), 1023 - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core), 1024 - X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core), 1025 - X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core), 1026 - X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core), 1027 - X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), 1028 - X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core), 1029 - X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), 1030 - 1031 - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), 1032 - X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht), 1033 - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng), 1034 - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,&rapl_defaults_ann), 1035 - X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core), 1036 - X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core), 1037 - X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core), 1038 - X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core), 1039 - X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core), 1040 - X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core), 1041 - 1042 - X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server), 1043 - X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server), 1044 - 1045 - X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd), 1046 - X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd), 1047 - X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd), 1048 - X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd), 1049 - {} 1050 - }; 1051 - MODULE_DEVICE_TABLE(x86cpu, rapl_ids); 1130 + EXPORT_SYMBOL_NS_GPL(rapl_default_compute_time_window, "INTEL_RAPL"); 1052 1131 1053 1132 /* Read once for all raw primitive data for domains */ 1054 1133 static void rapl_update_domain_data(struct rapl_package *rp) ··· 990 1443 */ 991 1444 static int rapl_get_domain_unit(struct rapl_domain *rd) 992 1445 { 993 - struct rapl_defaults *defaults = get_defaults(rd->rp); 1446 + const struct rapl_defaults *defaults = get_defaults(rd->rp); 994 1447 int ret; 995 1448 996 1449 if (!rd->regs[RAPL_DOMAIN_REG_UNIT].val) { ··· 1324 1777 PERF_RAPL_PSYS, /* psys */ 1325 1778 PERF_RAPL_MAX 1326 1779 }; 1327 - #define RAPL_EVENT_MASK GENMASK(7, 0) 1328 1780 1329 1781 static const int event_to_domain[PERF_RAPL_MAX] = { 1330 1782 [PERF_RAPL_PP0] = RAPL_DOMAIN_PP0, ··· 1629 2083 1630 2084 return rapl_pmu_update(rp); 1631 2085 } 1632 - EXPORT_SYMBOL_GPL(rapl_package_add_pmu_locked); 2086 + EXPORT_SYMBOL_NS_GPL(rapl_package_add_pmu_locked, "INTEL_RAPL"); 1633 2087 1634 2088 int rapl_package_add_pmu(struct rapl_package *rp) 1635 2089 { ··· 1637 2091 1638 2092 return rapl_package_add_pmu_locked(rp); 1639 2093 } 1640 - EXPORT_SYMBOL_GPL(rapl_package_add_pmu); 2094 + EXPORT_SYMBOL_NS_GPL(rapl_package_add_pmu, "INTEL_RAPL"); 1641 2095 1642 2096 void rapl_package_remove_pmu_locked(struct rapl_package *rp) 1643 2097 { ··· 1655 2109 perf_pmu_unregister(&rapl_pmu.pmu); 1656 2110 memset(&rapl_pmu, 0, sizeof(struct rapl_pmu)); 1657 2111 } 1658 - EXPORT_SYMBOL_GPL(rapl_package_remove_pmu_locked); 2112 + EXPORT_SYMBOL_NS_GPL(rapl_package_remove_pmu_locked, "INTEL_RAPL"); 1659 2113 1660 2114 void rapl_package_remove_pmu(struct rapl_package *rp) 1661 2115 { ··· 1663 2117 1664 2118 rapl_package_remove_pmu_locked(rp); 1665 2119 } 1666 - EXPORT_SYMBOL_GPL(rapl_package_remove_pmu); 2120 + EXPORT_SYMBOL_NS_GPL(rapl_package_remove_pmu, "INTEL_RAPL"); 1667 2121 #endif 1668 2122 1669 2123 /* called from CPU hotplug notifier, hotplug lock held */ ··· 1696 2150 list_del(&rp->plist); 1697 2151 kfree(rp); 1698 2152 } 1699 - EXPORT_SYMBOL_GPL(rapl_remove_package_cpuslocked); 2153 + EXPORT_SYMBOL_NS_GPL(rapl_remove_package_cpuslocked, "INTEL_RAPL"); 1700 2154 1701 2155 void rapl_remove_package(struct rapl_package *rp) 1702 2156 { 1703 2157 guard(cpus_read_lock)(); 1704 2158 rapl_remove_package_cpuslocked(rp); 1705 2159 } 1706 - EXPORT_SYMBOL_GPL(rapl_remove_package); 2160 + EXPORT_SYMBOL_NS_GPL(rapl_remove_package, "INTEL_RAPL"); 1707 2161 1708 2162 /* 1709 2163 * RAPL Package energy counter scope: ··· 1746 2200 1747 2201 return NULL; 1748 2202 } 1749 - EXPORT_SYMBOL_GPL(rapl_find_package_domain_cpuslocked); 2203 + EXPORT_SYMBOL_NS_GPL(rapl_find_package_domain_cpuslocked, "INTEL_RAPL"); 1750 2204 1751 2205 struct rapl_package *rapl_find_package_domain(int id, struct rapl_if_priv *priv, bool id_is_cpu) 1752 2206 { 1753 2207 guard(cpus_read_lock)(); 1754 2208 return rapl_find_package_domain_cpuslocked(id, priv, id_is_cpu); 1755 2209 } 1756 - EXPORT_SYMBOL_GPL(rapl_find_package_domain); 2210 + EXPORT_SYMBOL_NS_GPL(rapl_find_package_domain, "INTEL_RAPL"); 1757 2211 1758 2212 /* called from CPU hotplug notifier, hotplug lock held */ 1759 2213 struct rapl_package *rapl_add_package_cpuslocked(int id, struct rapl_if_priv *priv, bool id_is_cpu) ··· 1807 2261 kfree(rp); 1808 2262 return ERR_PTR(ret); 1809 2263 } 1810 - EXPORT_SYMBOL_GPL(rapl_add_package_cpuslocked); 2264 + EXPORT_SYMBOL_NS_GPL(rapl_add_package_cpuslocked, "INTEL_RAPL"); 1811 2265 1812 2266 struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id_is_cpu) 1813 2267 { 1814 2268 guard(cpus_read_lock)(); 1815 2269 return rapl_add_package_cpuslocked(id, priv, id_is_cpu); 1816 2270 } 1817 - EXPORT_SYMBOL_GPL(rapl_add_package); 2271 + EXPORT_SYMBOL_NS_GPL(rapl_add_package, "INTEL_RAPL"); 1818 2272 1819 2273 static void power_limit_state_save(void) 1820 2274 { ··· 1874 2328 .notifier_call = rapl_pm_callback, 1875 2329 }; 1876 2330 1877 - static struct platform_device *rapl_msr_platdev; 1878 - 1879 2331 static int __init rapl_init(void) 1880 2332 { 1881 - const struct x86_cpu_id *id; 1882 - int ret; 1883 - 1884 - id = x86_match_cpu(rapl_ids); 1885 - if (id) { 1886 - defaults_msr = (struct rapl_defaults *)id->driver_data; 1887 - 1888 - rapl_msr_platdev = platform_device_alloc("intel_rapl_msr", 0); 1889 - if (!rapl_msr_platdev) 1890 - return -ENOMEM; 1891 - 1892 - ret = platform_device_add(rapl_msr_platdev); 1893 - if (ret) { 1894 - platform_device_put(rapl_msr_platdev); 1895 - return ret; 1896 - } 1897 - } 1898 - 1899 - ret = register_pm_notifier(&rapl_pm_notifier); 1900 - if (ret && rapl_msr_platdev) { 1901 - platform_device_del(rapl_msr_platdev); 1902 - platform_device_put(rapl_msr_platdev); 1903 - } 1904 - 1905 - return ret; 2333 + return register_pm_notifier(&rapl_pm_notifier); 1906 2334 } 1907 2335 1908 2336 static void __exit rapl_exit(void) 1909 2337 { 1910 - platform_device_unregister(rapl_msr_platdev); 1911 2338 unregister_pm_notifier(&rapl_pm_notifier); 1912 2339 } 1913 2340

+365 -28

drivers/powercap/intel_rapl_msr.c

··· 21 21 #include <linux/intel_rapl.h> 22 22 #include <linux/processor.h> 23 23 #include <linux/platform_device.h> 24 + #include <linux/units.h> 25 + #include <linux/bits.h> 24 26 25 27 #include <asm/cpu_device_id.h> 26 28 #include <asm/intel-family.h> 29 + #include <asm/iosf_mbi.h> 27 30 #include <asm/msr.h> 28 31 29 32 /* Local defines */ 30 33 #define MSR_PLATFORM_POWER_LIMIT 0x0000065C 31 34 #define MSR_VR_CURRENT_CONFIG 0x00000601 35 + 36 + #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ 37 + 38 + #define POWER_UNIT_OFFSET 0x00 39 + #define POWER_UNIT_MASK GENMASK(3, 0) 40 + 41 + #define ENERGY_UNIT_OFFSET 0x08 42 + #define ENERGY_UNIT_MASK GENMASK(12, 8) 43 + 44 + #define TIME_UNIT_OFFSET 0x10 45 + #define TIME_UNIT_MASK GENMASK(19, 16) 46 + 47 + /* bitmasks for RAPL MSRs, used by primitive access functions */ 48 + #define ENERGY_STATUS_MASK GENMASK(31, 0) 49 + 50 + #define POWER_LIMIT1_MASK GENMASK(14, 0) 51 + #define POWER_LIMIT1_ENABLE BIT(15) 52 + #define POWER_LIMIT1_CLAMP BIT(16) 53 + 54 + #define POWER_LIMIT2_MASK GENMASK_ULL(46, 32) 55 + #define POWER_LIMIT2_ENABLE BIT_ULL(47) 56 + #define POWER_LIMIT2_CLAMP BIT_ULL(48) 57 + #define POWER_HIGH_LOCK BIT_ULL(63) 58 + #define POWER_LOW_LOCK BIT(31) 59 + 60 + #define POWER_LIMIT4_MASK GENMASK(12, 0) 61 + 62 + #define TIME_WINDOW1_MASK GENMASK_ULL(23, 17) 63 + #define TIME_WINDOW2_MASK GENMASK_ULL(55, 49) 64 + 65 + #define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) 66 + #define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) 67 + #define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) 68 + #define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) 69 + 70 + #define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) 71 + #define PP_POLICY_MASK GENMASK(4, 0) 72 + 73 + /* 74 + * SPR has different layout for Psys Domain PowerLimit registers. 75 + * There are 17 bits of PL1 and PL2 instead of 15 bits. 76 + * The Enable bits and TimeWindow bits are also shifted as a result. 77 + */ 78 + #define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0) 79 + #define PSYS_POWER_LIMIT1_ENABLE BIT(17) 80 + 81 + #define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32) 82 + #define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) 83 + 84 + #define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19) 85 + #define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51) 86 + 87 + /* Sideband MBI registers */ 88 + #define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02 89 + #define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF 32 90 33 91 /* private data for RAPL MSR Interface */ 34 92 static struct rapl_if_priv *rapl_msr_priv; ··· 216 158 return ra->err; 217 159 } 218 160 219 - /* List of verified CPUs. */ 220 - static const struct x86_cpu_id pl4_support_ids[] = { 221 - X86_MATCH_VFM(INTEL_ICELAKE_L, NULL), 222 - X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL), 223 - X86_MATCH_VFM(INTEL_ALDERLAKE, NULL), 224 - X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL), 225 - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, NULL), 226 - X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL), 227 - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL), 228 - X86_MATCH_VFM(INTEL_METEORLAKE, NULL), 229 - X86_MATCH_VFM(INTEL_METEORLAKE_L, NULL), 230 - X86_MATCH_VFM(INTEL_ARROWLAKE_U, NULL), 231 - X86_MATCH_VFM(INTEL_ARROWLAKE_H, NULL), 232 - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL), 233 - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL), 234 - X86_MATCH_VFM(INTEL_NOVALAKE, NULL), 235 - X86_MATCH_VFM(INTEL_NOVALAKE_L, NULL), 236 - {} 161 + static int rapl_check_unit_atom(struct rapl_domain *rd) 162 + { 163 + struct reg_action ra; 164 + u32 value; 165 + 166 + ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 167 + ra.mask = ~0; 168 + if (rapl_msr_read_raw(rd->rp->lead_cpu, &ra, false)) { 169 + pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 170 + ra.reg.val, rd->rp->name, rd->name); 171 + return -ENODEV; 172 + } 173 + 174 + value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; 175 + rd->energy_unit = ENERGY_UNIT_SCALE * (1ULL << value); 176 + 177 + value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; 178 + rd->power_unit = (1ULL << value) * MILLIWATT_PER_WATT; 179 + 180 + value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; 181 + rd->time_unit = USEC_PER_SEC >> value; 182 + 183 + pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n", 184 + rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 185 + 186 + return 0; 187 + } 188 + 189 + static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) 190 + { 191 + static u32 power_ctrl_orig_val; 192 + const struct rapl_defaults *defaults = rd->rp->priv->defaults; 193 + u32 mdata; 194 + 195 + if (!defaults->floor_freq_reg_addr) { 196 + pr_err("Invalid floor frequency config register\n"); 197 + return; 198 + } 199 + 200 + if (!power_ctrl_orig_val) 201 + iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, 202 + defaults->floor_freq_reg_addr, 203 + &power_ctrl_orig_val); 204 + mdata = power_ctrl_orig_val; 205 + if (enable) { 206 + mdata &= ~GENMASK(14, 8); 207 + mdata |= BIT(8); 208 + } 209 + iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, 210 + defaults->floor_freq_reg_addr, mdata); 211 + } 212 + 213 + static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value, 214 + bool to_raw) 215 + { 216 + if (to_raw) 217 + return div64_u64(value, rd->time_unit); 218 + 219 + /* 220 + * Atom time unit encoding is straight forward val * time_unit, 221 + * where time_unit is default to 1 sec. Never 0. 222 + */ 223 + return value ? value * rd->time_unit : rd->time_unit; 224 + } 225 + 226 + /* RAPL primitives for MSR I/F */ 227 + static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = { 228 + /* name, mask, shift, msr index, unit divisor */ 229 + [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0, 230 + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 231 + [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32, 232 + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 233 + [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0, 234 + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 235 + [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, 236 + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 237 + [FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31, 238 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 239 + [FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63, 240 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 241 + [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, 242 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 243 + [PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, 244 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 245 + [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, 246 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 247 + [PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, 248 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 249 + [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17, 250 + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 251 + [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49, 252 + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 253 + [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, 254 + POWER_INFO_THERMAL_SPEC_MASK, 0, 255 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 256 + [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, 257 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 258 + [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, 259 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 260 + [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, 261 + POWER_INFO_MAX_TIME_WIN_MASK, 48, 262 + RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 263 + [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, 264 + PERF_STATUS_THROTTLE_TIME_MASK, 0, 265 + RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 266 + [PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0, 267 + RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), 268 + [PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0, 269 + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 270 + [PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK, 271 + 32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 272 + [PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE, 273 + 17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 274 + 0), 275 + [PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE, 276 + 49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 277 + 0), 278 + [PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK, 279 + 19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 280 + [PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK, 281 + 51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 237 282 }; 238 283 239 - /* List of MSR-based RAPL PMU support CPUs */ 240 - static const struct x86_cpu_id pmu_support_ids[] = { 241 - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL), 242 - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL), 284 + static const struct rapl_defaults rapl_defaults_core = { 285 + .floor_freq_reg_addr = 0, 286 + .check_unit = rapl_default_check_unit, 287 + .set_floor_freq = rapl_default_set_floor_freq, 288 + .compute_time_window = rapl_default_compute_time_window, 289 + }; 290 + 291 + static const struct rapl_defaults rapl_defaults_hsw_server = { 292 + .check_unit = rapl_default_check_unit, 293 + .set_floor_freq = rapl_default_set_floor_freq, 294 + .compute_time_window = rapl_default_compute_time_window, 295 + .dram_domain_energy_unit = 15300, 296 + }; 297 + 298 + static const struct rapl_defaults rapl_defaults_spr_server = { 299 + .check_unit = rapl_default_check_unit, 300 + .set_floor_freq = rapl_default_set_floor_freq, 301 + .compute_time_window = rapl_default_compute_time_window, 302 + .psys_domain_energy_unit = NANOJOULE_PER_JOULE, 303 + .spr_psys_bits = true, 304 + }; 305 + 306 + static const struct rapl_defaults rapl_defaults_byt = { 307 + .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, 308 + .check_unit = rapl_check_unit_atom, 309 + .set_floor_freq = set_floor_freq_atom, 310 + .compute_time_window = rapl_compute_time_window_atom, 311 + }; 312 + 313 + static const struct rapl_defaults rapl_defaults_tng = { 314 + .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, 315 + .check_unit = rapl_check_unit_atom, 316 + .set_floor_freq = set_floor_freq_atom, 317 + .compute_time_window = rapl_compute_time_window_atom, 318 + }; 319 + 320 + static const struct rapl_defaults rapl_defaults_ann = { 321 + .floor_freq_reg_addr = 0, 322 + .check_unit = rapl_check_unit_atom, 323 + .set_floor_freq = NULL, 324 + .compute_time_window = rapl_compute_time_window_atom, 325 + }; 326 + 327 + static const struct rapl_defaults rapl_defaults_cht = { 328 + .floor_freq_reg_addr = 0, 329 + .check_unit = rapl_check_unit_atom, 330 + .set_floor_freq = NULL, 331 + .compute_time_window = rapl_compute_time_window_atom, 332 + }; 333 + 334 + static const struct rapl_defaults rapl_defaults_amd = { 335 + .check_unit = rapl_default_check_unit, 336 + }; 337 + 338 + static const struct rapl_defaults rapl_defaults_core_pl4 = { 339 + .floor_freq_reg_addr = 0, 340 + .check_unit = rapl_default_check_unit, 341 + .set_floor_freq = rapl_default_set_floor_freq, 342 + .compute_time_window = rapl_default_compute_time_window, 343 + .msr_pl4_support = 1, 344 + }; 345 + 346 + static const struct rapl_defaults rapl_defaults_core_pl4_pmu = { 347 + .floor_freq_reg_addr = 0, 348 + .check_unit = rapl_default_check_unit, 349 + .set_floor_freq = rapl_default_set_floor_freq, 350 + .compute_time_window = rapl_default_compute_time_window, 351 + .msr_pl4_support = 1, 352 + .msr_pmu_support = 1, 353 + }; 354 + 355 + static const struct x86_cpu_id rapl_ids[] = { 356 + X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), 357 + X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), 358 + 359 + X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core), 360 + X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core), 361 + 362 + X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core), 363 + X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core), 364 + X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core), 365 + X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server), 366 + 367 + X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core), 368 + X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core), 369 + X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core), 370 + X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server), 371 + 372 + X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core), 373 + X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core), 374 + X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server), 375 + X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), 376 + X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), 377 + X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), 378 + X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core_pl4), 379 + X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), 380 + X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), 381 + X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), 382 + X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), 383 + X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), 384 + X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), 385 + X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core_pl4), 386 + X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), 387 + X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), 388 + X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core_pl4), 389 + X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core_pl4), 390 + X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core_pl4), 391 + X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core_pl4), 392 + X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core_pl4), 393 + X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), 394 + X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core), 395 + X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core_pl4), 396 + X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core_pl4), 397 + X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), 398 + X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), 399 + X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), 400 + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core_pl4_pmu), 401 + X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core_pl4_pmu), 402 + X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core_pl4), 403 + X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core_pl4), 404 + X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core_pl4), 405 + X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), 406 + X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core_pl4), 407 + X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), 408 + 409 + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), 410 + X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht), 411 + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng), 412 + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2, &rapl_defaults_ann), 413 + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core), 414 + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core), 415 + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core), 416 + X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core), 417 + X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core), 418 + X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core), 419 + 420 + X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server), 421 + X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server), 422 + 423 + X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd), 424 + X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd), 425 + X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd), 426 + X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd), 243 427 {} 244 428 }; 429 + MODULE_DEVICE_TABLE(x86cpu, rapl_ids); 245 430 246 431 static int rapl_msr_probe(struct platform_device *pdev) 247 432 { 248 - const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids); 249 433 int ret; 250 434 251 435 switch (boot_cpu_data.x86_vendor) { ··· 504 204 } 505 205 rapl_msr_priv->read_raw = rapl_msr_read_raw; 506 206 rapl_msr_priv->write_raw = rapl_msr_write_raw; 207 + rapl_msr_priv->defaults = (const struct rapl_defaults *)pdev->dev.platform_data; 208 + rapl_msr_priv->rpi = rpi_msr; 507 209 508 - if (id) { 210 + if (rapl_msr_priv->defaults->msr_pl4_support) { 509 211 rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |= BIT(POWER_LIMIT4); 510 212 rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4].msr = 511 213 MSR_VR_CURRENT_CONFIG; 512 - pr_info("PL4 support detected.\n"); 214 + pr_info("PL4 support detected (updated).\n"); 513 215 } 514 216 515 - if (x86_match_cpu(pmu_support_ids)) { 217 + if (rapl_msr_priv->defaults->msr_pmu_support) { 516 218 rapl_msr_pmu = true; 517 - pr_info("MSR-based RAPL PMU support enabled\n"); 219 + pr_info("MSR-based RAPL PMU support enabled (updated)\n"); 518 220 } 519 221 520 222 rapl_msr_priv->control_type = powercap_register_control_type(NULL, "intel-rapl", NULL); ··· 560 258 }, 561 259 }; 562 260 563 - module_platform_driver(intel_rapl_msr_driver); 261 + static struct platform_device *rapl_msr_platdev; 262 + 263 + static int intel_rapl_msr_init(void) 264 + { 265 + const struct rapl_defaults *def; 266 + const struct x86_cpu_id *id; 267 + int ret; 268 + 269 + ret = platform_driver_register(&intel_rapl_msr_driver); 270 + if (ret) 271 + return ret; 272 + 273 + /* Create the MSR RAPL platform device for supported platforms */ 274 + id = x86_match_cpu(rapl_ids); 275 + if (!id) 276 + return 0; 277 + 278 + def = (const struct rapl_defaults *)id->driver_data; 279 + 280 + rapl_msr_platdev = platform_device_register_data(NULL, "intel_rapl_msr", 0, def, 281 + sizeof(*def)); 282 + if (IS_ERR(rapl_msr_platdev)) 283 + pr_debug("intel_rapl_msr device register failed, ret:%ld\n", 284 + PTR_ERR(rapl_msr_platdev)); 285 + 286 + return 0; 287 + } 288 + module_init(intel_rapl_msr_init); 289 + 290 + static void intel_rapl_msr_exit(void) 291 + { 292 + platform_device_unregister(rapl_msr_platdev); 293 + platform_driver_unregister(&intel_rapl_msr_driver); 294 + } 295 + module_exit(intel_rapl_msr_exit); 564 296 565 297 MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit) control via MSR interface"); 566 298 MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>"); 567 299 MODULE_LICENSE("GPL v2"); 300 + MODULE_IMPORT_NS("INTEL_RAPL");

+101

drivers/powercap/intel_rapl_tpmi.c

··· 9 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 10 11 11 #include <linux/auxiliary_bus.h> 12 + #include <linux/bits.h> 12 13 #include <linux/intel_rapl.h> 13 14 #include <linux/intel_tpmi.h> 14 15 #include <linux/intel_vsec.h> 15 16 #include <linux/io.h> 16 17 #include <linux/module.h> 17 18 #include <linux/slab.h> 19 + #include <linux/units.h> 18 20 19 21 #define TPMI_RAPL_MAJOR_VERSION 0 20 22 #define TPMI_RAPL_MINOR_VERSION 1 ··· 61 59 static DEFINE_MUTEX(tpmi_rapl_lock); 62 60 63 61 static struct powercap_control_type *tpmi_control_type; 62 + 63 + /* bitmasks for RAPL TPMI, used by primitive access functions */ 64 + #define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0) 65 + #define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62) 66 + #define TPMI_POWER_HIGH_LOCK BIT_ULL(63) 67 + #define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18) 68 + #define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0) 69 + #define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18) 70 + #define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36) 71 + #define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54) 72 + #define TPMI_ENERGY_STATUS_MASK GENMASK(31, 0) 73 + #define TPMI_PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) 74 + 75 + /* RAPL primitives for TPMI I/F */ 76 + static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] = { 77 + /* name, mask, shift, msr index, unit divisor */ 78 + [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0, 79 + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 80 + [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0, 81 + RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0), 82 + [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0, 83 + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 84 + [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, TPMI_ENERGY_STATUS_MASK, 0, 85 + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 86 + [PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, TPMI_POWER_HIGH_LOCK, 63, 87 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 88 + [PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, TPMI_POWER_HIGH_LOCK, 63, 89 + RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), 90 + [PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, TPMI_POWER_HIGH_LOCK, 63, 91 + RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), 92 + [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 93 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 94 + [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 95 + RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), 96 + [PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 97 + RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), 98 + [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18, 99 + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 100 + [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18, 101 + RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0), 102 + [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0, 103 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 104 + [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36, 105 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 106 + [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18, 107 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 108 + [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK, 109 + 54, RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 110 + [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, 111 + TPMI_PERF_STATUS_THROTTLE_TIME_MASK, 112 + 0, RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 113 + }; 64 114 65 115 static int tpmi_rapl_read_raw(int id, struct reg_action *ra, bool atomic) 66 116 { ··· 304 250 return 0; 305 251 } 306 252 253 + /* TPMI Unit register has different layout */ 254 + #define TPMI_ENERGY_UNIT_SCALE 1000 255 + #define TPMI_POWER_UNIT_OFFSET 0x00 256 + #define TPMI_POWER_UNIT_MASK GENMASK(3, 0) 257 + #define TPMI_ENERGY_UNIT_OFFSET 0x06 258 + #define TPMI_ENERGY_UNIT_MASK GENMASK_ULL(10, 6) 259 + #define TPMI_TIME_UNIT_OFFSET 0x0C 260 + #define TPMI_TIME_UNIT_MASK GENMASK_ULL(15, 12) 261 + 262 + static int rapl_check_unit_tpmi(struct rapl_domain *rd) 263 + { 264 + struct reg_action ra; 265 + u32 value; 266 + 267 + ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 268 + ra.mask = ~0; 269 + if (tpmi_rapl_read_raw(rd->rp->id, &ra, false)) { 270 + pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 271 + ra.reg.val, rd->rp->name, rd->name); 272 + return -ENODEV; 273 + } 274 + 275 + value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET; 276 + rd->energy_unit = (TPMI_ENERGY_UNIT_SCALE * MICROJOULE_PER_JOULE) >> value; 277 + 278 + value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET; 279 + rd->power_unit = MICROWATT_PER_WATT >> value; 280 + 281 + value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET; 282 + rd->time_unit = USEC_PER_SEC >> value; 283 + 284 + pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n", 285 + rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 286 + 287 + return 0; 288 + } 289 + 290 + static const struct rapl_defaults defaults_tpmi = { 291 + .check_unit = rapl_check_unit_tpmi, 292 + /* Reuse existing logic, ignore the PL_CLAMP failures and enable all Power Limits */ 293 + .set_floor_freq = rapl_default_set_floor_freq, 294 + .compute_time_window = rapl_default_compute_time_window, 295 + }; 296 + 307 297 static int intel_rapl_tpmi_probe(struct auxiliary_device *auxdev, 308 298 const struct auxiliary_device_id *id) 309 299 { ··· 395 297 trp->priv.read_raw = tpmi_rapl_read_raw; 396 298 trp->priv.write_raw = tpmi_rapl_write_raw; 397 299 trp->priv.control_type = tpmi_control_type; 300 + trp->priv.defaults = &defaults_tpmi; 301 + trp->priv.rpi = rpi_tpmi; 398 302 399 303 /* RAPL TPMI I/F is per physical package */ 400 304 trp->rp = rapl_find_package_domain(info->package_id, &trp->priv, false); ··· 448 348 449 349 module_auxiliary_driver(intel_rapl_tpmi_driver) 450 350 351 + MODULE_IMPORT_NS("INTEL_RAPL"); 451 352 MODULE_IMPORT_NS("INTEL_TPMI"); 452 353 453 354 MODULE_DESCRIPTION("Intel RAPL TPMI Driver");

+81

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

··· 11 11 12 12 static struct rapl_if_priv rapl_mmio_priv; 13 13 14 + /* bitmasks for RAPL MSRs, used by primitive access functions */ 15 + #define MMIO_ENERGY_STATUS_MASK GENMASK(31, 0) 16 + 17 + #define MMIO_POWER_LIMIT1_MASK GENMASK(14, 0) 18 + #define MMIO_POWER_LIMIT1_ENABLE BIT(15) 19 + #define MMIO_POWER_LIMIT1_CLAMP BIT(16) 20 + 21 + #define MMIO_POWER_LIMIT2_MASK GENMASK_ULL(46, 32) 22 + #define MMIO_POWER_LIMIT2_ENABLE BIT_ULL(47) 23 + #define MMIO_POWER_LIMIT2_CLAMP BIT_ULL(48) 24 + 25 + #define MMIO_POWER_LOW_LOCK BIT(31) 26 + #define MMIO_POWER_HIGH_LOCK BIT_ULL(63) 27 + 28 + #define MMIO_POWER_LIMIT4_MASK GENMASK(12, 0) 29 + 30 + #define MMIO_TIME_WINDOW1_MASK GENMASK_ULL(23, 17) 31 + #define MMIO_TIME_WINDOW2_MASK GENMASK_ULL(55, 49) 32 + 33 + #define MMIO_POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) 34 + #define MMIO_POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) 35 + #define MMIO_POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) 36 + #define MMIO_POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) 37 + 38 + #define MMIO_PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) 39 + #define MMIO_PP_POLICY_MASK GENMASK(4, 0) 40 + 41 + /* RAPL primitives for MMIO I/F */ 42 + static struct rapl_primitive_info rpi_mmio[NR_RAPL_PRIMITIVES] = { 43 + /* name, mask, shift, msr index, unit divisor */ 44 + [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, MMIO_POWER_LIMIT1_MASK, 0, 45 + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 46 + [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, MMIO_POWER_LIMIT2_MASK, 32, 47 + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 48 + [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, MMIO_POWER_LIMIT4_MASK, 0, 49 + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 50 + [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, MMIO_ENERGY_STATUS_MASK, 0, 51 + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 52 + [FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_LOW_LOCK, 31, 53 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 54 + [FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_HIGH_LOCK, 63, 55 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 56 + [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, MMIO_POWER_LIMIT1_ENABLE, 15, 57 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 58 + [PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, MMIO_POWER_LIMIT1_CLAMP, 16, 59 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 60 + [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, MMIO_POWER_LIMIT2_ENABLE, 47, 61 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 62 + [PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, MMIO_POWER_LIMIT2_CLAMP, 48, 63 + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 64 + [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, MMIO_TIME_WINDOW1_MASK, 17, 65 + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 66 + [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, MMIO_TIME_WINDOW2_MASK, 49, 67 + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 68 + [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, 69 + MMIO_POWER_INFO_THERMAL_SPEC_MASK, 0, 70 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 71 + [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, MMIO_POWER_INFO_MAX_MASK, 32, 72 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 73 + [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, MMIO_POWER_INFO_MIN_MASK, 16, 74 + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 75 + [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, 76 + MMIO_POWER_INFO_MAX_TIME_WIN_MASK, 48, 77 + RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 78 + [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, 79 + MMIO_PERF_STATUS_THROTTLE_TIME_MASK, 0, 80 + RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 81 + [PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, MMIO_PP_POLICY_MASK, 0, 82 + RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), 83 + }; 84 + 14 85 static const struct rapl_mmio_regs rapl_mmio_default = { 15 86 .reg_unit = 0x5938, 16 87 .regs[RAPL_DOMAIN_PACKAGE] = { 0x59a0, 0x593c, 0x58f0, 0, 0x5930, 0x59b0}, 17 88 .regs[RAPL_DOMAIN_DRAM] = { 0x58e0, 0x58e8, 0x58ec, 0, 0}, 18 89 .limits[RAPL_DOMAIN_PACKAGE] = BIT(POWER_LIMIT2) | BIT(POWER_LIMIT4), 19 90 .limits[RAPL_DOMAIN_DRAM] = BIT(POWER_LIMIT2), 91 + }; 92 + 93 + static const struct rapl_defaults rapl_defaults_mmio = { 94 + .floor_freq_reg_addr = 0, 95 + .check_unit = rapl_default_check_unit, 96 + .set_floor_freq = rapl_default_set_floor_freq, 97 + .compute_time_window = rapl_default_compute_time_window, 20 98 }; 21 99 22 100 static int rapl_mmio_read_raw(int cpu, struct reg_action *ra, bool atomic) ··· 145 67 146 68 rapl_mmio_priv.read_raw = rapl_mmio_read_raw; 147 69 rapl_mmio_priv.write_raw = rapl_mmio_write_raw; 70 + rapl_mmio_priv.defaults = &rapl_defaults_mmio; 71 + rapl_mmio_priv.rpi = rpi_mmio; 148 72 149 73 rapl_mmio_priv.control_type = powercap_register_control_type(NULL, "intel-rapl-mmio", NULL); 150 74 if (IS_ERR(rapl_mmio_priv.control_type)) { ··· 191 111 EXPORT_SYMBOL_GPL(proc_thermal_rapl_remove); 192 112 193 113 MODULE_LICENSE("GPL v2"); 114 + MODULE_IMPORT_NS("INTEL_RAPL"); 194 115 MODULE_DESCRIPTION("RAPL interface using MMIO");

+47 -5

include/linux/intel_rapl.h

··· 77 77 PSYS_TIME_WINDOW1, 78 78 PSYS_TIME_WINDOW2, 79 79 /* below are not raw primitive data */ 80 - AVERAGE_POWER, 81 80 NR_RAPL_PRIMITIVES, 82 81 }; 83 82 ··· 127 128 int err; 128 129 }; 129 130 131 + struct rapl_defaults { 132 + u8 floor_freq_reg_addr; 133 + int (*check_unit)(struct rapl_domain *rd); 134 + void (*set_floor_freq)(struct rapl_domain *rd, bool mode); 135 + u64 (*compute_time_window)(struct rapl_domain *rd, u64 val, bool to_raw); 136 + unsigned int dram_domain_energy_unit; 137 + unsigned int psys_domain_energy_unit; 138 + bool spr_psys_bits; 139 + bool msr_pl4_support; 140 + bool msr_pmu_support; 141 + }; 142 + 143 + #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ 144 + .name = #p, \ 145 + .mask = m, \ 146 + .shift = s, \ 147 + .id = i, \ 148 + .unit = u, \ 149 + .flag = f \ 150 + } 151 + 152 + enum unit_type { 153 + ARBITRARY_UNIT, /* no translation */ 154 + POWER_UNIT, 155 + ENERGY_UNIT, 156 + TIME_UNIT, 157 + }; 158 + 159 + /* per domain data. used to describe individual knobs such that access function 160 + * can be consolidated into one instead of many inline functions. 161 + */ 162 + struct rapl_primitive_info { 163 + const char *name; 164 + u64 mask; 165 + int shift; 166 + enum rapl_domain_reg_id id; 167 + enum unit_type unit; 168 + u32 flag; 169 + }; 170 + 130 171 /** 131 172 * struct rapl_if_priv: private data for different RAPL interfaces 132 173 * @control_type: Each RAPL interface must have its own powercap ··· 181 142 * registers. 182 143 * @write_raw: Callback for writing RAPL interface specific 183 144 * registers. 184 - * @defaults: internal pointer to interface default settings 185 - * @rpi: internal pointer to interface primitive info 145 + * @defaults: pointer to default settings 146 + * @rpi: pointer to interface primitive info 186 147 */ 187 148 struct rapl_if_priv { 188 149 enum rapl_if_type type; ··· 193 154 int limits[RAPL_DOMAIN_MAX]; 194 155 int (*read_raw)(int id, struct reg_action *ra, bool pmu_ctx); 195 156 int (*write_raw)(int id, struct reg_action *ra); 196 - void *defaults; 197 - void *rpi; 157 + const struct rapl_defaults *defaults; 158 + struct rapl_primitive_info *rpi; 198 159 }; 199 160 200 161 #ifdef CONFIG_PERF_EVENTS ··· 250 211 struct rapl_package *rapl_find_package_domain(int id, struct rapl_if_priv *priv, bool id_is_cpu); 251 212 struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id_is_cpu); 252 213 void rapl_remove_package(struct rapl_package *rp); 214 + int rapl_default_check_unit(struct rapl_domain *rd); 215 + void rapl_default_set_floor_freq(struct rapl_domain *rd, bool mode); 216 + u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bool to_raw); 253 217 254 218 #ifdef CONFIG_PERF_EVENTS 255 219 int rapl_package_add_pmu(struct rapl_package *rp);

+2 -2

include/linux/powercap.h

··· 238 238 * Advantage of this parameter is that client can embed 239 239 * this data in its data structures and allocate in a 240 240 * single call, preventing multiple allocations. 241 - * @control_type_name: The Name of this control_type, which will be shown 241 + * @name: The Name of this control_type, which will be shown 242 242 * in the sysfs Interface. 243 243 * @ops: Callbacks for control type. This parameter is optional. 244 244 * ··· 277 277 * @name: A name for this zone. 278 278 * @parent: A pointer to the parent power zone instance if any or NULL 279 279 * @ops: Pointer to zone operation callback structure. 280 - * @no_constraints: Number of constraints for this zone 280 + * @nr_constraints: Number of constraints for this zone 281 281 * @const_ops: Pointer to constraint callback structure 282 282 * 283 283 * Register a power zone under a given control type. A power zone must register

+3

include/linux/units.h

··· 57 57 #define MICROWATT_PER_MILLIWATT 1000UL 58 58 #define MICROWATT_PER_WATT 1000000UL 59 59 60 + #define MICROJOULE_PER_JOULE 1000000UL 61 + #define NANOJOULE_PER_JOULE 1000000000UL 62 + 60 63 #define BYTES_PER_KBIT (KILO / BITS_PER_BYTE) 61 64 #define BYTES_PER_MBIT (MEGA / BITS_PER_BYTE) 62 65 #define BYTES_PER_GBIT (GIGA / BITS_PER_BYTE)

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