Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mmc-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC updates from Ulf Hansson:
"MMC core:
- Share a helper to convert from crypto_profile to mmc_host
- Respect quirk_max_rate for non-UHS SDIO card too
MMC host:
- Add DT bindings for the mmc-slot
- Clarify DT bindings for the mmc-controller
- bcm2835: Add support for system-wide suspend/resume PM
- dw_mmc-exynos: Add support for the exynos8895 variant
- meson-mx-sdio: Convert DT bindings to dtschema
- mtk-sd: Fixup use of two register ranges
- mtk-sd: Add support for ignoring cmd response CRC
- sdhci-esdhc-imx: enable 'SDHCI_QUIRK_NO_LED' quirk for S32G
- sdhci-msm: Correctly set the load for the regulator
- sdhci-msm: Convert to use custom crypto profile
- sdhci-of-at91: Add support for the microchip sama7d65 variant"
* tag 'mmc-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (25 commits)
mmc: sdhci-msm: Correctly set the load for the regulator
mmc: hi3798mv200: Use syscon_regmap_lookup_by_phandle_args
mmc: Use of_property_present() for non-boolean properties
dt-bindings: mmc: samsung,exynos-dw-mshc: add specific compatible for exynos8895
mmc: sdhci-msm: convert to use custom crypto profile
mmc: crypto: add mmc_from_crypto_profile()
mmc: mtk-sd: Limit getting top_base to SoCs that require it
dt-bindings: mmc: mtk-sd: Document compatibles that need two register ranges
mmc: sdhci-acpi: Use devm_platform_ioremap_resource()
mmc: sdhci-acpi: Remove not so useful error message
dt-bindings: mmc: convert amlogic,meson-mx-sdio.txt to dtschema
dt-bindings: mmc: document mmc-slot
dt-bindings: mmc: controller: remove '|' when not needed
dt-bindings: mmc: controller: move properties common with slot out to mmc-controller-common
dt-bindings: mmc: controller: clarify the address-cells description
mmc: bcm2835: add suspend/resume pm support
dt-bindings: Drop Bhupesh Sharma from maintainers
mmc: core: don't include 'pm_wakeup.h' directly
mmc: mtk-sd: Add support for ignoring cmd response CRC
mmc: core: Introduce the MMC_RSP_R1B_NO_CRC response
...
+750
-523
+2
-1
Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+2
-1
Documentation/devicetree/bindings/crypto/qcom-qce.yaml
-54
Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt
-54
Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt
···
1
-
* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
2
-
3
-
The highspeed MMC host controller on Amlogic SoCs provides an interface
4
-
for MMC, SD, SDIO and SDHC types of memory cards.
5
-
6
-
Supported maximum speeds are the ones of the eMMC standard 4.41 as well
7
-
as the speed of SD standard 2.0.
8
-
9
-
The hardware provides an internal "mux" which allows up to three slots
10
-
to be controlled. Only one slot can be accessed at a time.
11
-
12
-
Required properties:
13
-
- compatible : must be one of
14
-
- "amlogic,meson8-sdio"
15
-
- "amlogic,meson8b-sdio"
16
-
along with the generic "amlogic,meson-mx-sdio"
17
-
- reg : mmc controller base registers
18
-
- interrupts : mmc controller interrupt
19
-
- #address-cells : must be 1
20
-
- size-cells : must be 0
21
-
- clocks : phandle to clock providers
22
-
- clock-names : must contain "core" and "clkin"
23
-
24
-
Required child nodes:
25
-
A node for each slot provided by the MMC controller is required.
26
-
NOTE: due to a driver limitation currently only one slot (= child node)
27
-
is supported!
28
-
29
-
Required properties on each child node (= slot):
30
-
- compatible : must be "mmc-slot" (see mmc.txt within this directory)
31
-
- reg : the slot (or "port") ID
32
-
33
-
Optional properties on each child node (= slot):
34
-
- bus-width : must be 1 or 4 (8-bit bus is not supported)
35
-
- for cd and all other additional generic mmc parameters
36
-
please refer to mmc.txt within this directory
37
-
38
-
Examples:
39
-
mmc@c1108c20 {
40
-
compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
41
-
reg = <0xc1108c20 0x20>;
42
-
interrupts = <0 28 1>;
43
-
#address-cells = <1>;
44
-
#size-cells = <0>;
45
-
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
46
-
clock-names = "core", "clkin";
47
-
48
-
slot@1 {
49
-
compatible = "mmc-slot";
50
-
reg = <1>;
51
-
52
-
bus-width = <4>;
53
-
};
54
-
};
+94
Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml
+94
Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
8
+
9
+
description: |
10
+
The highspeed MMC host controller on Amlogic SoCs provides an interface
11
+
for MMC, SD, SDIO and SDHC types of memory cards.
12
+
13
+
Supported maximum speeds are the ones of the eMMC standard 4.41 as well
14
+
as the speed of SD standard 2.0.
15
+
16
+
The hardware provides an internal "mux" which allows up to three slots
17
+
to be controlled. Only one slot can be accessed at a time.
18
+
19
+
maintainers:
20
+
- Neil Armstrong <neil.armstrong@linaro.org>
21
+
22
+
properties:
23
+
compatible:
24
+
items:
25
+
- enum:
26
+
- amlogic,meson8-sdio
27
+
- amlogic,meson8b-sdio
28
+
- const: amlogic,meson-mx-sdio
29
+
30
+
reg:
31
+
maxItems: 1
32
+
33
+
interrupts:
34
+
maxItems: 1
35
+
36
+
clocks:
37
+
maxItems: 2
38
+
39
+
clock-names:
40
+
items:
41
+
- const: core
42
+
- const: clkin
43
+
44
+
"#address-cells":
45
+
const: 1
46
+
47
+
"#size-cells":
48
+
const: 0
49
+
50
+
patternProperties:
51
+
"slot@[0-2]$":
52
+
$ref: mmc-slot.yaml#
53
+
description:
54
+
A node for each slot provided by the MMC controller
55
+
56
+
properties:
57
+
reg:
58
+
enum: [0, 1, 2]
59
+
60
+
bus-width:
61
+
enum: [1, 4]
62
+
63
+
unevaluatedProperties: false
64
+
65
+
required:
66
+
- compatible
67
+
- reg
68
+
- interrupts
69
+
- clocks
70
+
- clock-names
71
+
- "#address-cells"
72
+
- "#size-cells"
73
+
74
+
additionalProperties: false
75
+
76
+
examples:
77
+
- |
78
+
#include <dt-bindings/interrupt-controller/irq.h>
79
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
80
+
mmc@c1108c20 {
81
+
compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
82
+
reg = <0xc1108c20 0x20>;
83
+
interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
84
+
clocks = <&clk_core>, <&clk_in>;
85
+
clock-names = "core", "clkin";
86
+
#address-cells = <1>;
87
+
#size-cells = <0>;
88
+
89
+
slot@1 {
90
+
compatible = "mmc-slot";
91
+
reg = <1>;
92
+
bus-width = <4>;
93
+
};
94
+
};
+1
Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml
+1
Documentation/devicetree/bindings/mmc/atmel,sama5d2-sdhci.yaml
+22
-26
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
+22
-26
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
···
38
38
39
39
reg:
40
40
minItems: 1
41
-
maxItems: 2
42
-
description: |
43
-
For "marvell,armada-3700-sdhci", two register areas. The first one
44
-
for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
45
-
Voltage Control register. Please follow the examples with compatible
46
-
"marvell,armada-3700-sdhci" in below.
47
-
Please also check property marvell,pad-type in below.
48
-
49
-
For other compatible strings, one register area for Xenon IP.
41
+
items:
42
+
- description: Xenon IP registers
43
+
- description: Armada 3700 SoC PHY PAD Voltage Control register
50
44
51
45
clocks:
52
46
minItems: 1
···
54
60
55
61
interrupts:
56
62
maxItems: 1
63
+
64
+
marvell,pad-type:
65
+
$ref: /schemas/types.yaml#/definitions/string
66
+
enum:
67
+
- sd
68
+
- fixed-1-8v
69
+
description:
70
+
Type of Armada 3700 SoC PHY PAD Voltage Controller register. If "sd" is
71
+
selected, SoC PHY PAD is set as 3.3V at the beginning and is switched to
72
+
1.8V when later in higher speed mode. If "fixed-1-8v" is selected, SoC PHY
73
+
PAD is fixed 1.8V, such as for eMMC.
57
74
58
75
marvell,xenon-sdhc-id:
59
76
$ref: /schemas/types.yaml#/definitions/uint32
···
152
147
then:
153
148
properties:
154
149
reg:
155
-
items:
156
-
- description: Xenon IP registers
157
-
- description: Armada 3700 SoC PHY PAD Voltage Control register
158
-
159
-
marvell,pad-type:
160
-
$ref: /schemas/types.yaml#/definitions/string
161
-
enum:
162
-
- sd
163
-
- fixed-1-8v
164
-
description: |
165
-
Type of Armada 3700 SoC PHY PAD Voltage Controller register.
166
-
If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
167
-
and is switched to 1.8V when later in higher speed mode.
168
-
If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
169
-
eMMC.
170
-
Please follow the examples with compatible
171
-
"marvell,armada-3700-sdhci" in below.
150
+
minItems: 2
172
151
173
152
required:
174
153
- marvell,pad-type
154
+
155
+
else:
156
+
properties:
157
+
reg:
158
+
maxItems: 1
159
+
160
+
marvell,pad-type: false
175
161
176
162
- if:
177
163
properties:
+357
Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
+357
Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MMC Controller & Slots Common Properties
8
+
9
+
maintainers:
10
+
- Ulf Hansson <ulf.hansson@linaro.org>
11
+
12
+
description:
13
+
These properties are common to multiple MMC host controllers and the
14
+
possible slots or ports for multi-slot controllers.
15
+
16
+
properties:
17
+
"#address-cells":
18
+
const: 1
19
+
description:
20
+
The cell is the SDIO function number if a function subnode is used.
21
+
22
+
"#size-cells":
23
+
const: 0
24
+
25
+
# Card Detection.
26
+
# If none of these properties are supplied, the host native card
27
+
# detect will be used. Only one of them should be provided.
28
+
29
+
broken-cd:
30
+
$ref: /schemas/types.yaml#/definitions/flag
31
+
description:
32
+
There is no card detection available; polling must be used.
33
+
34
+
cd-gpios:
35
+
maxItems: 1
36
+
description:
37
+
The card detection will be done using the GPIO provided.
38
+
39
+
non-removable:
40
+
$ref: /schemas/types.yaml#/definitions/flag
41
+
description:
42
+
Non-removable slot (like eMMC); assume always present.
43
+
44
+
# *NOTE* on CD and WP polarity. To use common for all SD/MMC host
45
+
# controllers line polarity properties, we have to fix the meaning
46
+
# of the "normal" and "inverted" line levels. We choose to follow
47
+
# the SDHCI standard, which specifies both those lines as "active
48
+
# low." Therefore, using the "cd-inverted" property means, that the
49
+
# CD line is active high, i.e. it is high, when a card is
50
+
# inserted. Similar logic applies to the "wp-inverted" property.
51
+
#
52
+
# CD and WP lines can be implemented on the hardware in one of two
53
+
# ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
54
+
# as dedicated pins. Polarity of dedicated pins can be specified,
55
+
# using *-inverted properties. GPIO polarity can also be specified
56
+
# using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
57
+
# latter case. We choose to use the XOR logic for GPIO CD and WP
58
+
# lines. This means, the two properties are "superimposed," for
59
+
# example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
60
+
# respective *-inverted property property results in a
61
+
# double-inversion and actually means the "normal" line polarity is
62
+
# in effect.
63
+
wp-inverted:
64
+
$ref: /schemas/types.yaml#/definitions/flag
65
+
description:
66
+
The Write Protect line polarity is inverted.
67
+
68
+
cd-inverted:
69
+
$ref: /schemas/types.yaml#/definitions/flag
70
+
description:
71
+
The CD line polarity is inverted.
72
+
73
+
# Other properties
74
+
75
+
bus-width:
76
+
description:
77
+
Number of data lines.
78
+
$ref: /schemas/types.yaml#/definitions/uint32
79
+
enum: [1, 4, 8]
80
+
default: 1
81
+
82
+
max-frequency:
83
+
description: |
84
+
Maximum operating frequency of the bus:
85
+
- for eMMC, the maximum supported frequency is 200MHz,
86
+
- for SD/SDIO cards the SDR104 mode has a max supported
87
+
frequency of 208MHz,
88
+
- some mmc host controllers do support a max frequency upto
89
+
384MHz.
90
+
So, lets keep the maximum supported value here.
91
+
92
+
$ref: /schemas/types.yaml#/definitions/uint32
93
+
minimum: 400000
94
+
maximum: 384000000
95
+
96
+
disable-wp:
97
+
$ref: /schemas/types.yaml#/definitions/flag
98
+
description:
99
+
When set, no physical write-protect line is present. This
100
+
property should only be specified when the controller has a
101
+
dedicated write-protect detection logic. If a GPIO is always used
102
+
for the write-protect detection logic, it is sufficient to not
103
+
specify the wp-gpios property in the absence of a write-protect
104
+
line. Not used in combination with eMMC or SDIO.
105
+
106
+
wp-gpios:
107
+
maxItems: 1
108
+
description:
109
+
GPIO to use for the write-protect detection.
110
+
111
+
cd-debounce-delay-ms:
112
+
description:
113
+
Set delay time before detecting card after card insert
114
+
interrupt.
115
+
116
+
no-1-8-v:
117
+
$ref: /schemas/types.yaml#/definitions/flag
118
+
description:
119
+
When specified, denotes that 1.8V card voltage is not supported
120
+
on this system, even if the controller claims it.
121
+
122
+
cap-sd-highspeed:
123
+
$ref: /schemas/types.yaml#/definitions/flag
124
+
description:
125
+
SD high-speed timing is supported.
126
+
127
+
cap-mmc-highspeed:
128
+
$ref: /schemas/types.yaml#/definitions/flag
129
+
description:
130
+
MMC high-speed timing is supported.
131
+
132
+
sd-uhs-sdr12:
133
+
$ref: /schemas/types.yaml#/definitions/flag
134
+
description:
135
+
SD UHS SDR12 speed is supported.
136
+
137
+
sd-uhs-sdr25:
138
+
$ref: /schemas/types.yaml#/definitions/flag
139
+
description:
140
+
SD UHS SDR25 speed is supported.
141
+
142
+
sd-uhs-sdr50:
143
+
$ref: /schemas/types.yaml#/definitions/flag
144
+
description:
145
+
SD UHS SDR50 speed is supported.
146
+
147
+
sd-uhs-sdr104:
148
+
$ref: /schemas/types.yaml#/definitions/flag
149
+
description:
150
+
SD UHS SDR104 speed is supported.
151
+
152
+
sd-uhs-ddr50:
153
+
$ref: /schemas/types.yaml#/definitions/flag
154
+
description:
155
+
SD UHS DDR50 speed is supported.
156
+
157
+
cap-power-off-card:
158
+
$ref: /schemas/types.yaml#/definitions/flag
159
+
description:
160
+
Powering off the card is safe.
161
+
162
+
cap-mmc-hw-reset:
163
+
$ref: /schemas/types.yaml#/definitions/flag
164
+
description:
165
+
eMMC hardware reset is supported
166
+
167
+
cap-sdio-irq:
168
+
$ref: /schemas/types.yaml#/definitions/flag
169
+
description:
170
+
enable SDIO IRQ signalling on this interface
171
+
172
+
full-pwr-cycle:
173
+
$ref: /schemas/types.yaml#/definitions/flag
174
+
description:
175
+
Full power cycle of the card is supported.
176
+
177
+
full-pwr-cycle-in-suspend:
178
+
$ref: /schemas/types.yaml#/definitions/flag
179
+
description:
180
+
Full power cycle of the card in suspend is supported.
181
+
182
+
mmc-ddr-1_2v:
183
+
$ref: /schemas/types.yaml#/definitions/flag
184
+
description:
185
+
eMMC high-speed DDR mode (1.2V I/O) is supported.
186
+
187
+
mmc-ddr-1_8v:
188
+
$ref: /schemas/types.yaml#/definitions/flag
189
+
description:
190
+
eMMC high-speed DDR mode (1.8V I/O) is supported.
191
+
192
+
mmc-ddr-3_3v:
193
+
$ref: /schemas/types.yaml#/definitions/flag
194
+
description:
195
+
eMMC high-speed DDR mode (3.3V I/O) is supported.
196
+
197
+
mmc-hs200-1_2v:
198
+
$ref: /schemas/types.yaml#/definitions/flag
199
+
description:
200
+
eMMC HS200 mode (1.2V I/O) is supported.
201
+
202
+
mmc-hs200-1_8v:
203
+
$ref: /schemas/types.yaml#/definitions/flag
204
+
description:
205
+
eMMC HS200 mode (1.8V I/O) is supported.
206
+
207
+
mmc-hs400-1_2v:
208
+
$ref: /schemas/types.yaml#/definitions/flag
209
+
description:
210
+
eMMC HS400 mode (1.2V I/O) is supported.
211
+
212
+
mmc-hs400-1_8v:
213
+
$ref: /schemas/types.yaml#/definitions/flag
214
+
description:
215
+
eMMC HS400 mode (1.8V I/O) is supported.
216
+
217
+
mmc-hs400-enhanced-strobe:
218
+
$ref: /schemas/types.yaml#/definitions/flag
219
+
description:
220
+
eMMC HS400 enhanced strobe mode is supported
221
+
222
+
no-mmc-hs400:
223
+
$ref: /schemas/types.yaml#/definitions/flag
224
+
description:
225
+
All eMMC HS400 modes are not supported.
226
+
227
+
dsr:
228
+
description:
229
+
Value the card Driver Stage Register (DSR) should be programmed
230
+
with.
231
+
$ref: /schemas/types.yaml#/definitions/uint32
232
+
minimum: 0
233
+
maximum: 0xffff
234
+
235
+
no-sdio:
236
+
$ref: /schemas/types.yaml#/definitions/flag
237
+
description:
238
+
Controller is limited to send SDIO commands during
239
+
initialization.
240
+
241
+
no-sd:
242
+
$ref: /schemas/types.yaml#/definitions/flag
243
+
description:
244
+
Controller is limited to send SD commands during initialization.
245
+
246
+
no-mmc:
247
+
$ref: /schemas/types.yaml#/definitions/flag
248
+
description:
249
+
Controller is limited to send MMC commands during
250
+
initialization.
251
+
252
+
fixed-emmc-driver-type:
253
+
description:
254
+
For non-removable eMMC, enforce this driver type. The value is
255
+
the driver type as specified in the eMMC specification (table
256
+
206 in spec version 5.1)
257
+
$ref: /schemas/types.yaml#/definitions/uint32
258
+
minimum: 0
259
+
maximum: 4
260
+
261
+
post-power-on-delay-ms:
262
+
description:
263
+
It was invented for MMC pwrseq-simple which could be referred to
264
+
mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
265
+
waiting for I/O signalling and card power supply to be stable,
266
+
regardless of whether pwrseq-simple is used. Default to 10ms if
267
+
no available.
268
+
default: 10
269
+
270
+
supports-cqe:
271
+
$ref: /schemas/types.yaml#/definitions/flag
272
+
description:
273
+
The presence of this property indicates that the corresponding
274
+
MMC host controller supports HW command queue feature.
275
+
276
+
disable-cqe-dcmd:
277
+
$ref: /schemas/types.yaml#/definitions/flag
278
+
description:
279
+
The presence of this property indicates that the MMC
280
+
controller\'s command queue engine (CQE) does not support direct
281
+
commands (DCMDs).
282
+
283
+
keep-power-in-suspend:
284
+
$ref: /schemas/types.yaml#/definitions/flag
285
+
description:
286
+
SDIO only. Preserves card power during a suspend/resume cycle.
287
+
288
+
wakeup-source:
289
+
$ref: /schemas/types.yaml#/definitions/flag
290
+
description:
291
+
SDIO only. Enables wake up of host system on SDIO IRQ assertion.
292
+
293
+
vmmc-supply:
294
+
description:
295
+
Supply for the card power
296
+
297
+
vqmmc-supply:
298
+
description:
299
+
Supply for the bus IO line power, such as a level shifter.
300
+
If the level shifter is controlled by a GPIO line, this shall
301
+
be modeled as a "regulator-fixed" with a GPIO line for
302
+
switching the level shifter on/off.
303
+
304
+
mmc-pwrseq:
305
+
$ref: /schemas/types.yaml#/definitions/phandle
306
+
description:
307
+
System-on-Chip designs may specify a specific MMC power
308
+
sequence. To successfully detect an (e)MMC/SD/SDIO card, that
309
+
power sequence must be maintained while initializing the card.
310
+
311
+
patternProperties:
312
+
"^.*@[0-9]+$":
313
+
type: object
314
+
description: |
315
+
On embedded systems the cards connected to a host may need
316
+
additional properties. These can be specified in subnodes to the
317
+
host controller node. The subnodes are identified by the
318
+
standard \'reg\' property. Which information exactly can be
319
+
specified depends on the bindings for the SDIO function driver
320
+
for the subnode, as specified by the compatible string.
321
+
322
+
properties:
323
+
compatible:
324
+
description:
325
+
Name of SDIO function following generic names recommended
326
+
practice
327
+
328
+
reg:
329
+
items:
330
+
- minimum: 0
331
+
maximum: 7
332
+
description:
333
+
Must contain the SDIO function number of the function this
334
+
subnode describes. A value of 0 denotes the memory SD
335
+
function, values from 1 to 7 denote the SDIO functions.
336
+
337
+
required:
338
+
- reg
339
+
340
+
"^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
341
+
$ref: /schemas/types.yaml#/definitions/uint32-array
342
+
343
+
minItems: 2
344
+
maxItems: 2
345
+
items:
346
+
minimum: 0
347
+
maximum: 359
348
+
description:
349
+
Set the clock (phase) delays which are to be configured in the
350
+
controller while switching to particular speed mode. These values
351
+
are in pair of degrees.
352
+
353
+
dependencies:
354
+
cd-debounce-delay-ms: [ cd-gpios ]
355
+
fixed-emmc-driver-type: [ non-removable ]
356
+
357
+
additionalProperties: true
+4
-342
Documentation/devicetree/bindings/mmc/mmc-controller.yaml
+4
-342
Documentation/devicetree/bindings/mmc/mmc-controller.yaml
···
9
9
maintainers:
10
10
- Ulf Hansson <ulf.hansson@linaro.org>
11
11
12
-
description: |
12
+
description:
13
13
These properties are common to multiple MMC host controllers. Any host
14
14
that requires the respective functionality should implement them using
15
15
these definitions.
···
18
18
(and the corresponding mmcblkN devices) by defining an alias in the
19
19
/aliases device tree node.
20
20
21
+
$ref: mmc-controller-common.yaml#
22
+
21
23
properties:
22
24
$nodename:
23
25
pattern: "^mmc(@.*)?$"
24
26
25
-
"#address-cells":
26
-
const: 1
27
-
description: |
28
-
The cell is the slot ID if a function subnode is used.
29
-
30
-
"#size-cells":
31
-
const: 0
32
-
33
-
# Card Detection.
34
-
# If none of these properties are supplied, the host native card
35
-
# detect will be used. Only one of them should be provided.
36
-
37
-
broken-cd:
38
-
$ref: /schemas/types.yaml#/definitions/flag
39
-
description:
40
-
There is no card detection available; polling must be used.
41
-
42
-
cd-gpios:
43
-
maxItems: 1
44
-
description:
45
-
The card detection will be done using the GPIO provided.
46
-
47
-
non-removable:
48
-
$ref: /schemas/types.yaml#/definitions/flag
49
-
description:
50
-
Non-removable slot (like eMMC); assume always present.
51
-
52
-
# *NOTE* on CD and WP polarity. To use common for all SD/MMC host
53
-
# controllers line polarity properties, we have to fix the meaning
54
-
# of the "normal" and "inverted" line levels. We choose to follow
55
-
# the SDHCI standard, which specifies both those lines as "active
56
-
# low." Therefore, using the "cd-inverted" property means, that the
57
-
# CD line is active high, i.e. it is high, when a card is
58
-
# inserted. Similar logic applies to the "wp-inverted" property.
59
-
#
60
-
# CD and WP lines can be implemented on the hardware in one of two
61
-
# ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
62
-
# as dedicated pins. Polarity of dedicated pins can be specified,
63
-
# using *-inverted properties. GPIO polarity can also be specified
64
-
# using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
65
-
# latter case. We choose to use the XOR logic for GPIO CD and WP
66
-
# lines. This means, the two properties are "superimposed," for
67
-
# example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
68
-
# respective *-inverted property property results in a
69
-
# double-inversion and actually means the "normal" line polarity is
70
-
# in effect.
71
-
wp-inverted:
72
-
$ref: /schemas/types.yaml#/definitions/flag
73
-
description:
74
-
The Write Protect line polarity is inverted.
75
-
76
-
cd-inverted:
77
-
$ref: /schemas/types.yaml#/definitions/flag
78
-
description:
79
-
The CD line polarity is inverted.
80
-
81
-
# Other properties
82
-
83
-
bus-width:
84
-
description:
85
-
Number of data lines.
86
-
$ref: /schemas/types.yaml#/definitions/uint32
87
-
enum: [1, 4, 8]
88
-
default: 1
89
-
90
-
max-frequency:
91
-
description: |
92
-
Maximum operating frequency of the bus:
93
-
- for eMMC, the maximum supported frequency is 200MHz,
94
-
- for SD/SDIO cards the SDR104 mode has a max supported
95
-
frequency of 208MHz,
96
-
- some mmc host controllers do support a max frequency upto
97
-
384MHz.
98
-
So, lets keep the maximum supported value here.
99
-
100
-
$ref: /schemas/types.yaml#/definitions/uint32
101
-
minimum: 400000
102
-
maximum: 384000000
103
-
104
-
disable-wp:
105
-
$ref: /schemas/types.yaml#/definitions/flag
106
-
description:
107
-
When set, no physical write-protect line is present. This
108
-
property should only be specified when the controller has a
109
-
dedicated write-protect detection logic. If a GPIO is always used
110
-
for the write-protect detection logic, it is sufficient to not
111
-
specify the wp-gpios property in the absence of a write-protect
112
-
line. Not used in combination with eMMC or SDIO.
113
-
114
-
wp-gpios:
115
-
maxItems: 1
116
-
description:
117
-
GPIO to use for the write-protect detection.
118
-
119
-
cd-debounce-delay-ms:
120
-
description:
121
-
Set delay time before detecting card after card insert
122
-
interrupt.
123
-
124
-
no-1-8-v:
125
-
$ref: /schemas/types.yaml#/definitions/flag
126
-
description:
127
-
When specified, denotes that 1.8V card voltage is not supported
128
-
on this system, even if the controller claims it.
129
-
130
-
cap-sd-highspeed:
131
-
$ref: /schemas/types.yaml#/definitions/flag
132
-
description:
133
-
SD high-speed timing is supported.
134
-
135
-
cap-mmc-highspeed:
136
-
$ref: /schemas/types.yaml#/definitions/flag
137
-
description:
138
-
MMC high-speed timing is supported.
139
-
140
-
sd-uhs-sdr12:
141
-
$ref: /schemas/types.yaml#/definitions/flag
142
-
description:
143
-
SD UHS SDR12 speed is supported.
144
-
145
-
sd-uhs-sdr25:
146
-
$ref: /schemas/types.yaml#/definitions/flag
147
-
description:
148
-
SD UHS SDR25 speed is supported.
149
-
150
-
sd-uhs-sdr50:
151
-
$ref: /schemas/types.yaml#/definitions/flag
152
-
description:
153
-
SD UHS SDR50 speed is supported.
154
-
155
-
sd-uhs-sdr104:
156
-
$ref: /schemas/types.yaml#/definitions/flag
157
-
description:
158
-
SD UHS SDR104 speed is supported.
159
-
160
-
sd-uhs-ddr50:
161
-
$ref: /schemas/types.yaml#/definitions/flag
162
-
description:
163
-
SD UHS DDR50 speed is supported.
164
-
165
-
cap-power-off-card:
166
-
$ref: /schemas/types.yaml#/definitions/flag
167
-
description:
168
-
Powering off the card is safe.
169
-
170
-
cap-mmc-hw-reset:
171
-
$ref: /schemas/types.yaml#/definitions/flag
172
-
description:
173
-
eMMC hardware reset is supported
174
-
175
-
cap-sdio-irq:
176
-
$ref: /schemas/types.yaml#/definitions/flag
177
-
description:
178
-
enable SDIO IRQ signalling on this interface
179
-
180
-
full-pwr-cycle:
181
-
$ref: /schemas/types.yaml#/definitions/flag
182
-
description:
183
-
Full power cycle of the card is supported.
184
-
185
-
full-pwr-cycle-in-suspend:
186
-
$ref: /schemas/types.yaml#/definitions/flag
187
-
description:
188
-
Full power cycle of the card in suspend is supported.
189
-
190
-
mmc-ddr-1_2v:
191
-
$ref: /schemas/types.yaml#/definitions/flag
192
-
description:
193
-
eMMC high-speed DDR mode (1.2V I/O) is supported.
194
-
195
-
mmc-ddr-1_8v:
196
-
$ref: /schemas/types.yaml#/definitions/flag
197
-
description:
198
-
eMMC high-speed DDR mode (1.8V I/O) is supported.
199
-
200
-
mmc-ddr-3_3v:
201
-
$ref: /schemas/types.yaml#/definitions/flag
202
-
description:
203
-
eMMC high-speed DDR mode (3.3V I/O) is supported.
204
-
205
-
mmc-hs200-1_2v:
206
-
$ref: /schemas/types.yaml#/definitions/flag
207
-
description:
208
-
eMMC HS200 mode (1.2V I/O) is supported.
209
-
210
-
mmc-hs200-1_8v:
211
-
$ref: /schemas/types.yaml#/definitions/flag
212
-
description:
213
-
eMMC HS200 mode (1.8V I/O) is supported.
214
-
215
-
mmc-hs400-1_2v:
216
-
$ref: /schemas/types.yaml#/definitions/flag
217
-
description:
218
-
eMMC HS400 mode (1.2V I/O) is supported.
219
-
220
-
mmc-hs400-1_8v:
221
-
$ref: /schemas/types.yaml#/definitions/flag
222
-
description:
223
-
eMMC HS400 mode (1.8V I/O) is supported.
224
-
225
-
mmc-hs400-enhanced-strobe:
226
-
$ref: /schemas/types.yaml#/definitions/flag
227
-
description:
228
-
eMMC HS400 enhanced strobe mode is supported
229
-
230
-
no-mmc-hs400:
231
-
$ref: /schemas/types.yaml#/definitions/flag
232
-
description:
233
-
All eMMC HS400 modes are not supported.
234
-
235
-
dsr:
236
-
description:
237
-
Value the card Driver Stage Register (DSR) should be programmed
238
-
with.
239
-
$ref: /schemas/types.yaml#/definitions/uint32
240
-
minimum: 0
241
-
maximum: 0xffff
242
-
243
-
no-sdio:
244
-
$ref: /schemas/types.yaml#/definitions/flag
245
-
description:
246
-
Controller is limited to send SDIO commands during
247
-
initialization.
248
-
249
-
no-sd:
250
-
$ref: /schemas/types.yaml#/definitions/flag
251
-
description:
252
-
Controller is limited to send SD commands during initialization.
253
-
254
-
no-mmc:
255
-
$ref: /schemas/types.yaml#/definitions/flag
256
-
description:
257
-
Controller is limited to send MMC commands during
258
-
initialization.
259
-
260
-
fixed-emmc-driver-type:
261
-
description:
262
-
For non-removable eMMC, enforce this driver type. The value is
263
-
the driver type as specified in the eMMC specification (table
264
-
206 in spec version 5.1)
265
-
$ref: /schemas/types.yaml#/definitions/uint32
266
-
minimum: 0
267
-
maximum: 4
268
-
269
-
post-power-on-delay-ms:
270
-
description:
271
-
It was invented for MMC pwrseq-simple which could be referred to
272
-
mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
273
-
waiting for I/O signalling and card power supply to be stable,
274
-
regardless of whether pwrseq-simple is used. Default to 10ms if
275
-
no available.
276
-
default: 10
277
-
278
-
supports-cqe:
279
-
$ref: /schemas/types.yaml#/definitions/flag
280
-
description:
281
-
The presence of this property indicates that the corresponding
282
-
MMC host controller supports HW command queue feature.
283
-
284
-
disable-cqe-dcmd:
285
-
$ref: /schemas/types.yaml#/definitions/flag
286
-
description:
287
-
The presence of this property indicates that the MMC
288
-
controller\'s command queue engine (CQE) does not support direct
289
-
commands (DCMDs).
290
-
291
-
keep-power-in-suspend:
292
-
$ref: /schemas/types.yaml#/definitions/flag
293
-
description:
294
-
SDIO only. Preserves card power during a suspend/resume cycle.
295
-
296
-
wakeup-source:
297
-
$ref: /schemas/types.yaml#/definitions/flag
298
-
description:
299
-
SDIO only. Enables wake up of host system on SDIO IRQ assertion.
300
-
301
-
vmmc-supply:
302
-
description:
303
-
Supply for the card power
304
-
305
-
vqmmc-supply:
306
-
description:
307
-
Supply for the bus IO line power, such as a level shifter.
308
-
If the level shifter is controlled by a GPIO line, this shall
309
-
be modeled as a "regulator-fixed" with a GPIO line for
310
-
switching the level shifter on/off.
311
-
312
-
mmc-pwrseq:
313
-
$ref: /schemas/types.yaml#/definitions/phandle
314
-
description:
315
-
System-on-Chip designs may specify a specific MMC power
316
-
sequence. To successfully detect an (e)MMC/SD/SDIO card, that
317
-
power sequence must be maintained while initializing the card.
318
-
319
-
patternProperties:
320
-
"^.*@[0-9]+$":
321
-
type: object
322
-
description: |
323
-
On embedded systems the cards connected to a host may need
324
-
additional properties. These can be specified in subnodes to the
325
-
host controller node. The subnodes are identified by the
326
-
standard \'reg\' property. Which information exactly can be
327
-
specified depends on the bindings for the SDIO function driver
328
-
for the subnode, as specified by the compatible string.
329
-
330
-
properties:
331
-
compatible:
332
-
description: |
333
-
Name of SDIO function following generic names recommended
334
-
practice
335
-
336
-
reg:
337
-
items:
338
-
- minimum: 0
339
-
maximum: 7
340
-
description:
341
-
Must contain the SDIO function number of the function this
342
-
subnode describes. A value of 0 denotes the memory SD
343
-
function, values from 1 to 7 denote the SDIO functions.
344
-
345
-
required:
346
-
- reg
347
-
348
-
"^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
349
-
$ref: /schemas/types.yaml#/definitions/uint32-array
350
-
351
-
minItems: 2
352
-
maxItems: 2
353
-
items:
354
-
minimum: 0
355
-
maximum: 359
356
-
description:
357
-
Set the clock (phase) delays which are to be configured in the
358
-
controller while switching to particular speed mode. These values
359
-
are in pair of degrees.
360
-
361
-
dependencies:
362
-
cd-debounce-delay-ms: [ cd-gpios ]
363
-
fixed-emmc-driver-type: [ non-removable ]
364
-
365
-
additionalProperties: true
27
+
unevaluatedProperties: true
366
28
367
29
examples:
368
30
- |
+49
Documentation/devicetree/bindings/mmc/mmc-slot.yaml
+49
Documentation/devicetree/bindings/mmc/mmc-slot.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mmc/mmc-slot.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MMC slot properties
8
+
9
+
maintainers:
10
+
- Ulf Hansson <ulf.hansson@linaro.org>
11
+
12
+
description:
13
+
These properties defines slot properties for MMC controlers that
14
+
have multiple slots or ports provided by the same controller and
15
+
sharing the same resources.
16
+
17
+
$ref: mmc-controller-common.yaml#
18
+
19
+
properties:
20
+
$nodename:
21
+
pattern: "^slot(@.*)?$"
22
+
23
+
compatible:
24
+
const: mmc-slot
25
+
26
+
reg:
27
+
description:
28
+
the slot (or "port") ID
29
+
maxItems: 1
30
+
31
+
required:
32
+
- compatible
33
+
- reg
34
+
35
+
unevaluatedProperties: false
36
+
37
+
examples:
38
+
- |
39
+
mmc {
40
+
#address-cells = <1>;
41
+
#size-cells = <0>;
42
+
slot@0 {
43
+
compatible = "mmc-slot";
44
+
reg = <0>;
45
+
bus-width = <4>;
46
+
};
47
+
};
48
+
49
+
...
+9
-1
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+9
-1
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
···
235
235
properties:
236
236
compatible:
237
237
contains:
238
-
const: mediatek,mt8183-mmc
238
+
enum:
239
+
- mediatek,mt7986-mmc
240
+
- mediatek,mt7988-mmc
241
+
- mediatek,mt8183-mmc
242
+
- mediatek,mt8196-mmc
239
243
then:
240
244
properties:
241
245
reg:
242
246
minItems: 2
247
+
else:
248
+
properties:
249
+
reg:
250
+
maxItems: 1
243
251
244
252
- if:
245
253
properties:
+1
Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml
+1
Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml
+2
-1
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+2
-1
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
···
7
7
title: Qualcomm SDHCI controller (sdhci-msm)
8
8
9
9
maintainers:
10
-
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konradybcio@kernel.org>
11
12
12
13
description:
13
14
Secure Digital Host Controller Interface (SDHCI) present on
+2
-1
Documentation/devicetree/bindings/net/qcom,ethqos.yaml
+2
-1
Documentation/devicetree/bindings/net/qcom,ethqos.yaml
···
7
7
title: Qualcomm Ethernet ETHQOS device
8
8
9
9
maintainers:
10
-
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konradybcio@kernel.org>
11
12
12
13
description:
13
14
dwmmac based Qualcomm ethernet devices which support Gigabit
+2
-1
Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml
+2
-1
Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml
···
7
7
title: Qualcomm SM6115 Peripheral Authentication Service
8
8
9
9
maintainers:
10
-
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konradybcio@kernel.org>
11
12
12
13
description:
13
14
Qualcomm SM6115 SoC Peripheral Authentication Service loads and boots
+2
-5
drivers/mmc/core/core.c
+2
-5
drivers/mmc/core/core.c
···
19
19
#include <linux/scatterlist.h>
20
20
#include <linux/log2.h>
21
21
#include <linux/pm_runtime.h>
22
-
#include <linux/pm_wakeup.h>
23
22
#include <linux/suspend.h>
24
23
#include <linux/fault-inject.h>
25
24
#include <linux/random.h>
···
556
557
557
558
memset(&cmd, 0, sizeof(cmd));
558
559
cmd.opcode = MMC_STOP_TRANSMISSION;
559
-
cmd.flags = MMC_RSP_R1B | MMC_CMD_AC;
560
-
cmd.flags &= ~MMC_RSP_CRC; /* Ignore CRC */
560
+
cmd.flags = MMC_RSP_R1B_NO_CRC | MMC_CMD_AC; /* Ignore CRC */
561
561
cmd.busy_timeout = MMC_CQE_RECOVERY_TIMEOUT;
562
562
mmc_wait_for_cmd(host, &cmd, MMC_CMD_RETRIES);
563
563
···
565
567
memset(&cmd, 0, sizeof(cmd));
566
568
cmd.opcode = MMC_CMDQ_TASK_MGMT;
567
569
cmd.arg = 1; /* Discard entire queue */
568
-
cmd.flags = MMC_RSP_R1B | MMC_CMD_AC;
569
-
cmd.flags &= ~MMC_RSP_CRC; /* Ignore CRC */
570
+
cmd.flags = MMC_RSP_R1B_NO_CRC | MMC_CMD_AC; /* Ignore CRC */
570
571
cmd.busy_timeout = MMC_CQE_RECOVERY_TIMEOUT;
571
572
err = mmc_wait_for_cmd(host, &cmd, MMC_CMD_RETRIES);
572
573
-1
drivers/mmc/core/host.c
-1
drivers/mmc/core/host.c
+2
drivers/mmc/core/sdio.c
+2
drivers/mmc/core/sdio.c
+20
drivers/mmc/host/bcm2835.c
+20
drivers/mmc/host/bcm2835.c
···
1343
1343
return 0;
1344
1344
}
1345
1345
1346
+
static int bcm2835_suspend(struct device *dev)
1347
+
{
1348
+
struct bcm2835_host *host = dev_get_drvdata(dev);
1349
+
1350
+
clk_disable_unprepare(host->clk);
1351
+
1352
+
return 0;
1353
+
}
1354
+
1355
+
static int bcm2835_resume(struct device *dev)
1356
+
{
1357
+
struct bcm2835_host *host = dev_get_drvdata(dev);
1358
+
1359
+
return clk_prepare_enable(host->clk);
1360
+
}
1361
+
1362
+
static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pm_ops, bcm2835_suspend,
1363
+
bcm2835_resume);
1364
+
1346
1365
static int bcm2835_probe(struct platform_device *pdev)
1347
1366
{
1348
1367
struct device *dev = &pdev->dev;
···
1490
1471
.name = "sdhost-bcm2835",
1491
1472
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1492
1473
.of_match_table = bcm2835_match,
1474
+
.pm = pm_ptr(&bcm2835_pm_ops),
1493
1475
},
1494
1476
};
1495
1477
module_platform_driver(bcm2835_driver);
+17
-21
drivers/mmc/host/cqhci-crypto.c
+17
-21
drivers/mmc/host/cqhci-crypto.c
···
25
25
static inline struct cqhci_host *
26
26
cqhci_host_from_crypto_profile(struct blk_crypto_profile *profile)
27
27
{
28
-
struct mmc_host *mmc =
29
-
container_of(profile, struct mmc_host, crypto_profile);
30
-
31
-
return mmc->cqe_private;
28
+
return mmc_from_crypto_profile(profile)->cqe_private;
32
29
}
33
30
34
-
static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
35
-
const union cqhci_crypto_cfg_entry *cfg,
36
-
int slot)
31
+
static void cqhci_crypto_program_key(struct cqhci_host *cq_host,
32
+
const union cqhci_crypto_cfg_entry *cfg,
33
+
int slot)
37
34
{
38
35
u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg);
39
36
int i;
40
-
41
-
if (cq_host->ops->program_key)
42
-
return cq_host->ops->program_key(cq_host, cfg, slot);
43
37
44
38
/* Clear CFGE */
45
39
cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
···
49
55
/* Write dword 16, which includes the new value of CFGE */
50
56
cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),
51
57
slot_offset + 16 * sizeof(cfg->reg_val[0]));
52
-
return 0;
53
58
}
54
59
55
60
static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile,
···
65
72
int i;
66
73
int cap_idx = -1;
67
74
union cqhci_crypto_cfg_entry cfg = {};
68
-
int err;
69
75
70
76
BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
71
77
for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {
···
91
99
memcpy(cfg.crypto_key, key->raw, key->size);
92
100
}
93
101
94
-
err = cqhci_crypto_program_key(cq_host, &cfg, slot);
102
+
cqhci_crypto_program_key(cq_host, &cfg, slot);
95
103
96
104
memzero_explicit(&cfg, sizeof(cfg));
97
-
return err;
105
+
return 0;
98
106
}
99
107
100
108
static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
···
105
113
*/
106
114
union cqhci_crypto_cfg_entry cfg = {};
107
115
108
-
return cqhci_crypto_program_key(cq_host, &cfg, slot);
116
+
cqhci_crypto_program_key(cq_host, &cfg, slot);
117
+
return 0;
109
118
}
110
119
111
120
static int cqhci_crypto_keyslot_evict(struct blk_crypto_profile *profile,
···
163
170
struct mmc_host *mmc = cq_host->mmc;
164
171
struct device *dev = mmc_dev(mmc);
165
172
struct blk_crypto_profile *profile = &mmc->crypto_profile;
166
-
unsigned int num_keyslots;
167
173
unsigned int cap_idx;
168
174
enum blk_crypto_mode_num blk_mode_num;
169
175
unsigned int slot;
···
171
179
if (!(mmc->caps2 & MMC_CAP2_CRYPTO) ||
172
180
!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
173
181
goto out;
182
+
183
+
if (cq_host->ops->uses_custom_crypto_profile)
184
+
goto profile_initialized;
174
185
175
186
cq_host->crypto_capabilities.reg_val =
176
187
cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
···
193
198
* CCAP.CFGC is off by one, so the actual number of crypto
194
199
* configurations (a.k.a. keyslots) is CCAP.CFGC + 1.
195
200
*/
196
-
num_keyslots = cq_host->crypto_capabilities.config_count + 1;
197
-
198
-
err = devm_blk_crypto_profile_init(dev, profile, num_keyslots);
201
+
err = devm_blk_crypto_profile_init(
202
+
dev, profile, cq_host->crypto_capabilities.config_count + 1);
199
203
if (err)
200
204
goto out;
201
205
···
222
228
cq_host->crypto_cap_array[cap_idx].sdus_mask * 512;
223
229
}
224
230
231
+
profile_initialized:
232
+
225
233
/* Clear all the keyslots so that we start in a known state. */
226
-
for (slot = 0; slot < num_keyslots; slot++)
227
-
cqhci_crypto_clear_keyslot(cq_host, slot);
234
+
for (slot = 0; slot < profile->num_slots; slot++)
235
+
profile->ll_ops.keyslot_evict(profile, NULL, slot);
228
236
229
237
/* CQHCI crypto requires the use of 128-bit task descriptors. */
230
238
cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
+3
-5
drivers/mmc/host/cqhci.h
+3
-5
drivers/mmc/host/cqhci.h
···
289
289
u64 *data);
290
290
void (*pre_enable)(struct mmc_host *mmc);
291
291
void (*post_disable)(struct mmc_host *mmc);
292
-
#ifdef CONFIG_MMC_CRYPTO
293
-
int (*program_key)(struct cqhci_host *cq_host,
294
-
const union cqhci_crypto_cfg_entry *cfg, int slot);
295
-
#endif
296
292
void (*set_tran_desc)(struct cqhci_host *cq_host, u8 **desc,
297
293
dma_addr_t addr, int len, bool end, bool dma64);
298
-
294
+
#ifdef CONFIG_MMC_CRYPTO
295
+
bool uses_custom_crypto_profile;
296
+
#endif
299
297
};
300
298
301
299
static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
+2
-6
drivers/mmc/host/dw_mmc-hi3798mv200.c
+2
-6
drivers/mmc/host/dw_mmc-hi3798mv200.c
···
181
181
{
182
182
struct dw_mci_hi3798mv200_priv *priv;
183
183
struct device_node *np = host->dev->of_node;
184
-
int ret;
185
184
186
185
priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
187
186
if (!priv)
···
198
199
return dev_err_probe(host->dev, PTR_ERR(priv->drive_clk),
199
200
"failed to get enabled ciu-drive clock\n");
200
201
201
-
priv->crg_reg = syscon_regmap_lookup_by_phandle(np, "hisilicon,sap-dll-reg");
202
+
priv->crg_reg = syscon_regmap_lookup_by_phandle_args(np, "hisilicon,sap-dll-reg",
203
+
1, &priv->sap_dll_offset);
202
204
if (IS_ERR(priv->crg_reg))
203
205
return dev_err_probe(host->dev, PTR_ERR(priv->crg_reg),
204
206
"failed to get CRG reg\n");
205
-
206
-
ret = of_property_read_u32_index(np, "hisilicon,sap-dll-reg", 1, &priv->sap_dll_offset);
207
-
if (ret)
208
-
return dev_err_probe(host->dev, ret, "failed to get sample DLL register offset\n");
209
207
210
208
host->priv = priv;
211
209
return 0;
+15
-6
drivers/mmc/host/mtk-sd.c
+15
-6
drivers/mmc/host/mtk-sd.c
···
414
414
u8 clk_div_bits;
415
415
bool recheck_sdio_irq;
416
416
bool hs400_tune; /* only used for MT8173 */
417
+
bool needs_top_base;
417
418
u32 pad_tune_reg;
418
419
bool async_fifo;
419
420
bool data_tune;
···
588
587
.clk_div_bits = 12,
589
588
.recheck_sdio_irq = true,
590
589
.hs400_tune = false,
590
+
.needs_top_base = true,
591
591
.pad_tune_reg = MSDC_PAD_TUNE0,
592
592
.async_fifo = true,
593
593
.data_tune = true,
···
629
627
.clk_div_bits = 12,
630
628
.recheck_sdio_irq = false,
631
629
.hs400_tune = false,
630
+
.needs_top_base = true,
632
631
.pad_tune_reg = MSDC_PAD_TUNE0,
633
632
.async_fifo = true,
634
633
.data_tune = true,
···
656
653
.clk_div_bits = 12,
657
654
.recheck_sdio_irq = false,
658
655
.hs400_tune = false,
656
+
.needs_top_base = true,
659
657
.pad_tune_reg = MSDC_PAD_TUNE0,
660
658
.async_fifo = true,
661
659
.data_tune = true,
···
1101
1097
u32 resp;
1102
1098
1103
1099
switch (mmc_resp_type(cmd)) {
1104
-
/* Actually, R1, R5, R6, R7 are the same */
1100
+
/* Actually, R1, R5, R6, R7 are the same */
1105
1101
case MMC_RSP_R1:
1106
1102
resp = 0x1;
1107
1103
break;
1108
1104
case MMC_RSP_R1B:
1105
+
case MMC_RSP_R1B_NO_CRC:
1109
1106
resp = 0x7;
1110
1107
break;
1111
1108
case MMC_RSP_R2:
···
1356
1351
* CRC error.
1357
1352
*/
1358
1353
msdc_reset_hw(host);
1359
-
if (events & MSDC_INT_RSPCRCERR) {
1354
+
if (events & MSDC_INT_RSPCRCERR &&
1355
+
mmc_resp_type(cmd) != MMC_RSP_R1B_NO_CRC) {
1360
1356
cmd->error = -EILSEQ;
1361
1357
host->error |= REQ_CMD_EIO;
1362
1358
} else if (events & MSDC_INT_CMDTMO) {
···
2891
2885
if (IS_ERR(host->base))
2892
2886
return PTR_ERR(host->base);
2893
2887
2894
-
host->top_base = devm_platform_ioremap_resource(pdev, 1);
2895
-
if (IS_ERR(host->top_base))
2896
-
host->top_base = NULL;
2888
+
host->dev_comp = of_device_get_match_data(&pdev->dev);
2889
+
2890
+
if (host->dev_comp->needs_top_base) {
2891
+
host->top_base = devm_platform_ioremap_resource(pdev, 1);
2892
+
if (IS_ERR(host->top_base))
2893
+
return PTR_ERR(host->top_base);
2894
+
}
2897
2895
2898
2896
ret = mmc_regulator_get_supply(mmc);
2899
2897
if (ret)
···
2959
2949
msdc_of_property_parse(pdev, host);
2960
2950
2961
2951
host->dev = &pdev->dev;
2962
-
host->dev_comp = of_device_get_match_data(&pdev->dev);
2963
2952
host->src_clk_freq = clk_get_rate(host->src_clk);
2964
2953
/* Set host parameters to mmc */
2965
2954
mmc->ops = &mt_msdc_ops;
+4
-4
drivers/mmc/host/mxcmmc.c
+4
-4
drivers/mmc/host/mxcmmc.c
···
995
995
struct mxcmci_host *host;
996
996
struct resource *res;
997
997
int ret = 0, irq;
998
-
bool dat3_card_detect = false;
998
+
bool dat3_card_detect;
999
999
dma_cap_mask_t mask;
1000
1000
struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
1001
1001
···
1048
1048
1049
1049
if (pdata)
1050
1050
dat3_card_detect = pdata->dat3_card_detect;
1051
-
else if (mmc_card_is_removable(mmc)
1052
-
&& !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1053
-
dat3_card_detect = true;
1051
+
else
1052
+
dat3_card_detect = mmc_card_is_removable(mmc) &&
1053
+
!of_property_present(pdev->dev.of_node, "cd-gpios");
1054
1054
1055
1055
ret = mmc_regulator_get_supply(mmc);
1056
1056
if (ret)
-2
drivers/mmc/host/rtsx_pci_sdmmc.c
-2
drivers/mmc/host/rtsx_pci_sdmmc.c
-3
drivers/mmc/host/rtsx_usb_sdmmc.c
-3
drivers/mmc/host/rtsx_usb_sdmmc.c
+3
-17
drivers/mmc/host/sdhci-acpi.c
+3
-17
drivers/mmc/host/sdhci-acpi.c
···
822
822
struct acpi_device *device;
823
823
struct sdhci_acpi_host *c;
824
824
struct sdhci_host *host;
825
-
struct resource *iomem;
826
-
resource_size_t len;
827
825
size_t priv_size;
828
826
int quirks = 0;
829
827
int err;
···
841
843
842
844
if (sdhci_acpi_byt_defer(dev))
843
845
return -EPROBE_DEFER;
844
-
845
-
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
846
-
if (!iomem)
847
-
return -ENOMEM;
848
-
849
-
len = resource_size(iomem);
850
-
if (len < 0x100)
851
-
dev_err(dev, "Invalid iomem size!\n");
852
-
853
-
if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
854
-
return -ENOMEM;
855
846
856
847
priv_size = slot ? slot->priv_size : 0;
857
848
host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
···
863
876
goto err_free;
864
877
}
865
878
866
-
host->ioaddr = devm_ioremap(dev, iomem->start,
867
-
resource_size(iomem));
868
-
if (host->ioaddr == NULL) {
869
-
err = -ENOMEM;
879
+
host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
880
+
if (IS_ERR(host->ioaddr)) {
881
+
err = PTR_ERR(host->ioaddr);
870
882
goto err_free;
871
883
}
872
884
+2
-1
drivers/mmc/host/sdhci-esdhc-imx.c
+2
-1
drivers/mmc/host/sdhci-esdhc-imx.c
···
304
304
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
305
305
| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
306
306
| ESDHC_FLAG_SKIP_ERR004536 | ESDHC_FLAG_SKIP_CD_WAKE,
307
+
.quirks = SDHCI_QUIRK_NO_LED,
307
308
};
308
309
309
310
static struct esdhc_soc_data usdhc_imx7ulp_data = {
···
1648
1647
* Retrieving and requesting the actual WP GPIO will happen
1649
1648
* in the call to mmc_of_parse().
1650
1649
*/
1651
-
if (of_property_read_bool(np, "wp-gpios"))
1650
+
if (of_property_present(np, "wp-gpios"))
1652
1651
boarddata->wp_type = ESDHC_WP_GPIO;
1653
1652
1654
1653
of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
+126
-21
drivers/mmc/host/sdhci-msm.c
+126
-21
drivers/mmc/host/sdhci-msm.c
···
134
134
/* Timeout value to avoid infinite waiting for pwr_irq */
135
135
#define MSM_PWR_IRQ_TIMEOUT_MS 5000
136
136
137
+
/* Max load for eMMC Vdd supply */
138
+
#define MMC_VMMC_MAX_LOAD_UA 570000
139
+
137
140
/* Max load for eMMC Vdd-io supply */
138
141
#define MMC_VQMMC_MAX_LOAD_UA 325000
142
+
143
+
/* Max load for SD Vdd supply */
144
+
#define SD_VMMC_MAX_LOAD_UA 800000
145
+
146
+
/* Max load for SD Vdd-io supply */
147
+
#define SD_VQMMC_MAX_LOAD_UA 22000
139
148
140
149
#define msm_host_readl(msm_host, host, offset) \
141
150
msm_host->var_ops->msm_readl_relaxed(host, offset)
···
1412
1403
return ret;
1413
1404
}
1414
1405
1415
-
static int sdhci_msm_set_vmmc(struct mmc_host *mmc)
1406
+
static void msm_config_vmmc_regulator(struct mmc_host *mmc, bool hpm)
1407
+
{
1408
+
int load;
1409
+
1410
+
if (!hpm)
1411
+
load = 0;
1412
+
else if (!mmc->card)
1413
+
load = max(MMC_VMMC_MAX_LOAD_UA, SD_VMMC_MAX_LOAD_UA);
1414
+
else if (mmc_card_mmc(mmc->card))
1415
+
load = MMC_VMMC_MAX_LOAD_UA;
1416
+
else if (mmc_card_sd(mmc->card))
1417
+
load = SD_VMMC_MAX_LOAD_UA;
1418
+
else
1419
+
return;
1420
+
1421
+
regulator_set_load(mmc->supply.vmmc, load);
1422
+
}
1423
+
1424
+
static void msm_config_vqmmc_regulator(struct mmc_host *mmc, bool hpm)
1425
+
{
1426
+
int load;
1427
+
1428
+
if (!hpm)
1429
+
load = 0;
1430
+
else if (!mmc->card)
1431
+
load = max(MMC_VQMMC_MAX_LOAD_UA, SD_VQMMC_MAX_LOAD_UA);
1432
+
else if (mmc_card_sd(mmc->card))
1433
+
load = SD_VQMMC_MAX_LOAD_UA;
1434
+
else
1435
+
return;
1436
+
1437
+
regulator_set_load(mmc->supply.vqmmc, load);
1438
+
}
1439
+
1440
+
static int sdhci_msm_set_vmmc(struct sdhci_msm_host *msm_host,
1441
+
struct mmc_host *mmc, bool hpm)
1416
1442
{
1417
1443
if (IS_ERR(mmc->supply.vmmc))
1418
1444
return 0;
1445
+
1446
+
msm_config_vmmc_regulator(mmc, hpm);
1419
1447
1420
1448
return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);
1421
1449
}
···
1465
1419
1466
1420
if (msm_host->vqmmc_enabled == level)
1467
1421
return 0;
1422
+
1423
+
msm_config_vqmmc_regulator(mmc, level);
1468
1424
1469
1425
if (level) {
1470
1426
/* Set the IO voltage regulator to default voltage level */
···
1690
1642
}
1691
1643
1692
1644
if (pwr_state) {
1693
-
ret = sdhci_msm_set_vmmc(mmc);
1645
+
ret = sdhci_msm_set_vmmc(msm_host, mmc,
1646
+
pwr_state & REQ_BUS_ON);
1694
1647
if (!ret)
1695
1648
ret = sdhci_msm_set_vqmmc(msm_host, mmc,
1696
1649
pwr_state & REQ_BUS_ON);
···
1856
1807
1857
1808
#ifdef CONFIG_MMC_CRYPTO
1858
1809
1810
+
static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */
1811
+
1859
1812
static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1860
1813
struct cqhci_host *cq_host)
1861
1814
{
1862
1815
struct mmc_host *mmc = msm_host->mmc;
1816
+
struct blk_crypto_profile *profile = &mmc->crypto_profile;
1863
1817
struct device *dev = mmc_dev(mmc);
1864
1818
struct qcom_ice *ice;
1819
+
union cqhci_crypto_capabilities caps;
1820
+
union cqhci_crypto_cap_entry cap;
1821
+
int err;
1822
+
int i;
1865
1823
1866
1824
if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
1867
1825
return 0;
···
1883
1827
return PTR_ERR_OR_ZERO(ice);
1884
1828
1885
1829
msm_host->ice = ice;
1886
-
mmc->caps2 |= MMC_CAP2_CRYPTO;
1887
1830
1831
+
/* Initialize the blk_crypto_profile */
1832
+
1833
+
caps.reg_val = cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
1834
+
1835
+
/* The number of keyslots supported is (CFGC+1) */
1836
+
err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1);
1837
+
if (err)
1838
+
return err;
1839
+
1840
+
profile->ll_ops = sdhci_msm_crypto_ops;
1841
+
profile->max_dun_bytes_supported = 4;
1842
+
profile->dev = dev;
1843
+
1844
+
/*
1845
+
* Currently this driver only supports AES-256-XTS. All known versions
1846
+
* of ICE support it, but to be safe make sure it is really declared in
1847
+
* the crypto capability registers. The crypto capability registers
1848
+
* also give the supported data unit size(s).
1849
+
*/
1850
+
for (i = 0; i < caps.num_crypto_cap; i++) {
1851
+
cap.reg_val = cpu_to_le32(cqhci_readl(cq_host,
1852
+
CQHCI_CRYPTOCAP +
1853
+
i * sizeof(__le32)));
1854
+
if (cap.algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS &&
1855
+
cap.key_size == CQHCI_CRYPTO_KEY_SIZE_256)
1856
+
profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |=
1857
+
cap.sdus_mask * 512;
1858
+
}
1859
+
1860
+
mmc->caps2 |= MMC_CAP2_CRYPTO;
1888
1861
return 0;
1889
1862
}
1890
1863
···
1939
1854
return 0;
1940
1855
}
1941
1856
1942
-
/*
1943
-
* Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires
1944
-
* vendor-specific SCM calls for this; it doesn't support the standard way.
1945
-
*/
1946
-
static int sdhci_msm_program_key(struct cqhci_host *cq_host,
1947
-
const union cqhci_crypto_cfg_entry *cfg,
1948
-
int slot)
1857
+
static inline struct sdhci_msm_host *
1858
+
sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile *profile)
1949
1859
{
1950
-
struct sdhci_host *host = mmc_priv(cq_host->mmc);
1860
+
struct mmc_host *mmc = mmc_from_crypto_profile(profile);
1861
+
struct sdhci_host *host = mmc_priv(mmc);
1951
1862
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1952
1863
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1953
-
union cqhci_crypto_cap_entry cap;
1954
1864
1955
-
if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE))
1956
-
return qcom_ice_evict_key(msm_host->ice, slot);
1865
+
return msm_host;
1866
+
}
1867
+
1868
+
/*
1869
+
* Program a key into a QC ICE keyslot. QC ICE requires a QC-specific SCM call
1870
+
* for this; it doesn't support the standard way.
1871
+
*/
1872
+
static int sdhci_msm_ice_keyslot_program(struct blk_crypto_profile *profile,
1873
+
const struct blk_crypto_key *key,
1874
+
unsigned int slot)
1875
+
{
1876
+
struct sdhci_msm_host *msm_host =
1877
+
sdhci_msm_host_from_crypto_profile(profile);
1957
1878
1958
1879
/* Only AES-256-XTS has been tested so far. */
1959
-
cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
1960
-
if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
1961
-
cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256)
1962
-
return -EINVAL;
1880
+
if (key->crypto_cfg.crypto_mode != BLK_ENCRYPTION_MODE_AES_256_XTS)
1881
+
return -EOPNOTSUPP;
1963
1882
1964
1883
return qcom_ice_program_key(msm_host->ice,
1965
1884
QCOM_ICE_CRYPTO_ALG_AES_XTS,
1966
1885
QCOM_ICE_CRYPTO_KEY_SIZE_256,
1967
-
cfg->crypto_key,
1968
-
cfg->data_unit_size, slot);
1886
+
key->raw,
1887
+
key->crypto_cfg.data_unit_size / 512,
1888
+
slot);
1969
1889
}
1890
+
1891
+
static int sdhci_msm_ice_keyslot_evict(struct blk_crypto_profile *profile,
1892
+
const struct blk_crypto_key *key,
1893
+
unsigned int slot)
1894
+
{
1895
+
struct sdhci_msm_host *msm_host =
1896
+
sdhci_msm_host_from_crypto_profile(profile);
1897
+
1898
+
return qcom_ice_evict_key(msm_host->ice, slot);
1899
+
}
1900
+
1901
+
static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops = {
1902
+
.keyslot_program = sdhci_msm_ice_keyslot_program,
1903
+
.keyslot_evict = sdhci_msm_ice_keyslot_evict,
1904
+
};
1970
1905
1971
1906
#else /* CONFIG_MMC_CRYPTO */
1972
1907
···
2093
1988
.enable = sdhci_msm_cqe_enable,
2094
1989
.disable = sdhci_msm_cqe_disable,
2095
1990
#ifdef CONFIG_MMC_CRYPTO
2096
-
.program_key = sdhci_msm_program_key,
1991
+
.uses_custom_crypto_profile = true,
2097
1992
#endif
2098
1993
};
2099
1994
-1
drivers/mmc/host/tmio_mmc_core.c
-1
drivers/mmc/host/tmio_mmc_core.c
+1
-3
include/linux/mmc/core.h
+1
-3
include/linux/mmc/core.h
···
57
57
#define MMC_RSP_NONE (0)
58
58
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
59
59
#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
60
+
#define MMC_RSP_R1B_NO_CRC (MMC_RSP_PRESENT|MMC_RSP_OPCODE|MMC_RSP_BUSY)
60
61
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
61
62
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
62
63
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
63
64
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
64
65
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
65
66
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
66
-
67
-
/* Can be used by core to poll after switch to MMC HS mode */
68
-
#define MMC_RSP_R1_NO_CRC (MMC_RSP_PRESENT|MMC_RSP_OPCODE)
69
67
70
68
#define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE))
71
69
+8
include/linux/mmc/host.h
+8
include/linux/mmc/host.h
···
590
590
return container_of(priv, struct mmc_host, private);
591
591
}
592
592
593
+
#ifdef CONFIG_MMC_CRYPTO
594
+
static inline struct mmc_host *
595
+
mmc_from_crypto_profile(struct blk_crypto_profile *profile)
596
+
{
597
+
return container_of(profile, struct mmc_host, crypto_profile);
598
+
}
599
+
#endif
600
+
593
601
#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI)
594
602
595
603
#define mmc_dev(x) ((x)->parent)