Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpio: mt7621: use the generic GPIO chip lock for IRQ handling
This driver uses its own spinlock in interrupt routines while the
generic GPIO chip callbacks use a separate one. This is, of course, racy
so use the fact that the lock in generic GPIO chip is also a spinlock and
convert the interrupt handling functions in this module to using the
provided generic GPIO chip locking API.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250910-gpio-mmio-gpio-conv-part4-v2-9-f3d1a4c57124@linaro.org
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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drivers/gpio/gpio-mt7621.c
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drivers/gpio/gpio-mt7621.c
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define MTK_BANK_CNT 3
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#define MTK_BANK_WIDTH 32
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struct mtk_gc {
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struct irq_chip irq_chip;
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struct gpio_generic_chip chip;
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spinlock_t lock;
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int bank;
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u32 rising;
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u32 falling;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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int pin = d->hwirq;
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unsigned long flags;
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u32 rise, fall, high, low;
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gpiochip_enable_irq(gc, d->hwirq);
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spin_lock_irqsave(&rg->lock, flags);
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guard(gpio_generic_lock_irqsave)(&rg->chip);
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rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
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fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
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high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
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mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
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mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
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mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
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spin_unlock_irqrestore(&rg->lock, flags);
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}
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static void
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct mtk_gc *rg = to_mediatek_gpio(gc);
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int pin = d->hwirq;
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unsigned long flags;
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u32 rise, fall, high, low;
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spin_lock_irqsave(&rg->lock, flags);
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rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
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fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
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high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
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low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
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mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
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spin_unlock_irqrestore(&rg->lock, flags);
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scoped_guard(gpio_generic_lock_irqsave, &rg->chip) {
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rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
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fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
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high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
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low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
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mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
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}
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gpiochip_disable_irq(gc, d->hwirq);
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}
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rg = &mtk->gc_map[bank];
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memset(rg, 0, sizeof(*rg));
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spin_lock_init(&rg->lock);
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rg->bank = bank;
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dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);