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phy: cadence: cdns-dphy: Update calibration wait time for startup state machine

Do read-modify-write so that we re-use the characterized reset value as
specified in TRM [1] to program calibration wait time which defines number
of cycles to wait for after startup state machine is in bandgap enable
state.

This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's
AM62L and J721E SoC since earlier calibration wait time was getting
overwritten to zero value thus failing the PLL to lockup and causing
timeout.

[1] AM62P TRM (Section 14.8.6.3.2.1.1 DPHY_TX_DPHYTX_CMN0_CMN_DIG_TBIT2):
Link: https://www.ti.com/lit/pdf/spruj83

Cc: stable@vger.kernel.org
Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support")
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Tested-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://lore.kernel.org/r/20250704125915.1224738-3-devarsht@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Devarsh Thakkar and committed by
Vinod Koul 2c27aaee 284fb19a

+3 -1
+3 -1
drivers/phy/cadence/cdns-dphy.c
··· 30 30 31 31 #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) 32 32 #define DPHY_CMN_SSM_EN BIT(0) 33 + #define DPHY_CMN_SSM_CAL_WAIT_TIME GENMASK(8, 1) 33 34 #define DPHY_CMN_TX_MODE_EN BIT(9) 34 35 35 36 #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) ··· 411 410 writel(reg, dphy->regs + DPHY_BAND_CFG); 412 411 413 412 /* Start TX state machine. */ 414 - writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN, 413 + reg = readl(dphy->regs + DPHY_CMN_SSM); 414 + writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN, 415 415 dphy->regs + DPHY_CMN_SSM); 416 416 417 417 ret = cdns_dphy_wait_for_pll_lock(dphy);