Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add function to fill fw reserve region
Add a function to fill in details for firmware reserve region.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Lijo Lazar
and committed by
Alex Deucher
2c7b0e37
5dad4394
+41
-29
+41
-29
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+41
-29
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
···
1687
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resv->needs_cpu_map = needs_cpu_map;
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}
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+
static void amdgpu_ttm_init_fw_resv_region(struct amdgpu_device *adev)
1691
+
{
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+
uint32_t reserve_size = 0;
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+
1694
+
if (!adev->discovery.reserve_tmr)
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+
return;
1696
+
1697
+
/*
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* Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
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+
* the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
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+
*
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* Otherwise, fallback to legacy approach to check and reserve tmr block for ip
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+
* discovery data and G6 memory training data respectively
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+
*/
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+
if (adev->bios)
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+
reserve_size =
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amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
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+
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+
if (!adev->bios &&
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(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
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+
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
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amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)))
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reserve_size = max(reserve_size, (uint32_t)280 << 20);
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+
else if (!adev->bios &&
1714
+
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) {
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+
if (hweight32(adev->aid_mask) == 1)
1716
+
reserve_size = max(reserve_size, (uint32_t)128 << 20);
1717
+
else
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+
reserve_size = max(reserve_size, (uint32_t)144 << 20);
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+
} else if (!reserve_size)
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+
reserve_size = DISCOVERY_TMR_OFFSET;
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+
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+
amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW,
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adev->gmc.real_vram_size - reserve_size,
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+
reserve_size, false);
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+
}
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+
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static void amdgpu_ttm_init_vram_resv_regions(struct amdgpu_device *adev)
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{
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/* Initialize memory reservations as required for VGA.
···
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* and driver.
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*/
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amdgpu_gmc_init_vga_resv_regions(adev);
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+
amdgpu_ttm_init_fw_resv_region(adev);
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}
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int amdgpu_ttm_mark_vram_reserved(struct amdgpu_device *adev,
···
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{
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struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
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bool mem_train_support = false;
1829
-
uint32_t reserve_size = 0;
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+
uint32_t reserve_size;
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int ret;
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+
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reserve_size = adev->mman.resv_region[AMDGPU_RESV_FW].size;
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if (adev->bios && !amdgpu_sriov_vf(adev)) {
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if (amdgpu_atomfirmware_mem_training_supported(adev))
···
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else
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DRM_DEBUG("memory training does not support!\n");
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}
1840
-
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-
/*
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* Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
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-
* the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
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-
*
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-
* Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1846
-
* discovery data and G6 memory training data respectively
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-
*/
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if (adev->bios)
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-
reserve_size =
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amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
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-
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if (!adev->bios &&
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(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
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amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
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amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)))
1856
-
reserve_size = max(reserve_size, (uint32_t)280 << 20);
1857
-
else if (!adev->bios &&
1858
-
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) {
1859
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if (hweight32(adev->aid_mask) == 1)
1860
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reserve_size = max(reserve_size, (uint32_t)128 << 20);
1861
-
else
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-
reserve_size = max(reserve_size, (uint32_t)144 << 20);
1863
-
} else if (!reserve_size)
1864
-
reserve_size = DISCOVERY_TMR_OFFSET;
1865
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if (mem_train_support) {
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/* reserve vram for mem train according to TMR location */
···
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ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
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}
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-
amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW,
1856
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adev->gmc.real_vram_size - reserve_size,
1857
-
reserve_size, false);
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ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW);
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if (ret) {
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dev_err(adev->dev, "alloc tmr failed(%d)!\n", ret);