Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto fixes from Herbert Xu:
"This fixes the following issues:
API:
- algif_hash needs to wait for init operations to complete.
- The has_key setting for shash was always true.
Algorithms:
- Add missing selections of CRYPTO_HASH.
- Fix pkcs7 authentication.
Drivers:
- Fix stack alignment bug in chacha20-ssse3.
- Fix performance regression in caam due to incorrect setting.
- Fix potential compile-only build failure of stm32"
* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
crypto: atmel-aes - remove calls of clk_prepare() from atomic contexts
crypto: algif_hash - wait for crypto_ahash_init() to complete
crypto: shash - Fix has_key setting
hwrng: stm32 - Fix dependencies for !HAS_IOMEM archs
crypto: ghash,poly1305 - select CRYPTO_HASH where needed
crypto: chacha20-ssse3 - Align stack pointer to 64 bytes
PKCS#7: Don't require SpcSpOpusInfo in Authenticode pkcs7 signatures
crypto: caam - make write transactions bufferable on PPC platforms
+28
-16
+4
-2
arch/x86/crypto/chacha20-ssse3-x86_64.S
+4
-2
arch/x86/crypto/chacha20-ssse3-x86_64.S
···
157
157
# done with the slightly better performing SSSE3 byte shuffling,
158
158
# 7/12-bit word rotation uses traditional shift+OR.
159
159
160
-
sub $0x40,%rsp
160
+
mov %rsp,%r11
161
+
sub $0x80,%rsp
162
+
and $~63,%rsp
161
163
162
164
# x0..15[0-3] = s0..3[0..3]
163
165
movq 0x00(%rdi),%xmm1
···
622
620
pxor %xmm1,%xmm15
623
621
movdqu %xmm15,0xf0(%rsi)
624
622
625
-
add $0x40,%rsp
623
+
mov %r11,%rsp
626
624
ret
627
625
ENDPROC(chacha20_4block_xor_ssse3)
+2
crypto/Kconfig
+2
crypto/Kconfig
···
472
472
config CRYPTO_GHASH
473
473
tristate "GHASH digest algorithm"
474
474
select CRYPTO_GF128MUL
475
+
select CRYPTO_HASH
475
476
help
476
477
GHASH is message digest algorithm for GCM (Galois/Counter Mode).
477
478
478
479
config CRYPTO_POLY1305
479
480
tristate "Poly1305 authenticator algorithm"
481
+
select CRYPTO_HASH
480
482
help
481
483
Poly1305 authenticator algorithm, RFC7539.
482
484
+3
-1
crypto/algif_hash.c
+3
-1
crypto/algif_hash.c
···
54
54
55
55
lock_sock(sk);
56
56
if (!ctx->more) {
57
-
err = crypto_ahash_init(&ctx->req);
57
+
err = af_alg_wait_for_completion(crypto_ahash_init(&ctx->req),
58
+
&ctx->completion);
58
59
if (err)
59
60
goto unlock;
60
61
}
···
126
125
} else {
127
126
if (!ctx->more) {
128
127
err = crypto_ahash_init(&ctx->req);
128
+
err = af_alg_wait_for_completion(err, &ctx->completion);
129
129
if (err)
130
130
goto unlock;
131
131
}
+1
-3
crypto/asymmetric_keys/pkcs7_parser.c
+1
-3
crypto/asymmetric_keys/pkcs7_parser.c
···
547
547
struct pkcs7_signed_info *sinfo = ctx->sinfo;
548
548
549
549
if (!test_bit(sinfo_has_content_type, &sinfo->aa_set) ||
550
-
!test_bit(sinfo_has_message_digest, &sinfo->aa_set) ||
551
-
(ctx->msg->data_type == OID_msIndirectData &&
552
-
!test_bit(sinfo_has_ms_opus_info, &sinfo->aa_set))) {
550
+
!test_bit(sinfo_has_message_digest, &sinfo->aa_set)) {
553
551
pr_warn("Missing required AuthAttr\n");
554
552
return -EBADMSG;
555
553
}
+3
-4
crypto/shash.c
+3
-4
crypto/shash.c
···
354
354
crt->final = shash_async_final;
355
355
crt->finup = shash_async_finup;
356
356
crt->digest = shash_async_digest;
357
+
crt->setkey = shash_async_setkey;
357
358
358
-
if (alg->setkey) {
359
-
crt->setkey = shash_async_setkey;
360
-
crt->has_setkey = true;
361
-
}
359
+
crt->has_setkey = alg->setkey != shash_no_setkey;
360
+
362
361
if (alg->export)
363
362
crt->export = shash_async_export;
364
363
if (alg->import)
+1
drivers/char/hw_random/Kconfig
+1
drivers/char/hw_random/Kconfig
···
372
372
config HW_RANDOM_STM32
373
373
tristate "STMicroelectronics STM32 random number generator"
374
374
depends on HW_RANDOM && (ARCH_STM32 || COMPILE_TEST)
375
+
depends on HAS_IOMEM
375
376
help
376
377
This driver provides kernel-side support for the Random Number
377
378
Generator hardware found on STM32 microcontrollers.
+12
-4
drivers/crypto/atmel-aes.c
+12
-4
drivers/crypto/atmel-aes.c
···
400
400
{
401
401
int err;
402
402
403
-
err = clk_prepare_enable(dd->iclk);
403
+
err = clk_enable(dd->iclk);
404
404
if (err)
405
405
return err;
406
406
···
430
430
431
431
dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
432
432
433
-
clk_disable_unprepare(dd->iclk);
433
+
clk_disable(dd->iclk);
434
434
return 0;
435
435
}
436
436
···
448
448
449
449
static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
450
450
{
451
-
clk_disable_unprepare(dd->iclk);
451
+
clk_disable(dd->iclk);
452
452
dd->flags &= ~AES_FLAGS_BUSY;
453
453
454
454
if (dd->is_async)
···
2091
2091
goto res_err;
2092
2092
}
2093
2093
2094
-
err = atmel_aes_hw_version_init(aes_dd);
2094
+
err = clk_prepare(aes_dd->iclk);
2095
2095
if (err)
2096
2096
goto res_err;
2097
+
2098
+
err = atmel_aes_hw_version_init(aes_dd);
2099
+
if (err)
2100
+
goto iclk_unprepare;
2097
2101
2098
2102
atmel_aes_get_cap(aes_dd);
2099
2103
···
2131
2127
err_aes_dma:
2132
2128
atmel_aes_buff_cleanup(aes_dd);
2133
2129
err_aes_buff:
2130
+
iclk_unprepare:
2131
+
clk_unprepare(aes_dd->iclk);
2134
2132
res_err:
2135
2133
tasklet_kill(&aes_dd->done_task);
2136
2134
tasklet_kill(&aes_dd->queue_task);
···
2160
2154
2161
2155
atmel_aes_dma_cleanup(aes_dd);
2162
2156
atmel_aes_buff_cleanup(aes_dd);
2157
+
2158
+
clk_unprepare(aes_dd->iclk);
2163
2159
2164
2160
return 0;
2165
2161
}
+2
-2
drivers/crypto/caam/ctrl.c
+2
-2
drivers/crypto/caam/ctrl.c
···
534
534
* long pointers in master configuration register
535
535
*/
536
536
clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
537
-
MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
538
-
MCFGR_LONG_PTR : 0));
537
+
MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE |
538
+
(sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
539
539
540
540
/*
541
541
* Read the Compile Time paramters and SCFGR to determine