tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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arm64: Provide dcache_by_myline_op_nosync helper

dcache_by_myline_op ensures completion of the data cache operations for a
region, while dcache_by_myline_op_nosync only issues them without waiting.
This enables deferred synchronization so completion for multiple regions
can be handled together later.

Cc: Leon Romanovsky <leon@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Ryan Roberts <ryan.roberts@arm.com>
Cc: Suren Baghdasaryan <surenb@google.com>
Cc: Tangquan Zheng <zhengtangquan@oppo.com>
Tested-by: Xueyuan Chen <xueyuan.chen21@gmail.com>
Signed-off-by: Barry Song <baohua@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20260228221216.59886-1-21cnbao@gmail.com

authored by

Barry Song and committed by
Marek Szyprowski 2c92eff0 a54302cc

+21 -7
+19 -6
arch/arm64/include/asm/assembler.h
··· 371 371 * [start, end) with dcache line size explicitly provided. 372 372 * 373 373 * op: operation passed to dc instruction 374 - * domain: domain used in dsb instruction 375 374 * start: starting virtual address of the region 376 375 * end: end virtual address of the region 377 376 * linesz: dcache line size 378 377 * fixup: optional label to branch to on user fault 379 378 * Corrupts: start, end, tmp 380 379 */ 381 - .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup 380 + .macro dcache_by_myline_op_nosync op, start, end, linesz, tmp, fixup 382 381 sub \tmp, \linesz, #1 383 382 bic \start, \start, \tmp 384 383 alternative_if ARM64_WORKAROUND_4311569 ··· 411 412 cbnz \start, .Ldcache_op\@ 412 413 .endif 413 414 alternative_else_nop_endif 414 - dsb \domain 415 415 416 416 _cond_uaccess_extable .Ldcache_op\@, \fixup 417 417 .endm 418 418 419 419 /* 420 420 * Macro to perform a data cache maintenance for the interval 421 - * [start, end) 421 + * [start, end) without waiting for completion 422 + * 423 + * op: operation passed to dc instruction 424 + * start: starting virtual address of the region 425 + * end: end virtual address of the region 426 + * fixup: optional label to branch to on user fault 427 + * Corrupts: start, end, tmp1, tmp2 428 + */ 429 + .macro dcache_by_line_op_nosync op, start, end, tmp1, tmp2, fixup 430 + dcache_line_size \tmp1, \tmp2 431 + dcache_by_myline_op_nosync \op, \start, \end, \tmp1, \tmp2, \fixup 432 + .endm 433 + 434 + /* 435 + * Macro to perform a data cache maintenance for the interval 436 + * [start, end) and wait for completion 422 437 * 423 438 * op: operation passed to dc instruction 424 439 * domain: domain used in dsb instruction ··· 442 429 * Corrupts: start, end, tmp1, tmp2 443 430 */ 444 431 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup 445 - dcache_line_size \tmp1, \tmp2 446 - dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup 432 + dcache_by_line_op_nosync \op, \start, \end, \tmp1, \tmp2, \fixup 433 + dsb \domain 447 434 .endm 448 435 449 436 /*
+2 -1
arch/arm64/kernel/relocate_kernel.S
··· 64 64 mov x19, x13 65 65 copy_page x13, x12, x1, x2, x3, x4, x5, x6, x7, x8 66 66 add x1, x19, #PAGE_SIZE 67 - dcache_by_myline_op civac, sy, x19, x1, x15, x20 67 + dcache_by_myline_op_nosync civac, x19, x1, x15, x20 68 + dsb sy 68 69 b .Lnext 69 70 .Ltest_indirection: 70 71 tbz x16, IND_INDIRECTION_BIT, .Ltest_destination