tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: add UMSCH 4.0 register headers

Add headers for UMSCH 4.0.

v2: updates (Alex)

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lang Yu and committed by
Alex Deucher 2c98de56 6be6e74b

+1304
+422
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h
··· 1305 1305 #define regVCN_RB3_DB_CTRL_BASE_IDX 1 1306 1306 #define regVCN_RB4_DB_CTRL 0x0075 1307 1307 #define regVCN_RB4_DB_CTRL_BASE_IDX 1 1308 + #define regVCN_UMSCH_RB_DB_CTRL 0x0076 1309 + #define regVCN_UMSCH_RB_DB_CTRL_BASE_IDX 1 1310 + #define regVCN_AGDB_CTRL0 0x0079 1311 + #define regVCN_AGDB_CTRL0_BASE_IDX 1 1312 + #define regVCN_AGDB_CTRL1 0x007a 1313 + #define regVCN_AGDB_CTRL1_BASE_IDX 1 1314 + #define regVCN_AGDB_CTRL2 0x007b 1315 + #define regVCN_AGDB_CTRL2_BASE_IDX 1 1316 + #define regVCN_AGDB_CTRL3 0x007c 1317 + #define regVCN_AGDB_CTRL3_BASE_IDX 1 1318 + #define regVCN_AGDB_CTRL4 0x007d 1319 + #define regVCN_AGDB_CTRL4_BASE_IDX 1 1320 + #define regVCN_AGDB_CTRL5 0x007e 1321 + #define regVCN_AGDB_CTRL5_BASE_IDX 1 1322 + #define regVCN_AGDB_MASK0 0x007f 1323 + #define regVCN_AGDB_MASK0_BASE_IDX 1 1324 + #define regVCN_AGDB_MASK1 0x0080 1325 + #define regVCN_AGDB_MASK1_BASE_IDX 1 1326 + #define regVCN_AGDB_MASK2 0x0081 1327 + #define regVCN_AGDB_MASK2_BASE_IDX 1 1328 + #define regVCN_AGDB_MASK3 0x0082 1329 + #define regVCN_AGDB_MASK3_BASE_IDX 1 1330 + #define regVCN_AGDB_MASK4 0x0083 1331 + #define regVCN_AGDB_MASK4_BASE_IDX 1 1332 + #define regVCN_AGDB_MASK5 0x0084 1333 + #define regVCN_AGDB_MASK5_BASE_IDX 1 1308 1334 #define regVCN_RB_ENABLE 0x0085 1309 1335 #define regVCN_RB_ENABLE_BASE_IDX 1 1310 1336 #define regVCN_RB_WPTR_CTRL 0x0086 ··· 1582 1556 #define regVCN_RAS_CNTL_MMSCH 0x0914 1583 1557 #define regVCN_RAS_CNTL_MMSCH_BASE_IDX 1 1584 1558 1559 + #define regVCN_UMSCH_MES_UTCL1_CNTL 0x0759 1560 + #define regVCN_UMSCH_MES_UTCL1_CNTL_BASE_IDX 1 1561 + #define regVCN_UMSCH_MES_BUSY 0x075a 1562 + #define regVCN_UMSCH_MES_BUSY_BASE_IDX 1 1563 + #define regVCN_UMSCH_RB_BASE_LO 0x075b 1564 + #define regVCN_UMSCH_RB_BASE_LO_BASE_IDX 1 1565 + #define regVCN_UMSCH_RB_BASE_HI 0x075c 1566 + #define regVCN_UMSCH_RB_BASE_HI_BASE_IDX 1 1567 + #define regVCN_UMSCH_RB_SIZE 0x075d 1568 + #define regVCN_UMSCH_RB_SIZE_BASE_IDX 1 1569 + #define regVCN_UMSCH_RB_RPTR 0x075e 1570 + #define regVCN_UMSCH_RB_RPTR_BASE_IDX 1 1571 + #define regVCN_UMSCH_RB_WPTR 0x075f 1572 + #define regVCN_UMSCH_RB_WPTR_BASE_IDX 1 1573 + #define regVCN_UMSCH_MASTINT_EN 0x0760 1574 + #define regVCN_UMSCH_MASTINT_EN_BASE_IDX 1 1575 + #define regVCN_UMSCH_IH_CTRL 0x0761 1576 + #define regVCN_UMSCH_IH_CTRL_BASE_IDX 1 1577 + #define regVCN_UMSCH_SYS_INT_EN 0x0762 1578 + #define regVCN_UMSCH_SYS_INT_EN_BASE_IDX 1 1579 + #define regVCN_UMSCH_SYS_INT_STATUS 0x0763 1580 + #define regVCN_UMSCH_SYS_INT_STATUS_BASE_IDX 1 1581 + #define regVCN_UMSCH_SYS_INT_ACK 0x0764 1582 + #define regVCN_UMSCH_SYS_INT_ACK_BASE_IDX 1 1583 + #define regVCN_UMSCH_SYS_INT_SRC 0x0765 1584 + #define regVCN_UMSCH_SYS_INT_SRC_BASE_IDX 1 1585 + #define regVCN_UMSCH_IH_CTX_CTRL 0x0766 1586 + #define regVCN_UMSCH_IH_CTX_CTRL_BASE_IDX 1 1587 + #define regVCN_UMSCH_CGC_CTRL 0x0767 1588 + #define regVCN_UMSCH_CGC_CTRL_BASE_IDX 1 1589 + #define regVCN_UMSCH_CGC_STATUS 0x0768 1590 + #define regVCN_UMSCH_CGC_STATUS_BASE_IDX 1 1591 + #define regVCN_UMSCH_CGC_MEM_CTRL 0x0769 1592 + #define regVCN_UMSCH_CGC_MEM_CTRL_BASE_IDX 1 1593 + #define regUVD_INTERNAL_REG_VIOLATION_8 0x076a 1594 + #define regUVD_INTERNAL_REG_VIOLATION_8_BASE_IDX 1 1595 + #define regUVD_UMSCH_FORCE 0x076b 1596 + #define regUVD_UMSCH_FORCE_BASE_IDX 1 1597 + #define regUVD_UMSCH_DEBUG_INDEX 0x076c 1598 + #define regUVD_UMSCH_DEBUG_INDEX_BASE_IDX 1 1599 + #define regUVD_UMSCH_DEBUG_DATA_LO 0x076d 1600 + #define regUVD_UMSCH_DEBUG_DATA_LO_BASE_IDX 1 1601 + #define regUVD_UMSCH_DEBUG_DATA_HI 0x076e 1602 + #define regUVD_UMSCH_DEBUG_DATA_HI_BASE_IDX 1 1603 + #define regUVD_UMSCH_DEBUG_UTCL2_TCIU_IF 0x076f 1604 + #define regUVD_UMSCH_DEBUG_UTCL2_TCIU_IF_BASE_IDX 1 1605 + #define regUMSCH_MES_RESET_CTRL 0x0770 1606 + #define regUMSCH_MES_RESET_CTRL_BASE_IDX 1 1607 + 1608 + #define regVCN_MES_PRGRM_CNTR_START 0x0780 1609 + #define regVCN_MES_PRGRM_CNTR_START_BASE_IDX 1 1610 + #define regVCN_MES_INTR_ROUTINE_START 0x0781 1611 + #define regVCN_MES_INTR_ROUTINE_START_BASE_IDX 1 1612 + #define regVCN_MES_MTVEC_LO 0x0781 1613 + #define regVCN_MES_MTVEC_LO_BASE_IDX 1 1614 + #define regVCN_MES_INTR_ROUTINE_START_HI 0x0782 1615 + #define regVCN_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 1616 + #define regVCN_MES_MTVEC_HI 0x0782 1617 + #define regVCN_MES_MTVEC_HI_BASE_IDX 1 1618 + #define regVCN_MES_CNTL 0x0787 1619 + #define regVCN_MES_CNTL_BASE_IDX 1 1620 + #define regVCN_MES_PIPE_PRIORITY_CNTS 0x0788 1621 + #define regVCN_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 1622 + #define regVCN_MES_PIPE0_PRIORITY 0x0789 1623 + #define regVCN_MES_PIPE0_PRIORITY_BASE_IDX 1 1624 + #define regVCN_MES_PIPE1_PRIORITY 0x078a 1625 + #define regVCN_MES_PIPE1_PRIORITY_BASE_IDX 1 1626 + #define regVCN_MES_PIPE2_PRIORITY 0x078b 1627 + #define regVCN_MES_PIPE2_PRIORITY_BASE_IDX 1 1628 + #define regVCN_MES_PIPE3_PRIORITY 0x078c 1629 + #define regVCN_MES_PIPE3_PRIORITY_BASE_IDX 1 1630 + #define regVCN_MES_HEADER_DUMP 0x078d 1631 + #define regVCN_MES_HEADER_DUMP_BASE_IDX 1 1632 + #define regVCN_MES_MIE_LO 0x078e 1633 + #define regVCN_MES_MIE_LO_BASE_IDX 1 1634 + #define regVCN_MES_MIE_HI 0x078f 1635 + #define regVCN_MES_MIE_HI_BASE_IDX 1 1636 + #define regVCN_MES_INTERRUPT 0x0790 1637 + #define regVCN_MES_INTERRUPT_BASE_IDX 1 1638 + #define regVCN_MES_SCRATCH_INDEX 0x0791 1639 + #define regVCN_MES_SCRATCH_INDEX_BASE_IDX 1 1640 + #define regVCN_MES_SCRATCH_DATA 0x0792 1641 + #define regVCN_MES_SCRATCH_DATA_BASE_IDX 1 1642 + #define regVCN_MES_INSTR_PNTR 0x0793 1643 + #define regVCN_MES_INSTR_PNTR_BASE_IDX 1 1644 + #define regVCN_MES_MSCRATCH_HI 0x0794 1645 + #define regVCN_MES_MSCRATCH_HI_BASE_IDX 1 1646 + #define regVCN_MES_MSCRATCH_LO 0x0795 1647 + #define regVCN_MES_MSCRATCH_LO_BASE_IDX 1 1648 + #define regVCN_MES_MSTATUS_LO 0x0796 1649 + #define regVCN_MES_MSTATUS_LO_BASE_IDX 1 1650 + #define regVCN_MES_MSTATUS_HI 0x0797 1651 + #define regVCN_MES_MSTATUS_HI_BASE_IDX 1 1652 + #define regVCN_MES_MEPC_LO 0x0798 1653 + #define regVCN_MES_MEPC_LO_BASE_IDX 1 1654 + #define regVCN_MES_MEPC_HI 0x0799 1655 + #define regVCN_MES_MEPC_HI_BASE_IDX 1 1656 + #define regVCN_MES_MCAUSE_LO 0x079a 1657 + #define regVCN_MES_MCAUSE_LO_BASE_IDX 1 1658 + #define regVCN_MES_MCAUSE_HI 0x079b 1659 + #define regVCN_MES_MCAUSE_HI_BASE_IDX 1 1660 + #define regVCN_MES_MBADADDR_LO 0x079c 1661 + #define regVCN_MES_MBADADDR_LO_BASE_IDX 1 1662 + #define regVCN_MES_MBADADDR_HI 0x079d 1663 + #define regVCN_MES_MBADADDR_HI_BASE_IDX 1 1664 + #define regVCN_MES_MIP_LO 0x079e 1665 + #define regVCN_MES_MIP_LO_BASE_IDX 1 1666 + #define regVCN_MES_MIP_HI 0x079f 1667 + #define regVCN_MES_MIP_HI_BASE_IDX 1 1668 + #define regVCN_MES_IC_OP_CNTL 0x07a0 1669 + #define regVCN_MES_IC_OP_CNTL_BASE_IDX 1 1670 + #define regVCN_MES_MCYCLE_LO 0x07a6 1671 + #define regVCN_MES_MCYCLE_LO_BASE_IDX 1 1672 + #define regVCN_MES_MCYCLE_HI 0x07a7 1673 + #define regVCN_MES_MCYCLE_HI_BASE_IDX 1 1674 + #define regVCN_MES_MTIME_LO 0x07a8 1675 + #define regVCN_MES_MTIME_LO_BASE_IDX 1 1676 + #define regVCN_MES_MTIME_HI 0x07a9 1677 + #define regVCN_MES_MTIME_HI_BASE_IDX 1 1678 + #define regVCN_MES_MINSTRET_LO 0x07aa 1679 + #define regVCN_MES_MINSTRET_LO_BASE_IDX 1 1680 + #define regVCN_MES_MINSTRET_HI 0x07ab 1681 + #define regVCN_MES_MINSTRET_HI_BASE_IDX 1 1682 + #define regVCN_MES_MISA_LO 0x07ac 1683 + #define regVCN_MES_MISA_LO_BASE_IDX 1 1684 + #define regVCN_MES_MISA_HI 0x07ad 1685 + #define regVCN_MES_MISA_HI_BASE_IDX 1 1686 + #define regVCN_MES_MVENDORID_LO 0x07ae 1687 + #define regVCN_MES_MVENDORID_LO_BASE_IDX 1 1688 + #define regVCN_MES_MVENDORID_HI 0x07af 1689 + #define regVCN_MES_MVENDORID_HI_BASE_IDX 1 1690 + #define regVCN_MES_MARCHID_LO 0x07b0 1691 + #define regVCN_MES_MARCHID_LO_BASE_IDX 1 1692 + #define regVCN_MES_MARCHID_HI 0x07b1 1693 + #define regVCN_MES_MARCHID_HI_BASE_IDX 1 1694 + #define regVCN_MES_MIMPID_LO 0x07b2 1695 + #define regVCN_MES_MIMPID_LO_BASE_IDX 1 1696 + #define regVCN_MES_MIMPID_HI 0x07b3 1697 + #define regVCN_MES_MIMPID_HI_BASE_IDX 1 1698 + #define regVCN_MES_MHARTID_LO 0x07b4 1699 + #define regVCN_MES_MHARTID_LO_BASE_IDX 1 1700 + #define regVCN_MES_MHARTID_HI 0x07b5 1701 + #define regVCN_MES_MHARTID_HI_BASE_IDX 1 1702 + #define regVCN_MES_DC_BASE_CNTL 0x07b6 1703 + #define regVCN_MES_DC_BASE_CNTL_BASE_IDX 1 1704 + #define regVCN_MES_DC_OP_CNTL 0x07b7 1705 + #define regVCN_MES_DC_OP_CNTL_BASE_IDX 1 1706 + #define regVCN_MES_MTIMECMP_LO 0x07b8 1707 + #define regVCN_MES_MTIMECMP_LO_BASE_IDX 1 1708 + #define regVCN_MES_MTIMECMP_HI 0x07b9 1709 + #define regVCN_MES_MTIMECMP_HI_BASE_IDX 1 1710 + #define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x07c2 1711 + #define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1 1712 + #define regVCN_MES_GP0_LO 0x07c3 1713 + #define regVCN_MES_GP0_LO_BASE_IDX 1 1714 + #define regVCN_MES_GP0_HI 0x07c4 1715 + #define regVCN_MES_GP0_HI_BASE_IDX 1 1716 + #define regVCN_MES_GP1_LO 0x07c5 1717 + #define regVCN_MES_GP1_LO_BASE_IDX 1 1718 + #define regVCN_MES_GP1_HI 0x07c6 1719 + #define regVCN_MES_GP1_HI_BASE_IDX 1 1720 + #define regVCN_MES_GP2_LO 0x07c7 1721 + #define regVCN_MES_GP2_LO_BASE_IDX 1 1722 + #define regVCN_MES_GP2_HI 0x07c8 1723 + #define regVCN_MES_GP2_HI_BASE_IDX 1 1724 + #define regVCN_MES_GP3_LO 0x07c9 1725 + #define regVCN_MES_GP3_LO_BASE_IDX 1 1726 + #define regVCN_MES_GP3_HI 0x07ca 1727 + #define regVCN_MES_GP3_HI_BASE_IDX 1 1728 + #define regVCN_MES_GP4_LO 0x07cb 1729 + #define regVCN_MES_GP4_LO_BASE_IDX 1 1730 + #define regVCN_MES_GP4_HI 0x07cc 1731 + #define regVCN_MES_GP4_HI_BASE_IDX 1 1732 + #define regVCN_MES_GP5_LO 0x07cd 1733 + #define regVCN_MES_GP5_LO_BASE_IDX 1 1734 + #define regVCN_MES_GP5_HI 0x07ce 1735 + #define regVCN_MES_GP5_HI_BASE_IDX 1 1736 + #define regVCN_MES_GP6_LO 0x07cf 1737 + #define regVCN_MES_GP6_LO_BASE_IDX 1 1738 + #define regVCN_MES_GP6_HI 0x07d0 1739 + #define regVCN_MES_GP6_HI_BASE_IDX 1 1740 + #define regVCN_MES_GP7_LO 0x07d1 1741 + #define regVCN_MES_GP7_LO_BASE_IDX 1 1742 + #define regVCN_MES_GP7_HI 0x07d2 1743 + #define regVCN_MES_GP7_HI_BASE_IDX 1 1744 + #define regVCN_MES_GP8_LO 0x07d3 1745 + #define regVCN_MES_GP8_LO_BASE_IDX 1 1746 + #define regVCN_MES_GP8_HI 0x07d4 1747 + #define regVCN_MES_GP8_HI_BASE_IDX 1 1748 + #define regVCN_MES_GP9_LO 0x07d5 1749 + #define regVCN_MES_GP9_LO_BASE_IDX 1 1750 + #define regVCN_MES_GP9_HI 0x07d6 1751 + #define regVCN_MES_GP9_HI_BASE_IDX 1 1752 + #define regVCN_MES_DM_INDEX_ADDR 0x0800 1753 + #define regVCN_MES_DM_INDEX_ADDR_BASE_IDX 1 1754 + #define regVCN_MES_DM_INDEX_DATA 0x0801 1755 + #define regVCN_MES_DM_INDEX_DATA_BASE_IDX 1 1756 + #define regVCN_MES_DBG_FROM_RST 0x0802 1757 + #define regVCN_MES_DBG_FROM_RST_BASE_IDX 1 1758 + #define regVCN_MES_LOCAL_BASE0_LO 0x0803 1759 + #define regVCN_MES_LOCAL_BASE0_LO_BASE_IDX 1 1760 + #define regVCN_MES_LOCAL_BASE0_HI 0x0804 1761 + #define regVCN_MES_LOCAL_BASE0_HI_BASE_IDX 1 1762 + #define regVCN_MES_LOCAL_MASK0_LO 0x0805 1763 + #define regVCN_MES_LOCAL_MASK0_LO_BASE_IDX 1 1764 + #define regVCN_MES_LOCAL_MASK0_HI 0x0806 1765 + #define regVCN_MES_LOCAL_MASK0_HI_BASE_IDX 1 1766 + #define regVCN_MES_LOCAL_APERTURE 0x0807 1767 + #define regVCN_MES_LOCAL_APERTURE_BASE_IDX 1 1768 + #define regVCN_MES_LOCAL_INSTR_BASE_LO 0x0808 1769 + #define regVCN_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 1770 + #define regVCN_MES_LOCAL_INSTR_BASE_HI 0x0809 1771 + #define regVCN_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 1772 + #define regVCN_MES_LOCAL_INSTR_MASK_LO 0x080a 1773 + #define regVCN_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 1774 + #define regVCN_MES_LOCAL_INSTR_MASK_HI 0x080b 1775 + #define regVCN_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 1776 + #define regVCN_MES_LOCAL_INSTR_APERTURE 0x080c 1777 + #define regVCN_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 1778 + #define regVCN_MES_LOCAL_SCRATCH_APERTURE 0x080d 1779 + #define regVCN_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 1780 + #define regVCN_MES_LOCAL_SCRATCH_BASE_LO 0x080e 1781 + #define regVCN_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 1782 + #define regVCN_MES_LOCAL_SCRATCH_BASE_HI 0x080f 1783 + #define regVCN_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 1784 + #define regVCN_MES_PERFCOUNT_CNTL 0x0819 1785 + #define regVCN_MES_PERFCOUNT_CNTL_BASE_IDX 1 1786 + #define regVCN_MES_PENDING_INTERRUPT 0x081a 1787 + #define regVCN_MES_PENDING_INTERRUPT_BASE_IDX 1 1788 + #define regVCN_MES_PRIV_LEVEL 0x081b 1789 + #define regVCN_MES_PRIV_LEVEL_BASE_IDX 1 1790 + #define regVCN_MES_PRIV_LEVEL_VIOLATION_STATUS 0x081c 1791 + #define regVCN_MES_PRIV_LEVEL_VIOLATION_STATUS_BASE_IDX 1 1792 + #define regVCN_MES_PRGRM_CNTR_START_HI 0x081d 1793 + #define regVCN_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 1794 + #define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI 0x081e 1795 + #define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI_BASE_IDX 1 1796 + #define regVCN_MES_INTERRUPT_DATA_16 0x081f 1797 + #define regVCN_MES_INTERRUPT_DATA_16_BASE_IDX 1 1798 + #define regVCN_MES_INTERRUPT_DATA_17 0x0820 1799 + #define regVCN_MES_INTERRUPT_DATA_17_BASE_IDX 1 1800 + #define regVCN_MES_INTERRUPT_DATA_18 0x0821 1801 + #define regVCN_MES_INTERRUPT_DATA_18_BASE_IDX 1 1802 + #define regVCN_MES_INTERRUPT_DATA_19 0x0822 1803 + #define regVCN_MES_INTERRUPT_DATA_19_BASE_IDX 1 1804 + #define regVCN_MES_INTERRUPT_DATA_20 0x0823 1805 + #define regVCN_MES_INTERRUPT_DATA_20_BASE_IDX 1 1806 + #define regVCN_MES_INTERRUPT_DATA_21 0x0824 1807 + #define regVCN_MES_INTERRUPT_DATA_21_BASE_IDX 1 1808 + #define regVCN_MES_INTERRUPT_DATA_22 0x0825 1809 + #define regVCN_MES_INTERRUPT_DATA_22_BASE_IDX 1 1810 + #define regVCN_MES_INTERRUPT_DATA_23 0x0826 1811 + #define regVCN_MES_INTERRUPT_DATA_23_BASE_IDX 1 1812 + #define regVCN_MES_INTERRUPT_DATA_24 0x0827 1813 + #define regVCN_MES_INTERRUPT_DATA_24_BASE_IDX 1 1814 + #define regVCN_MES_INTERRUPT_DATA_25 0x0828 1815 + #define regVCN_MES_INTERRUPT_DATA_25_BASE_IDX 1 1816 + #define regVCN_MES_INTERRUPT_DATA_26 0x0829 1817 + #define regVCN_MES_INTERRUPT_DATA_26_BASE_IDX 1 1818 + #define regVCN_MES_INTERRUPT_DATA_27 0x082a 1819 + #define regVCN_MES_INTERRUPT_DATA_27_BASE_IDX 1 1820 + #define regVCN_MES_INTERRUPT_DATA_28 0x082b 1821 + #define regVCN_MES_INTERRUPT_DATA_28_BASE_IDX 1 1822 + #define regVCN_MES_INTERRUPT_DATA_29 0x082c 1823 + #define regVCN_MES_INTERRUPT_DATA_29_BASE_IDX 1 1824 + #define regVCN_MES_INTERRUPT_DATA_30 0x082d 1825 + #define regVCN_MES_INTERRUPT_DATA_30_BASE_IDX 1 1826 + #define regVCN_MES_INTERRUPT_DATA_31 0x082e 1827 + #define regVCN_MES_INTERRUPT_DATA_31_BASE_IDX 1 1828 + #define regVCN_MES_DC_APERTURE0_BASE 0x082f 1829 + #define regVCN_MES_DC_APERTURE0_BASE_BASE_IDX 1 1830 + #define regVCN_MES_DC_APERTURE0_MASK 0x0830 1831 + #define regVCN_MES_DC_APERTURE0_MASK_BASE_IDX 1 1832 + #define regVCN_MES_DC_APERTURE0_CNTL 0x0831 1833 + #define regVCN_MES_DC_APERTURE0_CNTL_BASE_IDX 1 1834 + #define regVCN_MES_DC_APERTURE1_BASE 0x0832 1835 + #define regVCN_MES_DC_APERTURE1_BASE_BASE_IDX 1 1836 + #define regVCN_MES_DC_APERTURE1_MASK 0x0833 1837 + #define regVCN_MES_DC_APERTURE1_MASK_BASE_IDX 1 1838 + #define regVCN_MES_DC_APERTURE1_CNTL 0x0834 1839 + #define regVCN_MES_DC_APERTURE1_CNTL_BASE_IDX 1 1840 + #define regVCN_MES_DC_APERTURE2_BASE 0x0835 1841 + #define regVCN_MES_DC_APERTURE2_BASE_BASE_IDX 1 1842 + #define regVCN_MES_DC_APERTURE2_MASK 0x0836 1843 + #define regVCN_MES_DC_APERTURE2_MASK_BASE_IDX 1 1844 + #define regVCN_MES_DC_APERTURE2_CNTL 0x0837 1845 + #define regVCN_MES_DC_APERTURE2_CNTL_BASE_IDX 1 1846 + #define regVCN_MES_DC_APERTURE3_BASE 0x0838 1847 + #define regVCN_MES_DC_APERTURE3_BASE_BASE_IDX 1 1848 + #define regVCN_MES_DC_APERTURE3_MASK 0x0839 1849 + #define regVCN_MES_DC_APERTURE3_MASK_BASE_IDX 1 1850 + #define regVCN_MES_DC_APERTURE3_CNTL 0x083a 1851 + #define regVCN_MES_DC_APERTURE3_CNTL_BASE_IDX 1 1852 + #define regVCN_MES_DC_APERTURE4_BASE 0x083b 1853 + #define regVCN_MES_DC_APERTURE4_BASE_BASE_IDX 1 1854 + #define regVCN_MES_DC_APERTURE4_MASK 0x083c 1855 + #define regVCN_MES_DC_APERTURE4_MASK_BASE_IDX 1 1856 + #define regVCN_MES_DC_APERTURE4_CNTL 0x083d 1857 + #define regVCN_MES_DC_APERTURE4_CNTL_BASE_IDX 1 1858 + #define regVCN_MES_DC_APERTURE5_BASE 0x083e 1859 + #define regVCN_MES_DC_APERTURE5_BASE_BASE_IDX 1 1860 + #define regVCN_MES_DC_APERTURE5_MASK 0x083f 1861 + #define regVCN_MES_DC_APERTURE5_MASK_BASE_IDX 1 1862 + #define regVCN_MES_DC_APERTURE5_CNTL 0x0840 1863 + #define regVCN_MES_DC_APERTURE5_CNTL_BASE_IDX 1 1864 + #define regVCN_MES_DC_APERTURE6_BASE 0x0841 1865 + #define regVCN_MES_DC_APERTURE6_BASE_BASE_IDX 1 1866 + #define regVCN_MES_DC_APERTURE6_MASK 0x0842 1867 + #define regVCN_MES_DC_APERTURE6_MASK_BASE_IDX 1 1868 + #define regVCN_MES_DC_APERTURE6_CNTL 0x0843 1869 + #define regVCN_MES_DC_APERTURE6_CNTL_BASE_IDX 1 1870 + #define regVCN_MES_DC_APERTURE7_BASE 0x0844 1871 + #define regVCN_MES_DC_APERTURE7_BASE_BASE_IDX 1 1872 + #define regVCN_MES_DC_APERTURE7_MASK 0x0845 1873 + #define regVCN_MES_DC_APERTURE7_MASK_BASE_IDX 1 1874 + #define regVCN_MES_DC_APERTURE7_CNTL 0x0846 1875 + #define regVCN_MES_DC_APERTURE7_CNTL_BASE_IDX 1 1876 + #define regVCN_MES_DC_APERTURE8_BASE 0x0847 1877 + #define regVCN_MES_DC_APERTURE8_BASE_BASE_IDX 1 1878 + #define regVCN_MES_DC_APERTURE8_MASK 0x0848 1879 + #define regVCN_MES_DC_APERTURE8_MASK_BASE_IDX 1 1880 + #define regVCN_MES_DC_APERTURE8_CNTL 0x0849 1881 + #define regVCN_MES_DC_APERTURE8_CNTL_BASE_IDX 1 1882 + #define regVCN_MES_DC_APERTURE9_BASE 0x084a 1883 + #define regVCN_MES_DC_APERTURE9_BASE_BASE_IDX 1 1884 + #define regVCN_MES_DC_APERTURE9_MASK 0x084b 1885 + #define regVCN_MES_DC_APERTURE9_MASK_BASE_IDX 1 1886 + #define regVCN_MES_DC_APERTURE9_CNTL 0x084c 1887 + #define regVCN_MES_DC_APERTURE9_CNTL_BASE_IDX 1 1888 + #define regVCN_MES_DC_APERTURE10_BASE 0x084d 1889 + #define regVCN_MES_DC_APERTURE10_BASE_BASE_IDX 1 1890 + #define regVCN_MES_DC_APERTURE10_MASK 0x084e 1891 + #define regVCN_MES_DC_APERTURE10_MASK_BASE_IDX 1 1892 + #define regVCN_MES_DC_APERTURE10_CNTL 0x084f 1893 + #define regVCN_MES_DC_APERTURE10_CNTL_BASE_IDX 1 1894 + #define regVCN_MES_DC_APERTURE11_BASE 0x0850 1895 + #define regVCN_MES_DC_APERTURE11_BASE_BASE_IDX 1 1896 + #define regVCN_MES_DC_APERTURE11_MASK 0x0851 1897 + #define regVCN_MES_DC_APERTURE11_MASK_BASE_IDX 1 1898 + #define regVCN_MES_DC_APERTURE11_CNTL 0x0852 1899 + #define regVCN_MES_DC_APERTURE11_CNTL_BASE_IDX 1 1900 + #define regVCN_MES_DC_APERTURE12_BASE 0x0853 1901 + #define regVCN_MES_DC_APERTURE12_BASE_BASE_IDX 1 1902 + #define regVCN_MES_DC_APERTURE12_MASK 0x0854 1903 + #define regVCN_MES_DC_APERTURE12_MASK_BASE_IDX 1 1904 + #define regVCN_MES_DC_APERTURE12_CNTL 0x0855 1905 + #define regVCN_MES_DC_APERTURE12_CNTL_BASE_IDX 1 1906 + #define regVCN_MES_DC_APERTURE13_BASE 0x0856 1907 + #define regVCN_MES_DC_APERTURE13_BASE_BASE_IDX 1 1908 + #define regVCN_MES_DC_APERTURE13_MASK 0x0857 1909 + #define regVCN_MES_DC_APERTURE13_MASK_BASE_IDX 1 1910 + #define regVCN_MES_DC_APERTURE13_CNTL 0x0858 1911 + #define regVCN_MES_DC_APERTURE13_CNTL_BASE_IDX 1 1912 + #define regVCN_MES_DC_APERTURE14_BASE 0x0859 1913 + #define regVCN_MES_DC_APERTURE14_BASE_BASE_IDX 1 1914 + #define regVCN_MES_DC_APERTURE14_MASK 0x085a 1915 + #define regVCN_MES_DC_APERTURE14_MASK_BASE_IDX 1 1916 + #define regVCN_MES_DC_APERTURE14_CNTL 0x085b 1917 + #define regVCN_MES_DC_APERTURE14_CNTL_BASE_IDX 1 1918 + #define regVCN_MES_DC_APERTURE15_BASE 0x085c 1919 + #define regVCN_MES_DC_APERTURE15_BASE_BASE_IDX 1 1920 + #define regVCN_MES_DC_APERTURE15_MASK 0x085d 1921 + #define regVCN_MES_DC_APERTURE15_MASK_BASE_IDX 1 1922 + #define regVCN_MES_DC_APERTURE15_CNTL 0x085e 1923 + #define regVCN_MES_DC_APERTURE15_CNTL_BASE_IDX 1 1924 + 1925 + #define regVCN_HYP_ME1_PIPE0_VMID_CNTL 0x0890 1926 + #define regVCN_HYP_ME1_PIPE0_VMID_CNTL_BASE_IDX 1 1927 + #define regVCN_HYP_ME1_PIPE1_VMID_CNTL 0x0891 1928 + #define regVCN_HYP_ME1_PIPE1_VMID_CNTL_BASE_IDX 1 1929 + #define regVCN_MES_IC_BASE_LO 0x08d0 1930 + #define regVCN_MES_IC_BASE_LO_BASE_IDX 1 1931 + #define regVCN_MES_MIBASE_LO 0x08d0 1932 + #define regVCN_MES_MIBASE_LO_BASE_IDX 1 1933 + #define regVCN_MES_IC_BASE_HI 0x08d1 1934 + #define regVCN_MES_IC_BASE_HI_BASE_IDX 1 1935 + #define regVCN_MES_MIBASE_HI 0x08d1 1936 + #define regVCN_MES_MIBASE_HI_BASE_IDX 1 1937 + #define regVCN_MES_IC_BASE_CNTL 0x08d2 1938 + #define regVCN_MES_IC_BASE_CNTL_BASE_IDX 1 1939 + #define regVCN_MES_DC_BASE_LO 0x08d4 1940 + #define regVCN_MES_DC_BASE_LO_BASE_IDX 1 1941 + #define regVCN_MES_MDBASE_LO 0x08d4 1942 + #define regVCN_MES_MDBASE_LO_BASE_IDX 1 1943 + #define regVCN_MES_DC_BASE_HI 0x08d5 1944 + #define regVCN_MES_DC_BASE_HI_BASE_IDX 1 1945 + #define regVCN_MES_MDBASE_HI 0x08d5 1946 + #define regVCN_MES_MDBASE_HI_BASE_IDX 1 1947 + #define regVCN_MES_MIBOUND_LO 0x08db 1948 + #define regVCN_MES_MIBOUND_LO_BASE_IDX 1 1949 + #define regVCN_MES_MIBOUND_HI 0x08dc 1950 + #define regVCN_MES_MIBOUND_HI_BASE_IDX 1 1951 + #define regVCN_MES_MDBOUND_LO 0x08dd 1952 + #define regVCN_MES_MDBOUND_LO_BASE_IDX 1 1953 + #define regVCN_MES_MDBOUND_HI 0x08de 1954 + #define regVCN_MES_MDBOUND_HI_BASE_IDX 1 1585 1955 1586 1956 // addressBlock: uvdctxind 1587 1957 // base address: 0x0
+882
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h
··· 6769 6769 #define VCN_RB4_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 6770 6770 #define VCN_RB4_DB_CTRL__EN_MASK 0x40000000L 6771 6771 #define VCN_RB4_DB_CTRL__HIT_MASK 0x80000000L 6772 + //VCN_UMSCH_RB_DB_CTRL 6773 + #define VCN_UMSCH_RB_DB_CTRL__OFFSET__SHIFT 0x2 6774 + #define VCN_UMSCH_RB_DB_CTRL__EN__SHIFT 0x1e 6775 + #define VCN_UMSCH_RB_DB_CTRL__HIT__SHIFT 0x1f 6776 + #define VCN_UMSCH_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 6777 + #define VCN_UMSCH_RB_DB_CTRL__EN_MASK 0x40000000L 6778 + #define VCN_UMSCH_RB_DB_CTRL__HIT_MASK 0x80000000L 6779 + //VCN_AGDB_CTRL0 6780 + #define VCN_AGDB_CTRL0__OFFSET__SHIFT 0x2 6781 + #define VCN_AGDB_CTRL0__EN__SHIFT 0x1e 6782 + #define VCN_AGDB_CTRL0__HIT__SHIFT 0x1f 6783 + #define VCN_AGDB_CTRL0__OFFSET_MASK 0x0FFFFFFCL 6784 + #define VCN_AGDB_CTRL0__EN_MASK 0x40000000L 6785 + #define VCN_AGDB_CTRL0__HIT_MASK 0x80000000L 6786 + //VCN_AGDB_CTRL1 6787 + #define VCN_AGDB_CTRL1__OFFSET__SHIFT 0x2 6788 + #define VCN_AGDB_CTRL1__EN__SHIFT 0x1e 6789 + #define VCN_AGDB_CTRL1__HIT__SHIFT 0x1f 6790 + #define VCN_AGDB_CTRL1__OFFSET_MASK 0x0FFFFFFCL 6791 + #define VCN_AGDB_CTRL1__EN_MASK 0x40000000L 6792 + #define VCN_AGDB_CTRL1__HIT_MASK 0x80000000L 6793 + //VCN_AGDB_CTRL2 6794 + #define VCN_AGDB_CTRL2__OFFSET__SHIFT 0x2 6795 + #define VCN_AGDB_CTRL2__EN__SHIFT 0x1e 6796 + #define VCN_AGDB_CTRL2__HIT__SHIFT 0x1f 6797 + #define VCN_AGDB_CTRL2__OFFSET_MASK 0x0FFFFFFCL 6798 + #define VCN_AGDB_CTRL2__EN_MASK 0x40000000L 6799 + #define VCN_AGDB_CTRL2__HIT_MASK 0x80000000L 6800 + //VCN_AGDB_CTRL3 6801 + #define VCN_AGDB_CTRL3__OFFSET__SHIFT 0x2 6802 + #define VCN_AGDB_CTRL3__EN__SHIFT 0x1e 6803 + #define VCN_AGDB_CTRL3__HIT__SHIFT 0x1f 6804 + #define VCN_AGDB_CTRL3__OFFSET_MASK 0x0FFFFFFCL 6805 + #define VCN_AGDB_CTRL3__EN_MASK 0x40000000L 6806 + #define VCN_AGDB_CTRL3__HIT_MASK 0x80000000L 6807 + //VCN_AGDB_CTRL4 6808 + #define VCN_AGDB_CTRL4__OFFSET__SHIFT 0x2 6809 + #define VCN_AGDB_CTRL4__EN__SHIFT 0x1e 6810 + #define VCN_AGDB_CTRL4__HIT__SHIFT 0x1f 6811 + #define VCN_AGDB_CTRL4__OFFSET_MASK 0x0FFFFFFCL 6812 + #define VCN_AGDB_CTRL4__EN_MASK 0x40000000L 6813 + #define VCN_AGDB_CTRL4__HIT_MASK 0x80000000L 6814 + //VCN_AGDB_CTRL5 6815 + #define VCN_AGDB_CTRL5__OFFSET__SHIFT 0x2 6816 + #define VCN_AGDB_CTRL5__EN__SHIFT 0x1e 6817 + #define VCN_AGDB_CTRL5__HIT__SHIFT 0x1f 6818 + #define VCN_AGDB_CTRL5__OFFSET_MASK 0x0FFFFFFCL 6819 + #define VCN_AGDB_CTRL5__EN_MASK 0x40000000L 6820 + #define VCN_AGDB_CTRL5__HIT_MASK 0x80000000L 6821 + //VCN_AGDB_MASK0 6822 + #define VCN_AGDB_MASK0__MASK__SHIFT 0x2 6823 + #define VCN_AGDB_MASK0__MASK_MASK 0x0FFFFFFCL 6824 + //VCN_AGDB_MASK1 6825 + #define VCN_AGDB_MASK1__MASK__SHIFT 0x2 6826 + #define VCN_AGDB_MASK1__MASK_MASK 0x0FFFFFFCL 6827 + //VCN_AGDB_MASK2 6828 + #define VCN_AGDB_MASK2__MASK__SHIFT 0x2 6829 + #define VCN_AGDB_MASK2__MASK_MASK 0x0FFFFFFCL 6830 + //VCN_AGDB_MASK3 6831 + #define VCN_AGDB_MASK3__MASK__SHIFT 0x2 6832 + #define VCN_AGDB_MASK3__MASK_MASK 0x0FFFFFFCL 6833 + //VCN_AGDB_MASK4 6834 + #define VCN_AGDB_MASK4__MASK__SHIFT 0x2 6835 + #define VCN_AGDB_MASK4__MASK_MASK 0x0FFFFFFCL 6836 + //VCN_AGDB_MASK5 6837 + #define VCN_AGDB_MASK5__MASK__SHIFT 0x2 6838 + #define VCN_AGDB_MASK5__MASK_MASK 0x0FFFFFFCL 6772 6839 //VCN_RB_ENABLE 6773 6840 #define VCN_RB_ENABLE__RB_EN__SHIFT 0x0 6774 6841 #define VCN_RB_ENABLE__JPEG_RB_EN__SHIFT 0x1 ··· 8118 8051 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK_MASK 0x04000000L 8119 8052 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK_MASK 0x08000000L 8120 8053 8054 + //VCN_UMSCH_MES_UTCL1_CNTL 8055 + #define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY__SHIFT 0x0 8056 + #define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop__SHIFT 0x14 8057 + #define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode__SHIFT 0x15 8058 + #define VCN_UMSCH_MES_UTCL1_CNTL__DropMode__SHIFT 0x16 8059 + #define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate__SHIFT 0x17 8060 + #define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY_MASK 0x000FFFFFL 8061 + #define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop_MASK 0x00100000L 8062 + #define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode_MASK 0x00200000L 8063 + #define VCN_UMSCH_MES_UTCL1_CNTL__DropMode_MASK 0x00400000L 8064 + #define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate_MASK 0x00800000L 8065 + //VCN_UMSCH_MES_BUSY 8066 + #define VCN_UMSCH_MES_BUSY__MesScratchRamBusy__SHIFT 0x0 8067 + #define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy__SHIFT 0x1 8068 + #define VCN_UMSCH_MES_BUSY__MesDataCacheBusy__SHIFT 0x2 8069 + #define VCN_UMSCH_MES_BUSY__MesBusy__SHIFT 0x3 8070 + #define VCN_UMSCH_MES_BUSY__MesLoadBusy__SHIFT 0x4 8071 + #define VCN_UMSCH_MES_BUSY__MesMutexBusy__SHIFT 0x5 8072 + #define VCN_UMSCH_MES_BUSY__MesThreadBusy__SHIFT 0x6 8073 + #define VCN_UMSCH_MES_BUSY__MesMessageBusy__SHIFT 0x8 8074 + #define VCN_UMSCH_MES_BUSY__MesTcBusy__SHIFT 0xa 8075 + #define VCN_UMSCH_MES_BUSY__MesDmaPending__SHIFT 0xc 8076 + #define VCN_UMSCH_MES_BUSY__MesScratchRamBusy_MASK 0x00000001L 8077 + #define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy_MASK 0x00000002L 8078 + #define VCN_UMSCH_MES_BUSY__MesDataCacheBusy_MASK 0x00000004L 8079 + #define VCN_UMSCH_MES_BUSY__MesBusy_MASK 0x00000008L 8080 + #define VCN_UMSCH_MES_BUSY__MesLoadBusy_MASK 0x00000010L 8081 + #define VCN_UMSCH_MES_BUSY__MesMutexBusy_MASK 0x00000020L 8082 + #define VCN_UMSCH_MES_BUSY__MesThreadBusy_MASK 0x000000C0L 8083 + #define VCN_UMSCH_MES_BUSY__MesMessageBusy_MASK 0x00000300L 8084 + #define VCN_UMSCH_MES_BUSY__MesTcBusy_MASK 0x00000C00L 8085 + #define VCN_UMSCH_MES_BUSY__MesDmaPending_MASK 0x00003000L 8086 + //VCN_UMSCH_RB_BASE_LO 8087 + #define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 8088 + #define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 8089 + //VCN_UMSCH_RB_BASE_HI 8090 + #define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 8091 + #define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 8092 + //VCN_UMSCH_RB_SIZE 8093 + #define VCN_UMSCH_RB_SIZE__WPTR__SHIFT 0x4 8094 + #define VCN_UMSCH_RB_SIZE__WPTR_MASK 0x007FFFF0L 8095 + //VCN_UMSCH_RB_RPTR 8096 + #define VCN_UMSCH_RB_RPTR__WPTR__SHIFT 0x4 8097 + #define VCN_UMSCH_RB_RPTR__WPTR_MASK 0x007FFFF0L 8098 + //VCN_UMSCH_RB_WPTR 8099 + #define VCN_UMSCH_RB_WPTR__WPTR__SHIFT 0x4 8100 + #define VCN_UMSCH_RB_WPTR__WPTR_MASK 0x007FFFF0L 8101 + //VCN_UMSCH_MASTINT_EN 8102 + #define VCN_UMSCH_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 8103 + #define VCN_UMSCH_MASTINT_EN__SYS_EN__SHIFT 0x2 8104 + #define VCN_UMSCH_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 8105 + #define VCN_UMSCH_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 8106 + #define VCN_UMSCH_MASTINT_EN__SYS_EN_MASK 0x00000004L 8107 + #define VCN_UMSCH_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 8108 + //VCN_UMSCH_IH_CTRL 8109 + #define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 8110 + #define VCN_UMSCH_IH_CTRL__IH_STALL_EN__SHIFT 0x1 8111 + #define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 8112 + #define VCN_UMSCH_IH_CTRL__IH_VMID__SHIFT 0x3 8113 + #define VCN_UMSCH_IH_CTRL__IH_USER_DATA__SHIFT 0x7 8114 + #define VCN_UMSCH_IH_CTRL__IH_RINGID__SHIFT 0x13 8115 + #define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 8116 + #define VCN_UMSCH_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 8117 + #define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 8118 + #define VCN_UMSCH_IH_CTRL__IH_VMID_MASK 0x00000078L 8119 + #define VCN_UMSCH_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 8120 + #define VCN_UMSCH_IH_CTRL__IH_RINGID_MASK 0x07F80000L 8121 + //VCN_UMSCH_SYS_INT_EN 8122 + #define VCN_UMSCH_SYS_INT_EN__INT0__SHIFT 0x0 8123 + #define VCN_UMSCH_SYS_INT_EN__INT1__SHIFT 0x1 8124 + #define VCN_UMSCH_SYS_INT_EN__INT2__SHIFT 0x2 8125 + #define VCN_UMSCH_SYS_INT_EN__INT3__SHIFT 0x3 8126 + #define VCN_UMSCH_SYS_INT_EN__INT4__SHIFT 0x4 8127 + #define VCN_UMSCH_SYS_INT_EN__INT5__SHIFT 0x5 8128 + #define VCN_UMSCH_SYS_INT_EN__INT6__SHIFT 0x6 8129 + #define VCN_UMSCH_SYS_INT_EN__INT7__SHIFT 0x7 8130 + #define VCN_UMSCH_SYS_INT_EN__INT0_MASK 0x00000001L 8131 + #define VCN_UMSCH_SYS_INT_EN__INT1_MASK 0x00000002L 8132 + #define VCN_UMSCH_SYS_INT_EN__INT2_MASK 0x00000004L 8133 + #define VCN_UMSCH_SYS_INT_EN__INT3_MASK 0x00000008L 8134 + #define VCN_UMSCH_SYS_INT_EN__INT4_MASK 0x00000010L 8135 + #define VCN_UMSCH_SYS_INT_EN__INT5_MASK 0x00000020L 8136 + #define VCN_UMSCH_SYS_INT_EN__INT6_MASK 0x00000040L 8137 + #define VCN_UMSCH_SYS_INT_EN__INT7_MASK 0x00000080L 8138 + //VCN_UMSCH_SYS_INT_STATUS 8139 + #define VCN_UMSCH_SYS_INT_STATUS__INT0__SHIFT 0x0 8140 + #define VCN_UMSCH_SYS_INT_STATUS__INT1__SHIFT 0x1 8141 + #define VCN_UMSCH_SYS_INT_STATUS__INT2__SHIFT 0x2 8142 + #define VCN_UMSCH_SYS_INT_STATUS__INT3__SHIFT 0x3 8143 + #define VCN_UMSCH_SYS_INT_STATUS__INT4__SHIFT 0x4 8144 + #define VCN_UMSCH_SYS_INT_STATUS__INT5__SHIFT 0x5 8145 + #define VCN_UMSCH_SYS_INT_STATUS__INT6__SHIFT 0x6 8146 + #define VCN_UMSCH_SYS_INT_STATUS__INT7__SHIFT 0x7 8147 + #define VCN_UMSCH_SYS_INT_STATUS__INT0_MASK 0x00000001L 8148 + #define VCN_UMSCH_SYS_INT_STATUS__INT1_MASK 0x00000002L 8149 + #define VCN_UMSCH_SYS_INT_STATUS__INT2_MASK 0x00000004L 8150 + #define VCN_UMSCH_SYS_INT_STATUS__INT3_MASK 0x00000008L 8151 + #define VCN_UMSCH_SYS_INT_STATUS__INT4_MASK 0x00000010L 8152 + #define VCN_UMSCH_SYS_INT_STATUS__INT5_MASK 0x00000020L 8153 + #define VCN_UMSCH_SYS_INT_STATUS__INT6_MASK 0x00000040L 8154 + #define VCN_UMSCH_SYS_INT_STATUS__INT7_MASK 0x00000080L 8155 + //VCN_UMSCH_SYS_INT_ACK 8156 + #define VCN_UMSCH_SYS_INT_ACK__INT0__SHIFT 0x0 8157 + #define VCN_UMSCH_SYS_INT_ACK__INT1__SHIFT 0x1 8158 + #define VCN_UMSCH_SYS_INT_ACK__INT2__SHIFT 0x2 8159 + #define VCN_UMSCH_SYS_INT_ACK__INT3__SHIFT 0x3 8160 + #define VCN_UMSCH_SYS_INT_ACK__INT4__SHIFT 0x4 8161 + #define VCN_UMSCH_SYS_INT_ACK__INT5__SHIFT 0x5 8162 + #define VCN_UMSCH_SYS_INT_ACK__INT6__SHIFT 0x6 8163 + #define VCN_UMSCH_SYS_INT_ACK__INT7__SHIFT 0x7 8164 + #define VCN_UMSCH_SYS_INT_ACK__INT0_MASK 0x00000001L 8165 + #define VCN_UMSCH_SYS_INT_ACK__INT1_MASK 0x00000002L 8166 + #define VCN_UMSCH_SYS_INT_ACK__INT2_MASK 0x00000004L 8167 + #define VCN_UMSCH_SYS_INT_ACK__INT3_MASK 0x00000008L 8168 + #define VCN_UMSCH_SYS_INT_ACK__INT4_MASK 0x00000010L 8169 + #define VCN_UMSCH_SYS_INT_ACK__INT5_MASK 0x00000020L 8170 + #define VCN_UMSCH_SYS_INT_ACK__INT6_MASK 0x00000040L 8171 + #define VCN_UMSCH_SYS_INT_ACK__INT7_MASK 0x00000080L 8172 + //VCN_UMSCH_SYS_INT_SRC 8173 + #define VCN_UMSCH_SYS_INT_SRC__INT0__SHIFT 0x0 8174 + #define VCN_UMSCH_SYS_INT_SRC__INT1__SHIFT 0x1 8175 + #define VCN_UMSCH_SYS_INT_SRC__INT2__SHIFT 0x2 8176 + #define VCN_UMSCH_SYS_INT_SRC__INT3__SHIFT 0x3 8177 + #define VCN_UMSCH_SYS_INT_SRC__INT4__SHIFT 0x4 8178 + #define VCN_UMSCH_SYS_INT_SRC__INT5__SHIFT 0x5 8179 + #define VCN_UMSCH_SYS_INT_SRC__INT6__SHIFT 0x6 8180 + #define VCN_UMSCH_SYS_INT_SRC__INT7__SHIFT 0x7 8181 + #define VCN_UMSCH_SYS_INT_SRC__INT0_MASK 0x00000001L 8182 + #define VCN_UMSCH_SYS_INT_SRC__INT1_MASK 0x00000002L 8183 + #define VCN_UMSCH_SYS_INT_SRC__INT2_MASK 0x00000004L 8184 + #define VCN_UMSCH_SYS_INT_SRC__INT3_MASK 0x00000008L 8185 + #define VCN_UMSCH_SYS_INT_SRC__INT4_MASK 0x00000010L 8186 + #define VCN_UMSCH_SYS_INT_SRC__INT5_MASK 0x00000020L 8187 + #define VCN_UMSCH_SYS_INT_SRC__INT6_MASK 0x00000040L 8188 + #define VCN_UMSCH_SYS_INT_SRC__INT7_MASK 0x00000080L 8189 + //VCN_UMSCH_IH_CTX_CTRL 8190 + #define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID__SHIFT 0x0 8191 + #define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID_MASK 0x0FFFFFFFL 8192 + //VCN_UMSCH_CGC_CTRL 8193 + #define VCN_UMSCH_CGC_CTRL__UMSCH_MODE__SHIFT 0x0 8194 + #define VCN_UMSCH_CGC_CTRL__UMSCH__SHIFT 0x1 8195 + #define VCN_UMSCH_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 8196 + #define VCN_UMSCH_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 8197 + #define VCN_UMSCH_CGC_CTRL__UMSCH_REG_CG_MODE__SHIFT 0xe 8198 + #define VCN_UMSCH_CGC_CTRL__UMSCH_MODE_MASK 0x00000001L 8199 + #define VCN_UMSCH_CGC_CTRL__UMSCH_MASK 0x00000002L 8200 + #define VCN_UMSCH_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 8201 + #define VCN_UMSCH_CGC_CTRL__CLK_OFF_DELAY_MASK 0x00003FC0L 8202 + #define VCN_UMSCH_CGC_CTRL__UMSCH_REG_CG_MODE_MASK 0x00004000L 8203 + //VCN_UMSCH_CGC_STATUS 8204 + #define VCN_UMSCH_CGC_STATUS__UMSCH_CORE_ACTIVE__SHIFT 0x0 8205 + #define VCN_UMSCH_CGC_STATUS__UMSCH_CORE_ACTIVE_MASK 0x00000001L 8206 + //VCN_UMSCH_CGC_MEM_CTRL 8207 + #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_HW_ON__SHIFT 0x0 8208 + #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_SW_ON__SHIFT 0x1 8209 + #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_DS_EN__SHIFT 0x2 8210 + #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_SD_EN__SHIFT 0x3 8211 + #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_HW_ON_MASK 0x00000001L 8212 + #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_SW_ON_MASK 0x00000002L 8213 + #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_DS_EN_MASK 0x00000004L 8214 + #define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_SD_EN_MASK 0x00000008L 8215 + //UVD_INTERNAL_REG_VIOLATION_8 8216 + #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_ADDR__SHIFT 0x2 8217 + #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_MASTER_ID__SHIFT 0x14 8218 + #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_OP__SHIFT 0x18 8219 + #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_ADDR_MASK 0x000FFFFCL 8220 + #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_MASTER_ID_MASK 0x00F00000L 8221 + #define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_OP_MASK 0x01000000L 8222 + //UVD_UMSCH_FORCE 8223 + #define UVD_UMSCH_FORCE__IC_FORCE_GPUVM__SHIFT 0x0 8224 + #define UVD_UMSCH_FORCE__DC_FORCE_GPUVM__SHIFT 0x1 8225 + #define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE__SHIFT 0x2 8226 + #define UVD_UMSCH_FORCE__IC_FORCE_GPUVM_MASK 0x00000001L 8227 + #define UVD_UMSCH_FORCE__DC_FORCE_GPUVM_MASK 0x00000002L 8228 + #define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE_MASK 0x00000004L 8229 + //UVD_UMSCH_DEBUG_INDEX 8230 + #define UVD_UMSCH_DEBUG_INDEX__DEBUG_READ_ADDR__SHIFT 0x0 8231 + #define UVD_UMSCH_DEBUG_INDEX__DEBUG_ADDR_FREE_STR_DIS__SHIFT 0x1e 8232 + #define UVD_UMSCH_DEBUG_INDEX__DEBUG_RESET__SHIFT 0x1f 8233 + #define UVD_UMSCH_DEBUG_INDEX__DEBUG_READ_ADDR_MASK 0x0000001FL 8234 + #define UVD_UMSCH_DEBUG_INDEX__DEBUG_ADDR_FREE_STR_DIS_MASK 0x40000000L 8235 + #define UVD_UMSCH_DEBUG_INDEX__DEBUG_RESET_MASK 0x80000000L 8236 + //UVD_UMSCH_DEBUG_DATA_LO 8237 + #define UVD_UMSCH_DEBUG_DATA_LO__DEBUG_DATA_LO__SHIFT 0x0 8238 + #define UVD_UMSCH_DEBUG_DATA_LO__DEBUG_DATA_LO_MASK 0xFFFFFFFFL 8239 + //UVD_UMSCH_DEBUG_DATA_HI 8240 + #define UVD_UMSCH_DEBUG_DATA_HI__DEBUG_DATA_HI__SHIFT 0x0 8241 + #define UVD_UMSCH_DEBUG_DATA_HI__DEBUG_DATA_HI_MASK 0xFFFFFFFFL 8242 + //UVD_UMSCH_DEBUG_UTCL2_TCIU_IF 8243 + #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_IC_NACK__SHIFT 0x0 8244 + #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_DC_NACK__SHIFT 0x2 8245 + #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_IC_DROP__SHIFT 0x4 8246 + #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_DC_DROP__SHIFT 0x5 8247 + #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_IC_NACK_MASK 0x00000003L 8248 + #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_DC_NACK_MASK 0x0000000CL 8249 + #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_IC_DROP_MASK 0x00000010L 8250 + #define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_DC_DROP_MASK 0x00000020L 8251 + //UMSCH_MES_RESET_CTRL 8252 + #define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET__SHIFT 0x0 8253 + #define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET_MASK 0x00000001L 8254 + 8255 + //VCN_MES_PRGRM_CNTR_START 8256 + #define VCN_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 8257 + #define VCN_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL 8258 + //VCN_MES_INTR_ROUTINE_START 8259 + #define VCN_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 8260 + #define VCN_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL 8261 + //VCN_MES_MTVEC_LO 8262 + #define VCN_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 8263 + #define VCN_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL 8264 + //VCN_MES_INTR_ROUTINE_START_HI 8265 + #define VCN_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 8266 + #define VCN_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL 8267 + //VCN_MES_MTVEC_HI 8268 + #define VCN_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 8269 + #define VCN_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL 8270 + //VCN_MES_CNTL 8271 + #define VCN_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 8272 + #define VCN_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 8273 + #define VCN_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 8274 + #define VCN_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 8275 + #define VCN_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 8276 + #define VCN_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a 8277 + #define VCN_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b 8278 + #define VCN_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c 8279 + #define VCN_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d 8280 + #define VCN_MES_CNTL__MES_HALT__SHIFT 0x1e 8281 + #define VCN_MES_CNTL__MES_STEP__SHIFT 0x1f 8282 + #define VCN_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L 8283 + #define VCN_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L 8284 + #define VCN_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L 8285 + #define VCN_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L 8286 + #define VCN_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L 8287 + #define VCN_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L 8288 + #define VCN_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L 8289 + #define VCN_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L 8290 + #define VCN_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L 8291 + #define VCN_MES_CNTL__MES_HALT_MASK 0x40000000L 8292 + #define VCN_MES_CNTL__MES_STEP_MASK 0x80000000L 8293 + //VCN_MES_PIPE_PRIORITY_CNTS 8294 + #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 8295 + #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 8296 + #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 8297 + #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 8298 + #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL 8299 + #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L 8300 + #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L 8301 + #define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L 8302 + //VCN_MES_PIPE0_PRIORITY 8303 + #define VCN_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 8304 + #define VCN_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L 8305 + //VCN_MES_PIPE1_PRIORITY 8306 + #define VCN_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 8307 + #define VCN_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L 8308 + //VCN_MES_PIPE2_PRIORITY 8309 + #define VCN_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 8310 + #define VCN_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L 8311 + //VCN_MES_PIPE3_PRIORITY 8312 + #define VCN_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 8313 + #define VCN_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L 8314 + //VCN_MES_HEADER_DUMP 8315 + #define VCN_MES_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 8316 + #define VCN_MES_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL 8317 + //VCN_MES_MIE_LO 8318 + #define VCN_MES_MIE_LO__MES_INT__SHIFT 0x0 8319 + #define VCN_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL 8320 + //VCN_MES_MIE_HI 8321 + #define VCN_MES_MIE_HI__MES_INT__SHIFT 0x0 8322 + #define VCN_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL 8323 + //VCN_MES_INTERRUPT 8324 + #define VCN_MES_INTERRUPT__MES_INT__SHIFT 0x0 8325 + #define VCN_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL 8326 + //VCN_MES_SCRATCH_INDEX 8327 + #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 8328 + #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f 8329 + #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL 8330 + #define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L 8331 + //VCN_MES_SCRATCH_DATA 8332 + #define VCN_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 8333 + #define VCN_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL 8334 + //VCN_MES_INSTR_PNTR 8335 + #define VCN_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 8336 + #define VCN_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL 8337 + //VCN_MES_MSCRATCH_HI 8338 + #define VCN_MES_MSCRATCH_HI__DATA__SHIFT 0x0 8339 + #define VCN_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL 8340 + //VCN_MES_MSCRATCH_LO 8341 + #define VCN_MES_MSCRATCH_LO__DATA__SHIFT 0x0 8342 + #define VCN_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL 8343 + //VCN_MES_MSTATUS_LO 8344 + #define VCN_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 8345 + #define VCN_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL 8346 + //VCN_MES_MSTATUS_HI 8347 + #define VCN_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 8348 + #define VCN_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL 8349 + //VCN_MES_MEPC_LO 8350 + #define VCN_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 8351 + #define VCN_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL 8352 + //VCN_MES_MEPC_HI 8353 + #define VCN_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 8354 + #define VCN_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL 8355 + //VCN_MES_MCAUSE_LO 8356 + #define VCN_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 8357 + #define VCN_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL 8358 + //VCN_MES_MCAUSE_HI 8359 + #define VCN_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 8360 + #define VCN_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL 8361 + //VCN_MES_MBADADDR_LO 8362 + #define VCN_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 8363 + #define VCN_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL 8364 + //VCN_MES_MBADADDR_HI 8365 + #define VCN_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 8366 + #define VCN_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL 8367 + //VCN_MES_MIP_LO 8368 + #define VCN_MES_MIP_LO__MIP_LO__SHIFT 0x0 8369 + #define VCN_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL 8370 + //VCN_MES_MIP_HI 8371 + #define VCN_MES_MIP_HI__MIP_HI__SHIFT 0x0 8372 + #define VCN_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL 8373 + //VCN_MES_IC_OP_CNTL 8374 + #define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 8375 + #define VCN_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 8376 + #define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 8377 + #define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L 8378 + #define VCN_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L 8379 + #define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L 8380 + //VCN_MES_MCYCLE_LO 8381 + #define VCN_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 8382 + #define VCN_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL 8383 + //VCN_MES_MCYCLE_HI 8384 + #define VCN_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 8385 + #define VCN_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL 8386 + //VCN_MES_MTIME_LO 8387 + #define VCN_MES_MTIME_LO__TIME_LO__SHIFT 0x0 8388 + #define VCN_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL 8389 + //VCN_MES_MTIME_HI 8390 + #define VCN_MES_MTIME_HI__TIME_HI__SHIFT 0x0 8391 + #define VCN_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL 8392 + //VCN_MES_MINSTRET_LO 8393 + #define VCN_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 8394 + #define VCN_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL 8395 + //VCN_MES_MINSTRET_HI 8396 + #define VCN_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 8397 + #define VCN_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL 8398 + //VCN_MES_MISA_LO 8399 + #define VCN_MES_MISA_LO__MISA_LO__SHIFT 0x0 8400 + #define VCN_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL 8401 + //VCN_MES_MISA_HI 8402 + #define VCN_MES_MISA_HI__MISA_HI__SHIFT 0x0 8403 + #define VCN_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL 8404 + //VCN_MES_MVENDORID_LO 8405 + #define VCN_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 8406 + #define VCN_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL 8407 + //VCN_MES_MVENDORID_HI 8408 + #define VCN_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 8409 + #define VCN_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL 8410 + //VCN_MES_MARCHID_LO 8411 + #define VCN_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 8412 + #define VCN_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL 8413 + //VCN_MES_MARCHID_HI 8414 + #define VCN_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 8415 + #define VCN_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL 8416 + //VCN_MES_MIMPID_LO 8417 + #define VCN_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 8418 + #define VCN_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL 8419 + //VCN_MES_MIMPID_HI 8420 + #define VCN_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 8421 + #define VCN_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL 8422 + //VCN_MES_MHARTID_LO 8423 + #define VCN_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 8424 + #define VCN_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL 8425 + //VCN_MES_MHARTID_HI 8426 + #define VCN_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 8427 + #define VCN_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL 8428 + //VCN_MES_DC_BASE_CNTL 8429 + #define VCN_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 8430 + #define VCN_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 8431 + #define VCN_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL 8432 + #define VCN_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L 8433 + //VCN_MES_DC_OP_CNTL 8434 + #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 8435 + #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 8436 + #define VCN_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 8437 + #define VCN_MES_DC_OP_CNTL__DEPRECATED__SHIFT 0x3 8438 + #define VCN_MES_DC_OP_CNTL__DEPRACATED__SHIFT 0x4 8439 + #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L 8440 + #define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L 8441 + #define VCN_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L 8442 + #define VCN_MES_DC_OP_CNTL__DEPRECATED_MASK 0x00000008L 8443 + #define VCN_MES_DC_OP_CNTL__DEPRACATED_MASK 0x00000010L 8444 + //VCN_MES_MTIMECMP_LO 8445 + #define VCN_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 8446 + #define VCN_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL 8447 + //VCN_MES_MTIMECMP_HI 8448 + #define VCN_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 8449 + #define VCN_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL 8450 + //VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR 8451 + #define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 8452 + #define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR__INSTR_PNTR_MASK 0xFFFFFFFFL 8453 + //VCN_MES_GP0_LO 8454 + #define VCN_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 8455 + #define VCN_MES_GP0_LO__DATA__SHIFT 0x1 8456 + #define VCN_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L 8457 + #define VCN_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL 8458 + //VCN_MES_GP0_HI 8459 + #define VCN_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 8460 + #define VCN_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL 8461 + //VCN_MES_GP1_LO 8462 + #define VCN_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 8463 + #define VCN_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL 8464 + //VCN_MES_GP1_HI 8465 + #define VCN_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 8466 + #define VCN_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL 8467 + //VCN_MES_GP2_LO 8468 + #define VCN_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 8469 + #define VCN_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL 8470 + //VCN_MES_GP2_HI 8471 + #define VCN_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 8472 + #define VCN_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL 8473 + //VCN_MES_GP3_LO 8474 + #define VCN_MES_GP3_LO__DATA__SHIFT 0x0 8475 + #define VCN_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL 8476 + //VCN_MES_GP3_HI 8477 + #define VCN_MES_GP3_HI__DATA__SHIFT 0x0 8478 + #define VCN_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL 8479 + //VCN_MES_GP4_LO 8480 + #define VCN_MES_GP4_LO__DATA__SHIFT 0x0 8481 + #define VCN_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL 8482 + //VCN_MES_GP4_HI 8483 + #define VCN_MES_GP4_HI__DATA__SHIFT 0x0 8484 + #define VCN_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL 8485 + //VCN_MES_GP5_LO 8486 + #define VCN_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 8487 + #define VCN_MES_GP5_LO__DATA__SHIFT 0x1 8488 + #define VCN_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L 8489 + #define VCN_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL 8490 + //VCN_MES_GP5_HI 8491 + #define VCN_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 8492 + #define VCN_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL 8493 + //VCN_MES_GP6_LO 8494 + #define VCN_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 8495 + #define VCN_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL 8496 + //VCN_MES_GP6_HI 8497 + #define VCN_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 8498 + #define VCN_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL 8499 + //VCN_MES_GP7_LO 8500 + #define VCN_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 8501 + #define VCN_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL 8502 + //VCN_MES_GP7_HI 8503 + #define VCN_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 8504 + #define VCN_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL 8505 + //VCN_MES_GP8_LO 8506 + #define VCN_MES_GP8_LO__DATA__SHIFT 0x0 8507 + #define VCN_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL 8508 + //VCN_MES_GP8_HI 8509 + #define VCN_MES_GP8_HI__DATA__SHIFT 0x0 8510 + #define VCN_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL 8511 + //VCN_MES_GP9_LO 8512 + #define VCN_MES_GP9_LO__DATA__SHIFT 0x0 8513 + #define VCN_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL 8514 + //VCN_MES_GP9_HI 8515 + #define VCN_MES_GP9_HI__DATA__SHIFT 0x0 8516 + #define VCN_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL 8517 + //VCN_MES_DM_INDEX_ADDR 8518 + #define VCN_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 8519 + #define VCN_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL 8520 + //VCN_MES_DM_INDEX_DATA 8521 + #define VCN_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 8522 + #define VCN_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL 8523 + //VCN_MES_DBG_FROM_RST 8524 + #define VCN_MES_DBG_FROM_RST__CONTROL__SHIFT 0x0 8525 + #define VCN_MES_DBG_FROM_RST__CONTROL_MASK 0x00000001L 8526 + //VCN_MES_LOCAL_BASE0_LO 8527 + #define VCN_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 8528 + #define VCN_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L 8529 + //VCN_MES_LOCAL_BASE0_HI 8530 + #define VCN_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 8531 + #define VCN_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL 8532 + //VCN_MES_LOCAL_MASK0_LO 8533 + #define VCN_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 8534 + #define VCN_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L 8535 + //VCN_MES_LOCAL_MASK0_HI 8536 + #define VCN_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 8537 + #define VCN_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL 8538 + //VCN_MES_LOCAL_APERTURE 8539 + #define VCN_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 8540 + #define VCN_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L 8541 + //VCN_MES_LOCAL_INSTR_BASE_LO 8542 + #define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 8543 + #define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L 8544 + //VCN_MES_LOCAL_INSTR_BASE_HI 8545 + #define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 8546 + #define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL 8547 + //VCN_MES_LOCAL_INSTR_MASK_LO 8548 + #define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 8549 + #define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L 8550 + //VCN_MES_LOCAL_INSTR_MASK_HI 8551 + #define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 8552 + #define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL 8553 + //VCN_MES_LOCAL_INSTR_APERTURE 8554 + #define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 8555 + #define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L 8556 + //VCN_MES_LOCAL_SCRATCH_APERTURE 8557 + #define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 8558 + #define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L 8559 + //VCN_MES_LOCAL_SCRATCH_BASE_LO 8560 + #define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 8561 + #define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L 8562 + //VCN_MES_LOCAL_SCRATCH_BASE_HI 8563 + #define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 8564 + #define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL 8565 + //VCN_MES_PERFCOUNT_CNTL 8566 + #define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 8567 + #define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL 8568 + //VCN_MES_PENDING_INTERRUPT 8569 + #define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 8570 + #define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL 8571 + //VCN_MES_PRIV_LEVEL 8572 + #define VCN_MES_PRIV_LEVEL__PRIV_LEVEL__SHIFT 0x0 8573 + #define VCN_MES_PRIV_LEVEL__GRBM_PRIV_LEVEL__SHIFT 0x1 8574 + #define VCN_MES_PRIV_LEVEL__PRIV_LEVEL_MASK 0x00000001L 8575 + #define VCN_MES_PRIV_LEVEL__GRBM_PRIV_LEVEL_MASK 0x00000002L 8576 + //VCN_MES_PRIV_LEVEL_VIOLATION_STATUS 8577 + #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OCCURRED__SHIFT 0x0 8578 + #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OP__SHIFT 0x1 8579 + #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_ADDR__SHIFT 0x2 8580 + #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_APERTURE__SHIFT 0x16 8581 + #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OCCURRED_MASK 0x00000001L 8582 + #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OP_MASK 0x00000002L 8583 + #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_ADDR_MASK 0x003FFFFCL 8584 + #define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_APERTURE_MASK 0x01C00000L 8585 + //VCN_MES_PRGRM_CNTR_START_HI 8586 + #define VCN_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 8587 + #define VCN_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL 8588 + //VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI 8589 + #define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI__INSTR_PNTR__SHIFT 0x0 8590 + #define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI__INSTR_PNTR_MASK 0x3FFFFFFFL 8591 + //VCN_MES_INTERRUPT_DATA_16 8592 + #define VCN_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0 8593 + #define VCN_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL 8594 + //VCN_MES_INTERRUPT_DATA_17 8595 + #define VCN_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0 8596 + #define VCN_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL 8597 + //VCN_MES_INTERRUPT_DATA_18 8598 + #define VCN_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0 8599 + #define VCN_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL 8600 + //VCN_MES_INTERRUPT_DATA_19 8601 + #define VCN_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0 8602 + #define VCN_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL 8603 + //VCN_MES_INTERRUPT_DATA_20 8604 + #define VCN_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0 8605 + #define VCN_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL 8606 + //VCN_MES_INTERRUPT_DATA_21 8607 + #define VCN_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0 8608 + #define VCN_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL 8609 + //VCN_MES_INTERRUPT_DATA_22 8610 + #define VCN_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0 8611 + #define VCN_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL 8612 + //VCN_MES_INTERRUPT_DATA_23 8613 + #define VCN_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0 8614 + #define VCN_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL 8615 + //VCN_MES_INTERRUPT_DATA_24 8616 + #define VCN_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0 8617 + #define VCN_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL 8618 + //VCN_MES_INTERRUPT_DATA_25 8619 + #define VCN_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0 8620 + #define VCN_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL 8621 + //VCN_MES_INTERRUPT_DATA_26 8622 + #define VCN_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0 8623 + #define VCN_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL 8624 + //VCN_MES_INTERRUPT_DATA_27 8625 + #define VCN_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0 8626 + #define VCN_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL 8627 + //VCN_MES_INTERRUPT_DATA_28 8628 + #define VCN_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0 8629 + #define VCN_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL 8630 + //VCN_MES_INTERRUPT_DATA_29 8631 + #define VCN_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0 8632 + #define VCN_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL 8633 + //VCN_MES_INTERRUPT_DATA_30 8634 + #define VCN_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0 8635 + #define VCN_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL 8636 + //VCN_MES_INTERRUPT_DATA_31 8637 + #define VCN_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0 8638 + #define VCN_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL 8639 + //VCN_MES_DC_APERTURE0_BASE 8640 + #define VCN_MES_DC_APERTURE0_BASE__BASE__SHIFT 0x0 8641 + #define VCN_MES_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL 8642 + //VCN_MES_DC_APERTURE0_MASK 8643 + #define VCN_MES_DC_APERTURE0_MASK__MASK__SHIFT 0x0 8644 + #define VCN_MES_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL 8645 + //VCN_MES_DC_APERTURE0_CNTL 8646 + #define VCN_MES_DC_APERTURE0_CNTL__VMID__SHIFT 0x0 8647 + #define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4 8648 + #define VCN_MES_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL 8649 + #define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L 8650 + //VCN_MES_DC_APERTURE1_BASE 8651 + #define VCN_MES_DC_APERTURE1_BASE__BASE__SHIFT 0x0 8652 + #define VCN_MES_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL 8653 + //VCN_MES_DC_APERTURE1_MASK 8654 + #define VCN_MES_DC_APERTURE1_MASK__MASK__SHIFT 0x0 8655 + #define VCN_MES_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL 8656 + //VCN_MES_DC_APERTURE1_CNTL 8657 + #define VCN_MES_DC_APERTURE1_CNTL__VMID__SHIFT 0x0 8658 + #define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4 8659 + #define VCN_MES_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL 8660 + #define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L 8661 + //VCN_MES_DC_APERTURE2_BASE 8662 + #define VCN_MES_DC_APERTURE2_BASE__BASE__SHIFT 0x0 8663 + #define VCN_MES_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL 8664 + //VCN_MES_DC_APERTURE2_MASK 8665 + #define VCN_MES_DC_APERTURE2_MASK__MASK__SHIFT 0x0 8666 + #define VCN_MES_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL 8667 + //VCN_MES_DC_APERTURE2_CNTL 8668 + #define VCN_MES_DC_APERTURE2_CNTL__VMID__SHIFT 0x0 8669 + #define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4 8670 + #define VCN_MES_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL 8671 + #define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L 8672 + //VCN_MES_DC_APERTURE3_BASE 8673 + #define VCN_MES_DC_APERTURE3_BASE__BASE__SHIFT 0x0 8674 + #define VCN_MES_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL 8675 + //VCN_MES_DC_APERTURE3_MASK 8676 + #define VCN_MES_DC_APERTURE3_MASK__MASK__SHIFT 0x0 8677 + #define VCN_MES_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL 8678 + //VCN_MES_DC_APERTURE3_CNTL 8679 + #define VCN_MES_DC_APERTURE3_CNTL__VMID__SHIFT 0x0 8680 + #define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4 8681 + #define VCN_MES_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL 8682 + #define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L 8683 + //VCN_MES_DC_APERTURE4_BASE 8684 + #define VCN_MES_DC_APERTURE4_BASE__BASE__SHIFT 0x0 8685 + #define VCN_MES_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL 8686 + //VCN_MES_DC_APERTURE4_MASK 8687 + #define VCN_MES_DC_APERTURE4_MASK__MASK__SHIFT 0x0 8688 + #define VCN_MES_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL 8689 + //VCN_MES_DC_APERTURE4_CNTL 8690 + #define VCN_MES_DC_APERTURE4_CNTL__VMID__SHIFT 0x0 8691 + #define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4 8692 + #define VCN_MES_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL 8693 + #define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L 8694 + //VCN_MES_DC_APERTURE5_BASE 8695 + #define VCN_MES_DC_APERTURE5_BASE__BASE__SHIFT 0x0 8696 + #define VCN_MES_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL 8697 + //VCN_MES_DC_APERTURE5_MASK 8698 + #define VCN_MES_DC_APERTURE5_MASK__MASK__SHIFT 0x0 8699 + #define VCN_MES_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL 8700 + //VCN_MES_DC_APERTURE5_CNTL 8701 + #define VCN_MES_DC_APERTURE5_CNTL__VMID__SHIFT 0x0 8702 + #define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4 8703 + #define VCN_MES_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL 8704 + #define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L 8705 + //VCN_MES_DC_APERTURE6_BASE 8706 + #define VCN_MES_DC_APERTURE6_BASE__BASE__SHIFT 0x0 8707 + #define VCN_MES_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL 8708 + //VCN_MES_DC_APERTURE6_MASK 8709 + #define VCN_MES_DC_APERTURE6_MASK__MASK__SHIFT 0x0 8710 + #define VCN_MES_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL 8711 + //VCN_MES_DC_APERTURE6_CNTL 8712 + #define VCN_MES_DC_APERTURE6_CNTL__VMID__SHIFT 0x0 8713 + #define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4 8714 + #define VCN_MES_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL 8715 + #define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L 8716 + //VCN_MES_DC_APERTURE7_BASE 8717 + #define VCN_MES_DC_APERTURE7_BASE__BASE__SHIFT 0x0 8718 + #define VCN_MES_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL 8719 + //VCN_MES_DC_APERTURE7_MASK 8720 + #define VCN_MES_DC_APERTURE7_MASK__MASK__SHIFT 0x0 8721 + #define VCN_MES_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL 8722 + //VCN_MES_DC_APERTURE7_CNTL 8723 + #define VCN_MES_DC_APERTURE7_CNTL__VMID__SHIFT 0x0 8724 + #define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4 8725 + #define VCN_MES_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL 8726 + #define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L 8727 + //VCN_MES_DC_APERTURE8_BASE 8728 + #define VCN_MES_DC_APERTURE8_BASE__BASE__SHIFT 0x0 8729 + #define VCN_MES_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL 8730 + //VCN_MES_DC_APERTURE8_MASK 8731 + #define VCN_MES_DC_APERTURE8_MASK__MASK__SHIFT 0x0 8732 + #define VCN_MES_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL 8733 + //VCN_MES_DC_APERTURE8_CNTL 8734 + #define VCN_MES_DC_APERTURE8_CNTL__VMID__SHIFT 0x0 8735 + #define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4 8736 + #define VCN_MES_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL 8737 + #define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L 8738 + //VCN_MES_DC_APERTURE9_BASE 8739 + #define VCN_MES_DC_APERTURE9_BASE__BASE__SHIFT 0x0 8740 + #define VCN_MES_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL 8741 + //VCN_MES_DC_APERTURE9_MASK 8742 + #define VCN_MES_DC_APERTURE9_MASK__MASK__SHIFT 0x0 8743 + #define VCN_MES_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL 8744 + //VCN_MES_DC_APERTURE9_CNTL 8745 + #define VCN_MES_DC_APERTURE9_CNTL__VMID__SHIFT 0x0 8746 + #define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4 8747 + #define VCN_MES_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL 8748 + #define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L 8749 + //VCN_MES_DC_APERTURE10_BASE 8750 + #define VCN_MES_DC_APERTURE10_BASE__BASE__SHIFT 0x0 8751 + #define VCN_MES_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL 8752 + //VCN_MES_DC_APERTURE10_MASK 8753 + #define VCN_MES_DC_APERTURE10_MASK__MASK__SHIFT 0x0 8754 + #define VCN_MES_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL 8755 + //VCN_MES_DC_APERTURE10_CNTL 8756 + #define VCN_MES_DC_APERTURE10_CNTL__VMID__SHIFT 0x0 8757 + #define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4 8758 + #define VCN_MES_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL 8759 + #define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L 8760 + //VCN_MES_DC_APERTURE11_BASE 8761 + #define VCN_MES_DC_APERTURE11_BASE__BASE__SHIFT 0x0 8762 + #define VCN_MES_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL 8763 + //VCN_MES_DC_APERTURE11_MASK 8764 + #define VCN_MES_DC_APERTURE11_MASK__MASK__SHIFT 0x0 8765 + #define VCN_MES_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL 8766 + //VCN_MES_DC_APERTURE11_CNTL 8767 + #define VCN_MES_DC_APERTURE11_CNTL__VMID__SHIFT 0x0 8768 + #define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4 8769 + #define VCN_MES_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL 8770 + #define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L 8771 + //VCN_MES_DC_APERTURE12_BASE 8772 + #define VCN_MES_DC_APERTURE12_BASE__BASE__SHIFT 0x0 8773 + #define VCN_MES_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL 8774 + //VCN_MES_DC_APERTURE12_MASK 8775 + #define VCN_MES_DC_APERTURE12_MASK__MASK__SHIFT 0x0 8776 + #define VCN_MES_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL 8777 + //VCN_MES_DC_APERTURE12_CNTL 8778 + #define VCN_MES_DC_APERTURE12_CNTL__VMID__SHIFT 0x0 8779 + #define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4 8780 + #define VCN_MES_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL 8781 + #define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L 8782 + //VCN_MES_DC_APERTURE13_BASE 8783 + #define VCN_MES_DC_APERTURE13_BASE__BASE__SHIFT 0x0 8784 + #define VCN_MES_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL 8785 + //VCN_MES_DC_APERTURE13_MASK 8786 + #define VCN_MES_DC_APERTURE13_MASK__MASK__SHIFT 0x0 8787 + #define VCN_MES_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL 8788 + //VCN_MES_DC_APERTURE13_CNTL 8789 + #define VCN_MES_DC_APERTURE13_CNTL__VMID__SHIFT 0x0 8790 + #define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4 8791 + #define VCN_MES_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL 8792 + #define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L 8793 + //VCN_MES_DC_APERTURE14_BASE 8794 + #define VCN_MES_DC_APERTURE14_BASE__BASE__SHIFT 0x0 8795 + #define VCN_MES_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL 8796 + //VCN_MES_DC_APERTURE14_MASK 8797 + #define VCN_MES_DC_APERTURE14_MASK__MASK__SHIFT 0x0 8798 + #define VCN_MES_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL 8799 + //VCN_MES_DC_APERTURE14_CNTL 8800 + #define VCN_MES_DC_APERTURE14_CNTL__VMID__SHIFT 0x0 8801 + #define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4 8802 + #define VCN_MES_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL 8803 + #define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L 8804 + //VCN_MES_DC_APERTURE15_BASE 8805 + #define VCN_MES_DC_APERTURE15_BASE__BASE__SHIFT 0x0 8806 + #define VCN_MES_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL 8807 + //VCN_MES_DC_APERTURE15_MASK 8808 + #define VCN_MES_DC_APERTURE15_MASK__MASK__SHIFT 0x0 8809 + #define VCN_MES_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL 8810 + //VCN_MES_DC_APERTURE15_CNTL 8811 + #define VCN_MES_DC_APERTURE15_CNTL__VMID__SHIFT 0x0 8812 + #define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4 8813 + #define VCN_MES_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL 8814 + #define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L 8815 + 8816 + //VCN_HYP_ME1_PIPE0_VMID_CNTL 8817 + #define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_ALLOWED_MASK__SHIFT 0x0 8818 + #define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_DEFAULT__SHIFT 0x10 8819 + #define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_ALLOWED_MASK_MASK 0x0000FFFFL 8820 + #define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_DEFAULT_MASK 0x000F0000L 8821 + //VCN_HYP_ME1_PIPE1_VMID_CNTL 8822 + #define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_ALLOWED_MASK__SHIFT 0x0 8823 + #define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_DEFAULT__SHIFT 0x10 8824 + #define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_ALLOWED_MASK_MASK 0x0000FFFFL 8825 + #define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_DEFAULT_MASK 0x000F0000L 8826 + //VCN_MES_IC_BASE_LO 8827 + #define VCN_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc 8828 + #define VCN_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L 8829 + //VCN_MES_MIBASE_LO 8830 + #define VCN_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc 8831 + #define VCN_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L 8832 + //VCN_MES_IC_BASE_HI 8833 + #define VCN_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 8834 + #define VCN_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL 8835 + //VCN_MES_MIBASE_HI 8836 + #define VCN_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 8837 + #define VCN_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL 8838 + //VCN_MES_IC_BASE_CNTL 8839 + #define VCN_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 8840 + #define VCN_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 8841 + #define VCN_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 8842 + #define VCN_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL 8843 + #define VCN_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L 8844 + #define VCN_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L 8845 + //VCN_MES_DC_BASE_LO 8846 + #define VCN_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 8847 + #define VCN_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L 8848 + //VCN_MES_MDBASE_LO 8849 + #define VCN_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 8850 + #define VCN_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L 8851 + //VCN_MES_DC_BASE_HI 8852 + #define VCN_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 8853 + #define VCN_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL 8854 + //VCN_MES_MDBASE_HI 8855 + #define VCN_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 8856 + #define VCN_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL 8857 + //VCN_MES_MIBOUND_LO 8858 + #define VCN_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 8859 + #define VCN_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL 8860 + //VCN_MES_MIBOUND_HI 8861 + #define VCN_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 8862 + #define VCN_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL 8863 + //VCN_MES_MDBOUND_LO 8864 + #define VCN_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 8865 + #define VCN_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL 8866 + //VCN_MES_MDBOUND_HI 8867 + #define VCN_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 8868 + #define VCN_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL 8121 8869 8122 8870 #endif