Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: Merge up fixes
Merge branch 'for-6.11' of
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into
asoc-6.12 for some AMD work.
+70
-25
-1
MAINTAINERS
-1
MAINTAINERS
···
18526
18526
18527
18527
QCOM AUDIO (ASoC) DRIVERS
18528
18528
M: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18529
-
M: Banajit Goswami <bgoswami@quicinc.com>
18530
18529
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
18531
18530
L: linux-arm-msm@vger.kernel.org
18532
18531
S: Supported
+2
sound/soc/amd/acp/acp-legacy-mach.c
+2
sound/soc/amd/acp/acp-legacy-mach.c
+6
sound/soc/codecs/lpass-macro-common.h
+6
sound/soc/codecs/lpass-macro-common.h
···
49
49
static inline const char *lpass_macro_get_codec_version_string(int version)
50
50
{
51
51
switch (version) {
52
+
case LPASS_CODEC_VERSION_1_0:
53
+
return "v1.0";
54
+
case LPASS_CODEC_VERSION_1_1:
55
+
return "v1.1";
56
+
case LPASS_CODEC_VERSION_1_2:
57
+
return "v1.2";
52
58
case LPASS_CODEC_VERSION_2_0:
53
59
return "v2.0";
54
60
case LPASS_CODEC_VERSION_2_1:
+4
sound/soc/codecs/lpass-va-macro.c
+4
sound/soc/codecs/lpass-va-macro.c
···
1485
1485
if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x80 || core_id_2 == 0x81))
1486
1486
version = LPASS_CODEC_VERSION_2_8;
1487
1487
1488
+
if (version == LPASS_CODEC_VERSION_UNKNOWN)
1489
+
dev_warn(va->dev, "Unknown Codec version, ID: %02x / %02x / %02x\n",
1490
+
core_id_0, core_id_1, core_id_2);
1491
+
1488
1492
lpass_macro_set_codec_version(version);
1489
1493
1490
1494
dev_dbg(va->dev, "LPASS Codec Version %s\n", lpass_macro_get_codec_version_string(version));
+2
-3
sound/soc/codecs/wcd937x.c
+2
-3
sound/soc/codecs/wcd937x.c
+1
sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
+1
sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
+4
-2
sound/soc/sof/amd/acp-dsp-offset.h
+4
-2
sound/soc/sof/amd/acp-dsp-offset.h
···
76
76
#define DSP_SW_INTR_CNTL_OFFSET 0x0
77
77
#define DSP_SW_INTR_STAT_OFFSET 0x4
78
78
#define DSP_SW_INTR_TRIG_OFFSET 0x8
79
-
#define ACP_ERROR_STATUS 0x18C4
79
+
#define ACP3X_ERROR_STATUS 0x18C4
80
+
#define ACP6X_ERROR_STATUS 0x1A4C
80
81
#define ACP3X_AXI2DAGB_SEM_0 0x1880
81
82
#define ACP5X_AXI2DAGB_SEM_0 0x1884
82
83
#define ACP6X_AXI2DAGB_SEM_0 0x1874
83
84
84
85
/* ACP common registers to report errors related to I2S & SoundWire interfaces */
85
-
#define ACP_SW0_I2S_ERROR_REASON 0x18B4
86
+
#define ACP3X_SW_I2S_ERROR_REASON 0x18C8
87
+
#define ACP6X_SW0_I2S_ERROR_REASON 0x18B4
86
88
#define ACP_SW1_I2S_ERROR_REASON 0x1A50
87
89
88
90
/* Registers from ACP_SHA block */
+35
-17
sound/soc/sof/amd/acp.c
+35
-17
sound/soc/sof/amd/acp.c
···
92
92
unsigned int idx, unsigned int dscr_count)
93
93
{
94
94
struct snd_sof_dev *sdev = adata->dev;
95
+
const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
95
96
unsigned int val, status;
96
97
int ret;
97
98
···
103
102
val & (1 << ch), ACP_REG_POLL_INTERVAL,
104
103
ACP_REG_POLL_TIMEOUT_US);
105
104
if (ret < 0) {
106
-
status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS);
105
+
status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);
107
106
val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
108
107
109
108
dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
···
264
263
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);
265
264
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);
266
265
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);
266
+
267
+
/* psp_send_cmd only required for vangogh platform (rev - 5) */
268
+
if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) {
269
+
/* Modify IRAM and DRAM size */
270
+
ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2);
271
+
if (ret)
272
+
return ret;
273
+
ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG);
274
+
if (ret)
275
+
return ret;
276
+
}
267
277
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);
268
278
269
279
ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,
···
288
276
/* psp_send_cmd only required for renoir platform (rev - 3) */
289
277
if (desc->rev == 3) {
290
278
ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND);
291
-
if (ret)
292
-
return ret;
293
-
}
294
-
295
-
/* psp_send_cmd only required for vangogh platform (rev - 5) */
296
-
if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) {
297
-
/* Modify IRAM and DRAM size */
298
-
ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2);
299
-
if (ret)
300
-
return ret;
301
-
ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG);
302
279
if (ret)
303
280
return ret;
304
281
}
···
403
402
404
403
if (val & ACP_ERROR_IRQ_MASK) {
405
404
snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK);
406
-
snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW0_I2S_ERROR_REASON, 0);
407
-
snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW1_I2S_ERROR_REASON, 0);
408
-
snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_ERROR_STATUS, 0);
405
+
snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0);
406
+
/* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */
407
+
if (desc->rev >= 6)
408
+
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0);
409
+
snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0);
409
410
irq_flag = 1;
410
411
}
411
412
···
433
430
const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
434
431
unsigned int base = desc->pgfsm_base;
435
432
unsigned int val;
433
+
unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask;
436
434
int ret;
437
435
438
436
val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);
···
441
437
if (val == ACP_POWERED_ON)
442
438
return 0;
443
439
444
-
if (val & ACP_PGFSM_STATUS_MASK)
440
+
switch (desc->rev) {
441
+
case 3:
442
+
case 5:
443
+
acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK;
444
+
acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK;
445
+
break;
446
+
case 6:
447
+
acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;
448
+
acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;
449
+
break;
450
+
default:
451
+
return -EINVAL;
452
+
}
453
+
454
+
if (val & acp_pgfsm_status_mask)
445
455
snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
446
-
ACP_PGFSM_CNTL_POWER_ON_MASK);
456
+
acp_pgfsm_cntl_mask);
447
457
448
458
ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
449
459
!val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
+7
-2
sound/soc/sof/amd/acp.h
+7
-2
sound/soc/sof/amd/acp.h
···
25
25
#define ACP_REG_POLL_TIMEOUT_US 2000
26
26
#define ACP_DMA_COMPLETE_TIMEOUT_US 5000
27
27
28
-
#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
29
-
#define ACP_PGFSM_STATUS_MASK 0x03
28
+
#define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01
29
+
#define ACP3X_PGFSM_STATUS_MASK 0x03
30
+
#define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07
31
+
#define ACP6X_PGFSM_STATUS_MASK 0x0F
32
+
30
33
#define ACP_POWERED_ON 0x00
31
34
#define ACP_ASSERT_RESET 0x01
32
35
#define ACP_RELEASE_RESET 0x00
···
206
203
u32 probe_reg_offset;
207
204
u32 reg_start_addr;
208
205
u32 reg_end_addr;
206
+
u32 acp_error_stat;
207
+
u32 acp_sw0_i2s_err_reason;
209
208
u32 sdw_max_link_count;
210
209
u64 sdw_acpi_dev_addr;
211
210
};
+2
sound/soc/sof/amd/pci-acp63.c
+2
sound/soc/sof/amd/pci-acp63.c
···
35
35
.ext_intr_cntl = ACP6X_EXTERNAL_INTR_CNTL,
36
36
.ext_intr_stat = ACP6X_EXT_INTR_STAT,
37
37
.ext_intr_stat1 = ACP6X_EXT_INTR_STAT1,
38
+
.acp_error_stat = ACP6X_ERROR_STATUS,
39
+
.acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON,
38
40
.dsp_intr_base = ACP6X_DSP_SW_INTR_BASE,
39
41
.sram_pte_offset = ACP6X_SRAM_PTE_OFFSET,
40
42
.hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0,
+2
sound/soc/sof/amd/pci-rmb.c
+2
sound/soc/sof/amd/pci-rmb.c
···
33
33
.pgfsm_base = ACP6X_PGFSM_BASE,
34
34
.ext_intr_stat = ACP6X_EXT_INTR_STAT,
35
35
.dsp_intr_base = ACP6X_DSP_SW_INTR_BASE,
36
+
.acp_error_stat = ACP6X_ERROR_STATUS,
37
+
.acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON,
36
38
.sram_pte_offset = ACP6X_SRAM_PTE_OFFSET,
37
39
.hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0,
38
40
.fusion_dsp_offset = ACP6X_DSP_FUSION_RUNSTALL,
+2
sound/soc/sof/amd/pci-rn.c
+2
sound/soc/sof/amd/pci-rn.c
···
33
33
.pgfsm_base = ACP3X_PGFSM_BASE,
34
34
.ext_intr_stat = ACP3X_EXT_INTR_STAT,
35
35
.dsp_intr_base = ACP3X_DSP_SW_INTR_BASE,
36
+
.acp_error_stat = ACP3X_ERROR_STATUS,
37
+
.acp_sw0_i2s_err_reason = ACP3X_SW_I2S_ERROR_REASON,
36
38
.sram_pte_offset = ACP3X_SRAM_PTE_OFFSET,
37
39
.hw_semaphore_offset = ACP3X_AXI2DAGB_SEM_0,
38
40
.acp_clkmux_sel = ACP3X_CLKMUX_SEL,
+3
sound/soc/sof/mediatek/mt8195/mt8195.c
+3
sound/soc/sof/mediatek/mt8195/mt8195.c
···
575
575
.compatible = "google,tomato",
576
576
.sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682.tplg"
577
577
}, {
578
+
.compatible = "google,dojo",
579
+
.sof_tplg_filename = "sof-mt8195-mt6359-max98390-rt5682.tplg"
580
+
}, {
578
581
.compatible = "mediatek,mt8195",
579
582
.sof_tplg_filename = "sof-mt8195.tplg"
580
583
}, {