Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm: don't set the signal blocker on the master process.
drm: don't call the vblank tasklet with irqs disabled.
r300: Fix cliprect emit
drm/radeon: r300_cmdbuf: Always emit INDX_BUFFER immediately after DRAW_INDEX
radeon: fix some hard lockups on r3/4/500s
+225
-86
+12
-8
drivers/gpu/drm/drm_irq.c
+12
-8
drivers/gpu/drm/drm_irq.c
···
400
400
{
401
401
struct drm_device *dev = (struct drm_device *)data;
402
402
unsigned long irqflags;
403
-
403
+
void (*tasklet_func)(struct drm_device *);
404
+
404
405
spin_lock_irqsave(&dev->tasklet_lock, irqflags);
406
+
tasklet_func = dev->locked_tasklet_func;
407
+
spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
405
408
406
-
if (!dev->locked_tasklet_func ||
409
+
if (!tasklet_func ||
407
410
!drm_lock_take(&dev->lock,
408
411
DRM_KERNEL_CONTEXT)) {
409
-
spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
410
412
return;
411
413
}
412
414
413
415
dev->lock.lock_time = jiffies;
414
416
atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
415
417
416
-
dev->locked_tasklet_func(dev);
418
+
spin_lock_irqsave(&dev->tasklet_lock, irqflags);
419
+
tasklet_func = dev->locked_tasklet_func;
420
+
dev->locked_tasklet_func = NULL;
421
+
spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
422
+
423
+
if (tasklet_func != NULL)
424
+
tasklet_func(dev);
417
425
418
426
drm_lock_free(&dev->lock,
419
427
DRM_KERNEL_CONTEXT);
420
-
421
-
dev->locked_tasklet_func = NULL;
422
-
423
-
spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
424
428
}
425
429
426
430
/**
+18
-15
drivers/gpu/drm/drm_lock.c
+18
-15
drivers/gpu/drm/drm_lock.c
···
105
105
ret ? "interrupted" : "has lock");
106
106
if (ret) return ret;
107
107
108
-
sigemptyset(&dev->sigmask);
109
-
sigaddset(&dev->sigmask, SIGSTOP);
110
-
sigaddset(&dev->sigmask, SIGTSTP);
111
-
sigaddset(&dev->sigmask, SIGTTIN);
112
-
sigaddset(&dev->sigmask, SIGTTOU);
113
-
dev->sigdata.context = lock->context;
114
-
dev->sigdata.lock = dev->lock.hw_lock;
115
-
block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
108
+
/* don't set the block all signals on the master process for now
109
+
* really probably not the correct answer but lets us debug xkb
110
+
* xserver for now */
111
+
if (!file_priv->master) {
112
+
sigemptyset(&dev->sigmask);
113
+
sigaddset(&dev->sigmask, SIGSTOP);
114
+
sigaddset(&dev->sigmask, SIGTSTP);
115
+
sigaddset(&dev->sigmask, SIGTTIN);
116
+
sigaddset(&dev->sigmask, SIGTTOU);
117
+
dev->sigdata.context = lock->context;
118
+
dev->sigdata.lock = dev->lock.hw_lock;
119
+
block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
120
+
}
116
121
117
122
if (dev->driver->dma_ready && (lock->flags & _DRM_LOCK_READY))
118
123
dev->driver->dma_ready(dev);
···
155
150
{
156
151
struct drm_lock *lock = data;
157
152
unsigned long irqflags;
153
+
void (*tasklet_func)(struct drm_device *);
158
154
159
155
if (lock->context == DRM_KERNEL_CONTEXT) {
160
156
DRM_ERROR("Process %d using kernel context %d\n",
···
164
158
}
165
159
166
160
spin_lock_irqsave(&dev->tasklet_lock, irqflags);
167
-
168
-
if (dev->locked_tasklet_func) {
169
-
dev->locked_tasklet_func(dev);
170
-
171
-
dev->locked_tasklet_func = NULL;
172
-
}
173
-
161
+
tasklet_func = dev->locked_tasklet_func;
162
+
dev->locked_tasklet_func = NULL;
174
163
spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
164
+
if (tasklet_func != NULL)
165
+
tasklet_func(dev);
175
166
176
167
atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]);
177
168
+162
-34
drivers/gpu/drm/radeon/r300_cmdbuf.c
+162
-34
drivers/gpu/drm/radeon/r300_cmdbuf.c
···
77
77
return -EFAULT;
78
78
}
79
79
80
+
box.x2--; /* Hardware expects inclusive bottom-right corner */
81
+
box.y2--;
82
+
80
83
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
81
84
box.x1 = (box.x1) &
82
85
R300_CLIPRECT_MASK;
···
98
95
R300_CLIPRECT_MASK;
99
96
box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) &
100
97
R300_CLIPRECT_MASK;
101
-
102
98
}
99
+
103
100
OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
104
101
(box.y1 << R300_CLIPRECT_Y_SHIFT));
105
102
OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
···
139
136
ADVANCE_RING();
140
137
}
141
138
139
+
/* flus cache and wait idle clean after cliprect change */
140
+
BEGIN_RING(2);
141
+
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
142
+
OUT_RING(R300_RB3D_DC_FLUSH);
143
+
ADVANCE_RING();
144
+
BEGIN_RING(2);
145
+
OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
146
+
OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
147
+
ADVANCE_RING();
148
+
/* set flush flag */
149
+
dev_priv->track_flush |= RADEON_FLUSH_EMITED;
150
+
142
151
return 0;
143
152
}
144
153
···
181
166
ADD_RANGE(0x21DC, 1);
182
167
ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
183
168
ADD_RANGE(R300_VAP_CLIP_X_0, 4);
184
-
ADD_RANGE(R300_VAP_PVS_WAITIDLE, 1);
169
+
ADD_RANGE(R300_VAP_PVS_STATE_FLUSH_REG, 1);
185
170
ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
186
171
ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
187
172
ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
188
173
ADD_RANGE(R300_GB_ENABLE, 1);
189
174
ADD_RANGE(R300_GB_MSPOS0, 5);
190
-
ADD_RANGE(R300_TX_CNTL, 1);
175
+
ADD_RANGE(R300_TX_INVALTAGS, 1);
191
176
ADD_RANGE(R300_TX_ENABLE, 1);
192
177
ADD_RANGE(0x4200, 4);
193
178
ADD_RANGE(0x4214, 1);
···
403
388
if (sz * 16 > cmdbuf->bufsz)
404
389
return -EINVAL;
405
390
406
-
BEGIN_RING(5 + sz * 4);
407
-
/* Wait for VAP to come to senses.. */
408
-
/* there is no need to emit it multiple times, (only once before VAP is programmed,
409
-
but this optimization is for later */
410
-
OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0);
391
+
/* VAP is very sensitive so we purge cache before we program it
392
+
* and we also flush its state before & after */
393
+
BEGIN_RING(6);
394
+
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
395
+
OUT_RING(R300_RB3D_DC_FLUSH);
396
+
OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
397
+
OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
398
+
OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
399
+
OUT_RING(0);
400
+
ADVANCE_RING();
401
+
/* set flush flag */
402
+
dev_priv->track_flush |= RADEON_FLUSH_EMITED;
403
+
404
+
BEGIN_RING(3 + sz * 4);
411
405
OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
412
406
OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
413
407
OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
408
+
ADVANCE_RING();
414
409
410
+
BEGIN_RING(2);
411
+
OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
412
+
OUT_RING(0);
415
413
ADVANCE_RING();
416
414
417
415
cmdbuf->buf += sz * 16;
···
451
423
(1 << R300_PRIM_NUM_VERTICES_SHIFT));
452
424
OUT_RING_TABLE((int *)cmdbuf->buf, 8);
453
425
ADVANCE_RING();
426
+
427
+
BEGIN_RING(4);
428
+
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
429
+
OUT_RING(R300_RB3D_DC_FLUSH);
430
+
OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
431
+
OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
432
+
ADVANCE_RING();
433
+
/* set flush flag */
434
+
dev_priv->track_flush |= RADEON_FLUSH_EMITED;
454
435
455
436
cmdbuf->buf += 8 * 4;
456
437
cmdbuf->bufsz -= 8 * 4;
···
580
543
return 0;
581
544
}
582
545
583
-
static __inline__ int r300_emit_indx_buffer(drm_radeon_private_t *dev_priv,
584
-
drm_radeon_kcmd_buffer_t *cmdbuf)
546
+
static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv,
547
+
drm_radeon_kcmd_buffer_t *cmdbuf)
585
548
{
586
-
u32 *cmd = (u32 *) cmdbuf->buf;
587
-
int count, ret;
549
+
u32 *cmd;
550
+
int count;
551
+
int expected_count;
588
552
RING_LOCALS;
589
553
590
-
count=(cmd[0]>>16) & 0x3fff;
554
+
cmd = (u32 *) cmdbuf->buf;
555
+
count = (cmd[0]>>16) & 0x3fff;
556
+
expected_count = cmd[1] >> 16;
557
+
if (!(cmd[1] & R300_VAP_VF_CNTL__INDEX_SIZE_32bit))
558
+
expected_count = (expected_count+1)/2;
591
559
592
-
if ((cmd[1] & 0x8000ffff) != 0x80000810) {
593
-
DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
594
-
return -EINVAL;
595
-
}
596
-
ret = !radeon_check_offset(dev_priv, cmd[2]);
597
-
if (ret) {
598
-
DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
560
+
if (count && count != expected_count) {
561
+
DRM_ERROR("3D_DRAW_INDX_2: packet size %i, expected %i\n",
562
+
count, expected_count);
599
563
return -EINVAL;
600
564
}
601
565
···
607
569
608
570
cmdbuf->buf += (count+2)*4;
609
571
cmdbuf->bufsz -= (count+2)*4;
572
+
573
+
if (!count) {
574
+
drm_r300_cmd_header_t header;
575
+
576
+
if (cmdbuf->bufsz < 4*4 + sizeof(header)) {
577
+
DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER, but stream is too short.\n");
578
+
return -EINVAL;
579
+
}
580
+
581
+
header.u = *(unsigned int *)cmdbuf->buf;
582
+
583
+
cmdbuf->buf += sizeof(header);
584
+
cmdbuf->bufsz -= sizeof(header);
585
+
cmd = (u32 *) cmdbuf->buf;
586
+
587
+
if (header.header.cmd_type != R300_CMD_PACKET3 ||
588
+
header.packet3.packet != R300_CMD_PACKET3_RAW ||
589
+
cmd[0] != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) {
590
+
DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER.\n");
591
+
return -EINVAL;
592
+
}
593
+
594
+
if ((cmd[1] & 0x8000ffff) != 0x80000810) {
595
+
DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
596
+
return -EINVAL;
597
+
}
598
+
if (!radeon_check_offset(dev_priv, cmd[2])) {
599
+
DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
600
+
return -EINVAL;
601
+
}
602
+
if (cmd[3] != expected_count) {
603
+
DRM_ERROR("INDX_BUFFER: buffer size %i, expected %i\n",
604
+
cmd[3], expected_count);
605
+
return -EINVAL;
606
+
}
607
+
608
+
BEGIN_RING(4);
609
+
OUT_RING(cmd[0]);
610
+
OUT_RING_TABLE((int *)(cmdbuf->buf + 4), 3);
611
+
ADVANCE_RING();
612
+
613
+
cmdbuf->buf += 4*4;
614
+
cmdbuf->bufsz -= 4*4;
615
+
}
610
616
611
617
return 0;
612
618
}
···
695
613
case RADEON_CNTL_BITBLT_MULTI:
696
614
return r300_emit_bitblt_multi(dev_priv, cmdbuf);
697
615
698
-
case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
699
-
return r300_emit_indx_buffer(dev_priv, cmdbuf);
700
-
case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
701
-
case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
702
-
case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
616
+
case RADEON_CP_INDX_BUFFER:
617
+
DRM_ERROR("packet3 INDX_BUFFER without preceding 3D_DRAW_INDX_2 is illegal.\n");
618
+
return -EINVAL;
619
+
case RADEON_CP_3D_DRAW_IMMD_2:
620
+
/* triggers drawing using in-packet vertex data */
621
+
case RADEON_CP_3D_DRAW_VBUF_2:
622
+
/* triggers drawing of vertex buffers setup elsewhere */
623
+
dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
624
+
RADEON_PURGE_EMITED);
625
+
break;
626
+
case RADEON_CP_3D_DRAW_INDX_2:
627
+
/* triggers drawing using indices to vertex buffer */
628
+
/* whenever we send vertex we clear flush & purge */
629
+
dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
630
+
RADEON_PURGE_EMITED);
631
+
return r300_emit_draw_indx_2(dev_priv, cmdbuf);
703
632
case RADEON_WAIT_FOR_IDLE:
704
633
case RADEON_CP_NOP:
705
634
/* these packets are safe */
···
806
713
*/
807
714
static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
808
715
{
716
+
uint32_t cache_z, cache_3d, cache_2d;
809
717
RING_LOCALS;
810
718
811
-
BEGIN_RING(6);
812
-
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
813
-
OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
719
+
cache_z = R300_ZC_FLUSH;
720
+
cache_2d = R300_RB2D_DC_FLUSH;
721
+
cache_3d = R300_RB3D_DC_FLUSH;
722
+
if (!(dev_priv->track_flush & RADEON_PURGE_EMITED)) {
723
+
/* we can purge, primitive where draw since last purge */
724
+
cache_z |= R300_ZC_FREE;
725
+
cache_2d |= R300_RB2D_DC_FREE;
726
+
cache_3d |= R300_RB3D_DC_FREE;
727
+
}
728
+
729
+
/* flush & purge zbuffer */
730
+
BEGIN_RING(2);
814
731
OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
815
-
OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
816
-
R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
817
-
OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
818
-
OUT_RING(0x0);
732
+
OUT_RING(cache_z);
819
733
ADVANCE_RING();
734
+
/* flush & purge 3d */
735
+
BEGIN_RING(2);
736
+
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
737
+
OUT_RING(cache_3d);
738
+
ADVANCE_RING();
739
+
/* flush & purge texture */
740
+
BEGIN_RING(2);
741
+
OUT_RING(CP_PACKET0(R300_TX_INVALTAGS, 0));
742
+
OUT_RING(0);
743
+
ADVANCE_RING();
744
+
/* FIXME: is this one really needed ? */
745
+
BEGIN_RING(2);
746
+
OUT_RING(CP_PACKET0(R300_RB3D_AARESOLVE_CTL, 0));
747
+
OUT_RING(0);
748
+
ADVANCE_RING();
749
+
BEGIN_RING(2);
750
+
OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
751
+
OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
752
+
ADVANCE_RING();
753
+
/* flush & purge 2d through E2 as RB2D will trigger lockup */
754
+
BEGIN_RING(4);
755
+
OUT_RING(CP_PACKET0(R300_DSTCACHE_CTLSTAT, 0));
756
+
OUT_RING(cache_2d);
757
+
OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
758
+
OUT_RING(RADEON_WAIT_2D_IDLECLEAN |
759
+
RADEON_WAIT_HOST_IDLECLEAN);
760
+
ADVANCE_RING();
761
+
/* set flush & purge flags */
762
+
dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
820
763
}
821
764
822
765
/**
···
1034
905
1035
906
DRM_DEBUG("\n");
1036
907
1037
-
/* See the comment above r300_emit_begin3d for why this call must be here,
1038
-
* and what the cleanup gotos are for. */
908
+
/* pacify */
1039
909
r300_pacify(dev_priv);
1040
910
1041
911
if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
+3
-2
drivers/gpu/drm/radeon/r300_reg.h
+3
-2
drivers/gpu/drm/radeon/r300_reg.h
···
317
317
* Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
318
318
* avoids bugs caused by still running shaders reading bad data from memory.
319
319
*/
320
-
#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */
320
+
#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
321
321
322
322
/* Absolutely no clue what this register is about. */
323
323
#define R300_VAP_UNKNOWN_2288 0x2288
···
513
513
/* gap */
514
514
515
515
/* Zero to flush caches. */
516
-
#define R300_TX_CNTL 0x4100
516
+
#define R300_TX_INVALTAGS 0x4100
517
517
#define R300_TX_FLUSH 0x0
518
518
519
519
/* The upper enable bits are guessed, based on fglrx reported limits. */
···
1362
1362
#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */
1363
1363
#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */
1364
1364
1365
+
#define R300_RB3D_AARESOLVE_CTL 0x4E88
1365
1366
/* gap */
1366
1367
1367
1368
/* Guess by Vladimir.
+18
-20
drivers/gpu/drm/radeon/radeon_cp.c
+18
-20
drivers/gpu/drm/radeon/radeon_cp.c
···
40
40
#define RADEON_FIFO_DEBUG 0
41
41
42
42
static int radeon_do_cleanup_cp(struct drm_device * dev);
43
+
static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
43
44
44
45
static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
45
46
{
···
199
198
DRM_UDELAY(1);
200
199
}
201
200
} else {
202
-
/* 3D */
203
-
tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
204
-
tmp |= RADEON_RB3D_DC_FLUSH_ALL;
205
-
RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
206
-
207
-
/* 2D */
208
-
tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
209
-
tmp |= RADEON_RB3D_DC_FLUSH_ALL;
210
-
RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
211
-
212
-
for (i = 0; i < dev_priv->usec_timeout; i++) {
213
-
if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
214
-
& RADEON_RB3D_DC_BUSY)) {
215
-
return 0;
216
-
}
217
-
DRM_UDELAY(1);
218
-
}
201
+
/* don't flush or purge cache here or lockup */
202
+
return 0;
219
203
}
220
204
221
205
#if RADEON_FIFO_DEBUG
···
223
237
return 0;
224
238
DRM_UDELAY(1);
225
239
}
240
+
DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
241
+
RADEON_READ(RADEON_RBBM_STATUS),
242
+
RADEON_READ(R300_VAP_CNTL_STATUS));
226
243
227
244
#if RADEON_FIFO_DEBUG
228
245
DRM_ERROR("failed!\n");
···
252
263
}
253
264
DRM_UDELAY(1);
254
265
}
266
+
DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
267
+
RADEON_READ(RADEON_RBBM_STATUS),
268
+
RADEON_READ(R300_VAP_CNTL_STATUS));
255
269
256
270
#if RADEON_FIFO_DEBUG
257
271
DRM_ERROR("failed!\n");
···
435
443
436
444
dev_priv->cp_running = 1;
437
445
438
-
BEGIN_RING(6);
439
-
446
+
BEGIN_RING(8);
447
+
/* isync can only be written through cp on r5xx write it here */
448
+
OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
449
+
OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
450
+
RADEON_ISYNC_ANY3D_IDLE2D |
451
+
RADEON_ISYNC_WAIT_IDLEGUI |
452
+
RADEON_ISYNC_CPSCRATCH_IDLEGUI);
440
453
RADEON_PURGE_CACHE();
441
454
RADEON_PURGE_ZCACHE();
442
455
RADEON_WAIT_UNTIL_IDLE();
443
-
444
456
ADVANCE_RING();
445
457
COMMIT_RING();
458
+
459
+
dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
446
460
}
447
461
448
462
/* Reset the Command Processor. This will not flush any pending
+12
-7
drivers/gpu/drm/radeon/radeon_drv.h
+12
-7
drivers/gpu/drm/radeon/radeon_drv.h
···
220
220
struct drm_file *file_priv;
221
221
};
222
222
223
+
#define RADEON_FLUSH_EMITED (1 < 0)
224
+
#define RADEON_PURGE_EMITED (1 < 1)
225
+
223
226
typedef struct drm_radeon_private {
224
227
drm_radeon_ring_buffer_t ring;
225
228
drm_radeon_sarea_t *sarea_priv;
···
314
311
unsigned long fb_aper_offset;
315
312
316
313
int num_gb_pipes;
314
+
int track_flush;
317
315
} drm_radeon_private_t;
318
316
319
317
typedef struct drm_radeon_buf_priv {
···
697
693
#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
698
694
# define R300_ZC_FLUSH (1 << 0)
699
695
# define R300_ZC_FREE (1 << 1)
700
-
# define R300_ZC_FLUSH_ALL 0x3
701
696
# define R300_ZC_BUSY (1 << 31)
702
697
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
703
698
# define RADEON_RB3D_DC_FLUSH (3 << 0)
···
704
701
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
705
702
# define RADEON_RB3D_DC_BUSY (1 << 31)
706
703
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
704
+
# define R300_RB3D_DC_FLUSH (2 << 0)
705
+
# define R300_RB3D_DC_FREE (2 << 2)
707
706
# define R300_RB3D_DC_FINISH (1 << 4)
708
707
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
709
708
# define RADEON_Z_TEST_MASK (7 << 4)
···
1251
1246
OUT_RING(RADEON_RB3D_DC_FLUSH); \
1252
1247
} else { \
1253
1248
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1254
-
OUT_RING(RADEON_RB3D_DC_FLUSH); \
1249
+
OUT_RING(R300_RB3D_DC_FLUSH); \
1255
1250
} \
1256
1251
} while (0)
1257
1252
1258
1253
#define RADEON_PURGE_CACHE() do { \
1259
1254
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1260
1255
OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1261
-
OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1256
+
OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
1262
1257
} else { \
1263
1258
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1264
-
OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1259
+
OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
1265
1260
} \
1266
1261
} while (0)
1267
1262
···
1278
1273
#define RADEON_PURGE_ZCACHE() do { \
1279
1274
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1280
1275
OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1281
-
OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1276
+
OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
1282
1277
} else { \
1283
-
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1284
-
OUT_RING(R300_ZC_FLUSH_ALL); \
1278
+
OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1279
+
OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
1285
1280
} \
1286
1281
} while (0)
1287
1282