Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-5.0-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
"Fixes for ARC for 5.0, bunch of those are stable fodder anyways so
sooner the better.
- Fix memcpy to prevent prefetchw beyond end of buffer [Eugeniy]
- Enable unaligned access early to prevent exceptions given newer gcc
code gen [Eugeniy]
- Tighten up uboot arg checking to prevent false negatives and also
allow both jtag and bootloading to coexist w/o config option as
needed by kernelCi folks [Eugeniy]
- Set slab alignment to 8 for ARC to avoid the atomic64_t unalign
[Alexey]
- Disable regfile auto save on interrupts on HSDK platform due to a
silicon issue [Vineet]
- Avoid HS38x boot printing crash by not reading HS48x only reg
[Vineet]"
* tag 'arc-5.0-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARCv2: don't assume core 0x54 has dual issue
ARC: define ARCH_SLAB_MINALIGN = 8
ARC: enable uboot support unconditionally
ARC: U-boot: check arguments paranoidly
ARCv2: support manual regfile save on interrupts
ARC: uacces: remove lp_start, lp_end from clobber list
ARC: fix actionpoints configuration detection
ARCv2: lib: memcpy: fix doing prefetchw outside of buffer
ARCv2: Enable unaligned access in early ASM code
+192
-77
+8
-12
arch/arc/Kconfig
+8
-12
arch/arc/Kconfig
···
191
191
192
192
config ARC_SMP_HALT_ON_RESET
193
193
bool "Enable Halt-on-reset boot mode"
194
-
default y if ARC_UBOOT_SUPPORT
195
194
help
196
195
In SMP configuration cores can be configured as Halt-on-reset
197
196
or they could all start at same time. For Halt-on-reset, non
···
406
407
(also referred to as r58:r59). These can also be used by gcc as GPR so
407
408
kernel needs to save/restore per process
408
409
410
+
config ARC_IRQ_NO_AUTOSAVE
411
+
bool "Disable hardware autosave regfile on interrupts"
412
+
default n
413
+
help
414
+
On HS cores, taken interrupt auto saves the regfile on stack.
415
+
This is programmable and can be optionally disabled in which case
416
+
software INTERRUPT_PROLOGUE/EPILGUE do the needed work
417
+
409
418
endif # ISA_ARCV2
410
419
411
420
endmenu # "ARC CPU Configuration"
···
521
514
bool "Paranoia Checks in Low Level TLB Handlers"
522
515
523
516
endif
524
-
525
-
config ARC_UBOOT_SUPPORT
526
-
bool "Support uboot arg Handling"
527
-
help
528
-
ARC Linux by default checks for uboot provided args as pointers to
529
-
external cmdline or DTB. This however breaks in absence of uboot,
530
-
when booting from Metaware debugger directly, as the registers are
531
-
not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
532
-
registers look like uboot args to kernel which then chokes.
533
-
So only enable the uboot arg checking/processing if users are sure
534
-
of uboot being in play.
535
517
536
518
config ARC_BUILTIN_DTB_NAME
537
519
string "Built in DTB"
-1
arch/arc/configs/nps_defconfig
-1
arch/arc/configs/nps_defconfig
-1
arch/arc/configs/vdk_hs38_defconfig
-1
arch/arc/configs/vdk_hs38_defconfig
-2
arch/arc/configs/vdk_hs38_smp_defconfig
-2
arch/arc/configs/vdk_hs38_smp_defconfig
+8
arch/arc/include/asm/arcregs.h
+8
arch/arc/include/asm/arcregs.h
···
151
151
#endif
152
152
};
153
153
154
+
struct bcr_uarch_build_arcv2 {
155
+
#ifdef CONFIG_CPU_BIG_ENDIAN
156
+
unsigned int pad:8, prod:8, maj:8, min:8;
157
+
#else
158
+
unsigned int min:8, maj:8, prod:8, pad:8;
159
+
#endif
160
+
};
161
+
154
162
struct bcr_mpy {
155
163
#ifdef CONFIG_CPU_BIG_ENDIAN
156
164
unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
+11
arch/arc/include/asm/cache.h
+11
arch/arc/include/asm/cache.h
···
52
52
#define cache_line_size() SMP_CACHE_BYTES
53
53
#define ARCH_DMA_MINALIGN SMP_CACHE_BYTES
54
54
55
+
/*
56
+
* Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
57
+
* ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
58
+
* alignment for any atomic64_t embedded in buffer.
59
+
* Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
60
+
* value of 4 (and not 8) in ARC ABI.
61
+
*/
62
+
#if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
63
+
#define ARCH_SLAB_MINALIGN 8
64
+
#endif
65
+
55
66
extern void arc_cache_init(void);
56
67
extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
57
68
extern void read_decode_cache_bcr(void);
+54
arch/arc/include/asm/entry-arcv2.h
+54
arch/arc/include/asm/entry-arcv2.h
···
17
17
;
18
18
; Now manually save: r12, sp, fp, gp, r25
19
19
20
+
#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
21
+
.ifnc \called_from, exception
22
+
st.as r9, [sp, -10] ; save r9 in it's final stack slot
23
+
sub sp, sp, 12 ; skip JLI, LDI, EI
24
+
25
+
PUSH lp_count
26
+
PUSHAX lp_start
27
+
PUSHAX lp_end
28
+
PUSH blink
29
+
30
+
PUSH r11
31
+
PUSH r10
32
+
33
+
sub sp, sp, 4 ; skip r9
34
+
35
+
PUSH r8
36
+
PUSH r7
37
+
PUSH r6
38
+
PUSH r5
39
+
PUSH r4
40
+
PUSH r3
41
+
PUSH r2
42
+
PUSH r1
43
+
PUSH r0
44
+
.endif
45
+
#endif
46
+
20
47
#ifdef CONFIG_ARC_HAS_ACCL_REGS
21
48
PUSH r59
22
49
PUSH r58
···
111
84
#ifdef CONFIG_ARC_HAS_ACCL_REGS
112
85
POP r58
113
86
POP r59
87
+
#endif
88
+
89
+
#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
90
+
.ifnc \called_from, exception
91
+
POP r0
92
+
POP r1
93
+
POP r2
94
+
POP r3
95
+
POP r4
96
+
POP r5
97
+
POP r6
98
+
POP r7
99
+
POP r8
100
+
POP r9
101
+
POP r10
102
+
POP r11
103
+
104
+
POP blink
105
+
POPAX lp_end
106
+
POPAX lp_start
107
+
108
+
POP r9
109
+
mov lp_count, r9
110
+
111
+
add sp, sp, 12 ; skip JLI, LDI, EI
112
+
ld.as r9, [sp, -10] ; reload r9 which got clobbered
113
+
.endif
114
114
#endif
115
115
116
116
.endm
+4
-4
arch/arc/include/asm/uaccess.h
+4
-4
arch/arc/include/asm/uaccess.h
···
207
207
*/
208
208
"=&r" (tmp), "+r" (to), "+r" (from)
209
209
:
210
-
: "lp_count", "lp_start", "lp_end", "memory");
210
+
: "lp_count", "memory");
211
211
212
212
return n;
213
213
}
···
433
433
*/
434
434
"=&r" (tmp), "+r" (to), "+r" (from)
435
435
:
436
-
: "lp_count", "lp_start", "lp_end", "memory");
436
+
: "lp_count", "memory");
437
437
438
438
return n;
439
439
}
···
653
653
" .previous \n"
654
654
: "+r"(d_char), "+r"(res)
655
655
: "i"(0)
656
-
: "lp_count", "lp_start", "lp_end", "memory");
656
+
: "lp_count", "memory");
657
657
658
658
return res;
659
659
}
···
686
686
" .previous \n"
687
687
: "+r"(res), "+r"(dst), "+r"(src), "=r"(val)
688
688
: "g"(-EFAULT), "r"(count)
689
-
: "lp_count", "lp_start", "lp_end", "memory");
689
+
: "lp_count", "memory");
690
690
691
691
return res;
692
692
}
+3
-1
arch/arc/kernel/entry-arcv2.S
+3
-1
arch/arc/kernel/entry-arcv2.S
···
209
209
;####### Return from Intr #######
210
210
211
211
debug_marker_l1:
212
-
bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
212
+
; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
213
+
btst r0, STATUS_DE_BIT ; Z flag set if bit clear
214
+
bnz .Lintr_ret_to_delay_slot ; branch if STATUS_DE_BIT set
213
215
214
216
.Lisr_ret_fast_path:
215
217
; Handle special case #1: (Entry via Exception, Return via IRQ)
+12
-4
arch/arc/kernel/head.S
+12
-4
arch/arc/kernel/head.S
···
17
17
#include <asm/entry.h>
18
18
#include <asm/arcregs.h>
19
19
#include <asm/cache.h>
20
+
#include <asm/irqflags.h>
20
21
21
22
.macro CPU_EARLY_SETUP
22
23
···
48
47
sr r5, [ARC_REG_DC_CTRL]
49
48
50
49
1:
50
+
51
+
#ifdef CONFIG_ISA_ARCV2
52
+
; Unaligned access is disabled at reset, so re-enable early as
53
+
; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access
54
+
; by default
55
+
lr r5, [status32]
56
+
bset r5, r5, STATUS_AD_BIT
57
+
kflag r5
58
+
#endif
51
59
.endm
52
60
53
61
.section .init.text, "ax",@progbits
···
100
90
st.ab 0, [r5, 4]
101
91
1:
102
92
103
-
#ifdef CONFIG_ARC_UBOOT_SUPPORT
104
93
; Uboot - kernel ABI
105
94
; r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
106
-
; r1 = magic number (board identity, unused as of now
95
+
; r1 = magic number (always zero as of now)
107
96
; r2 = pointer to uboot provided cmdline or external DTB in mem
108
-
; These are handled later in setup_arch()
97
+
; These are handled later in handle_uboot_args()
109
98
st r0, [@uboot_tag]
110
99
st r2, [@uboot_arg]
111
-
#endif
112
100
113
101
; setup "current" tsk and optionally cache it in dedicated r25
114
102
mov r9, @init_task
+2
arch/arc/kernel/intc-arcv2.c
+2
arch/arc/kernel/intc-arcv2.c
···
49
49
50
50
*(unsigned int *)&ictrl = 0;
51
51
52
+
#ifndef CONFIG_ARC_IRQ_NO_AUTOSAVE
52
53
ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */
53
54
ictrl.save_blink = 1;
54
55
ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */
55
56
ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */
56
57
ictrl.save_idx_regs = 1; /* JLI, LDI, EI */
58
+
#endif
57
59
58
60
WRITE_AUX(AUX_IRQ_CTRL, ictrl);
59
61
+89
-38
arch/arc/kernel/setup.c
+89
-38
arch/arc/kernel/setup.c
···
199
199
cpu->bpu.ret_stk = 4 << bpu.rse;
200
200
201
201
if (cpu->core.family >= 0x54) {
202
-
unsigned int exec_ctrl;
203
202
204
-
READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
205
-
cpu->extn.dual_enb = !(exec_ctrl & 1);
203
+
struct bcr_uarch_build_arcv2 uarch;
206
204
207
-
/* dual issue always present for this core */
208
-
cpu->extn.dual = 1;
205
+
/*
206
+
* The first 0x54 core (uarch maj:min 0:1 or 0:2) was
207
+
* dual issue only (HS4x). But next uarch rev (1:0)
208
+
* allows it be configured for single issue (HS3x)
209
+
* Ensure we fiddle with dual issue only on HS4x
210
+
*/
211
+
READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
212
+
213
+
if (uarch.prod == 4) {
214
+
unsigned int exec_ctrl;
215
+
216
+
/* dual issue hardware always present */
217
+
cpu->extn.dual = 1;
218
+
219
+
READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
220
+
221
+
/* dual issue hardware enabled ? */
222
+
cpu->extn.dual_enb = !(exec_ctrl & 1);
223
+
224
+
}
209
225
}
210
226
}
211
227
212
228
READ_BCR(ARC_REG_AP_BCR, ap);
213
229
if (ap.ver) {
214
230
cpu->extn.ap_num = 2 << ap.num;
215
-
cpu->extn.ap_full = !!ap.min;
231
+
cpu->extn.ap_full = !ap.min;
216
232
}
217
233
218
234
READ_BCR(ARC_REG_SMART_BCR, bcr);
···
478
462
arc_chk_core_config();
479
463
}
480
464
481
-
static inline int is_kernel(unsigned long addr)
465
+
static inline bool uboot_arg_invalid(unsigned long addr)
482
466
{
483
-
if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end)
484
-
return 1;
485
-
return 0;
467
+
/*
468
+
* Check that it is a untranslated address (although MMU is not enabled
469
+
* yet, it being a high address ensures this is not by fluke)
470
+
*/
471
+
if (addr < PAGE_OFFSET)
472
+
return true;
473
+
474
+
/* Check that address doesn't clobber resident kernel image */
475
+
return addr >= (unsigned long)_stext && addr <= (unsigned long)_end;
476
+
}
477
+
478
+
#define IGNORE_ARGS "Ignore U-boot args: "
479
+
480
+
/* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */
481
+
#define UBOOT_TAG_NONE 0
482
+
#define UBOOT_TAG_CMDLINE 1
483
+
#define UBOOT_TAG_DTB 2
484
+
485
+
void __init handle_uboot_args(void)
486
+
{
487
+
bool use_embedded_dtb = true;
488
+
bool append_cmdline = false;
489
+
490
+
/* check that we know this tag */
491
+
if (uboot_tag != UBOOT_TAG_NONE &&
492
+
uboot_tag != UBOOT_TAG_CMDLINE &&
493
+
uboot_tag != UBOOT_TAG_DTB) {
494
+
pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag);
495
+
goto ignore_uboot_args;
496
+
}
497
+
498
+
if (uboot_tag != UBOOT_TAG_NONE &&
499
+
uboot_arg_invalid((unsigned long)uboot_arg)) {
500
+
pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
501
+
goto ignore_uboot_args;
502
+
}
503
+
504
+
/* see if U-boot passed an external Device Tree blob */
505
+
if (uboot_tag == UBOOT_TAG_DTB) {
506
+
machine_desc = setup_machine_fdt((void *)uboot_arg);
507
+
508
+
/* external Device Tree blob is invalid - use embedded one */
509
+
use_embedded_dtb = !machine_desc;
510
+
}
511
+
512
+
if (uboot_tag == UBOOT_TAG_CMDLINE)
513
+
append_cmdline = true;
514
+
515
+
ignore_uboot_args:
516
+
517
+
if (use_embedded_dtb) {
518
+
machine_desc = setup_machine_fdt(__dtb_start);
519
+
if (!machine_desc)
520
+
panic("Embedded DT invalid\n");
521
+
}
522
+
523
+
/*
524
+
* NOTE: @boot_command_line is populated by setup_machine_fdt() so this
525
+
* append processing can only happen after.
526
+
*/
527
+
if (append_cmdline) {
528
+
/* Ensure a whitespace between the 2 cmdlines */
529
+
strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
530
+
strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE);
531
+
}
486
532
}
487
533
488
534
void __init setup_arch(char **cmdline_p)
489
535
{
490
-
#ifdef CONFIG_ARC_UBOOT_SUPPORT
491
-
/* make sure that uboot passed pointer to cmdline/dtb is valid */
492
-
if (uboot_tag && is_kernel((unsigned long)uboot_arg))
493
-
panic("Invalid uboot arg\n");
494
-
495
-
/* See if u-boot passed an external Device Tree blob */
496
-
machine_desc = setup_machine_fdt(uboot_arg); /* uboot_tag == 2 */
497
-
if (!machine_desc)
498
-
#endif
499
-
{
500
-
/* No, so try the embedded one */
501
-
machine_desc = setup_machine_fdt(__dtb_start);
502
-
if (!machine_desc)
503
-
panic("Embedded DT invalid\n");
504
-
505
-
/*
506
-
* If we are here, it is established that @uboot_arg didn't
507
-
* point to DT blob. Instead if u-boot says it is cmdline,
508
-
* append to embedded DT cmdline.
509
-
* setup_machine_fdt() would have populated @boot_command_line
510
-
*/
511
-
if (uboot_tag == 1) {
512
-
/* Ensure a whitespace between the 2 cmdlines */
513
-
strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
514
-
strlcat(boot_command_line, uboot_arg,
515
-
COMMAND_LINE_SIZE);
516
-
}
517
-
}
536
+
handle_uboot_args();
518
537
519
538
/* Save unparsed command line copy for /proc/cmdline */
520
539
*cmdline_p = boot_command_line;
-14
arch/arc/lib/memcpy-archs.S
-14
arch/arc/lib/memcpy-archs.S
···
25
25
#endif
26
26
27
27
#ifdef CONFIG_ARC_HAS_LL64
28
-
# define PREFETCH_READ(RX) prefetch [RX, 56]
29
-
# define PREFETCH_WRITE(RX) prefetchw [RX, 64]
30
28
# define LOADX(DST,RX) ldd.ab DST, [RX, 8]
31
29
# define STOREX(SRC,RX) std.ab SRC, [RX, 8]
32
30
# define ZOLSHFT 5
33
31
# define ZOLAND 0x1F
34
32
#else
35
-
# define PREFETCH_READ(RX) prefetch [RX, 28]
36
-
# define PREFETCH_WRITE(RX) prefetchw [RX, 32]
37
33
# define LOADX(DST,RX) ld.ab DST, [RX, 4]
38
34
# define STOREX(SRC,RX) st.ab SRC, [RX, 4]
39
35
# define ZOLSHFT 4
···
37
41
#endif
38
42
39
43
ENTRY_CFI(memcpy)
40
-
prefetch [r1] ; Prefetch the read location
41
-
prefetchw [r0] ; Prefetch the write location
42
44
mov.f 0, r2
43
45
;;; if size is zero
44
46
jz.d [blink]
···
66
72
lpnz @.Lcopy32_64bytes
67
73
;; LOOP START
68
74
LOADX (r6, r1)
69
-
PREFETCH_READ (r1)
70
-
PREFETCH_WRITE (r3)
71
75
LOADX (r8, r1)
72
76
LOADX (r10, r1)
73
77
LOADX (r4, r1)
···
109
117
lpnz @.Lcopy8bytes_1
110
118
;; LOOP START
111
119
ld.ab r6, [r1, 4]
112
-
prefetch [r1, 28] ;Prefetch the next read location
113
120
ld.ab r8, [r1,4]
114
-
prefetchw [r3, 32] ;Prefetch the next write location
115
121
116
122
SHIFT_1 (r7, r6, 24)
117
123
or r7, r7, r5
···
152
162
lpnz @.Lcopy8bytes_2
153
163
;; LOOP START
154
164
ld.ab r6, [r1, 4]
155
-
prefetch [r1, 28] ;Prefetch the next read location
156
165
ld.ab r8, [r1,4]
157
-
prefetchw [r3, 32] ;Prefetch the next write location
158
166
159
167
SHIFT_1 (r7, r6, 16)
160
168
or r7, r7, r5
···
192
204
lpnz @.Lcopy8bytes_3
193
205
;; LOOP START
194
206
ld.ab r6, [r1, 4]
195
-
prefetch [r1, 28] ;Prefetch the next read location
196
207
ld.ab r8, [r1,4]
197
-
prefetchw [r3, 32] ;Prefetch the next write location
198
208
199
209
SHIFT_1 (r7, r6, 8)
200
210
or r7, r7, r5