Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux
* 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux:
drm/i915/dp: Dither down to 6bpc if it makes the mode fit
drm/i915: enable semaphores on per-device defaults
drm/i915: don't set unpin_work if vblank_get fails
drm/i915: By default, enable RC6 on IVB and SNB when reasonable
iommu: Export intel_iommu_enabled to signal when iommu is in use
drm/i915/sdvo: Include LVDS panels for the IS_DIGITAL check
drm/i915: prevent division by zero when asking for chipset power
drm/i915: add PCH info to i915_capabilities
drm/i915: set the right SDVO transcoder for CPT
drm/i915: no-lvds quirk for ASUS AT5NM10T-I
drm/i915: Treat pre-gen4 backlight duty cycle value consistently
drm/i915: Hook up Ivybridge eDP
drm/i915: add multi-threaded forcewake support
+361
-90
+1
drivers/gpu/drm/i915/i915_debugfs.c
+1
drivers/gpu/drm/i915/i915_debugfs.c
+10
drivers/gpu/drm/i915/i915_dma.c
+10
drivers/gpu/drm/i915/i915_dma.c
···
1454
1454
1455
1455
diff1 = now - dev_priv->last_time1;
1456
1456
1457
+
/* Prevent division-by-zero if we are asking too fast.
1458
+
* Also, we don't get interesting results if we are polling
1459
+
* faster than once in 10ms, so just return the saved value
1460
+
* in such cases.
1461
+
*/
1462
+
if (diff1 <= 10)
1463
+
return dev_priv->chipset_power;
1464
+
1457
1465
count1 = I915_READ(DMIEC);
1458
1466
count2 = I915_READ(DDREC);
1459
1467
count3 = I915_READ(CSIEC);
···
1491
1483
1492
1484
dev_priv->last_count1 = total_count;
1493
1485
dev_priv->last_time1 = now;
1486
+
1487
+
dev_priv->chipset_power = ret;
1494
1488
1495
1489
return ret;
1496
1490
}
+33
-10
drivers/gpu/drm/i915/i915_drv.c
+33
-10
drivers/gpu/drm/i915/i915_drv.c
···
58
58
MODULE_PARM_DESC(powersave,
59
59
"Enable powersavings, fbc, downclocking, etc. (default: true)");
60
60
61
-
unsigned int i915_semaphores __read_mostly = 0;
61
+
int i915_semaphores __read_mostly = -1;
62
62
module_param_named(semaphores, i915_semaphores, int, 0600);
63
63
MODULE_PARM_DESC(semaphores,
64
-
"Use semaphores for inter-ring sync (default: false)");
64
+
"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
65
66
-
unsigned int i915_enable_rc6 __read_mostly = 0;
66
+
int i915_enable_rc6 __read_mostly = -1;
67
67
module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
68
68
MODULE_PARM_DESC(i915_enable_rc6,
69
-
"Enable power-saving render C-state 6 (default: true)");
69
+
"Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
70
70
71
71
int i915_enable_fbc __read_mostly = -1;
72
72
module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
···
328
328
}
329
329
}
330
330
331
-
static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
331
+
void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
332
332
{
333
333
int count;
334
334
···
344
344
udelay(10);
345
345
}
346
346
347
+
void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
348
+
{
349
+
int count;
350
+
351
+
count = 0;
352
+
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
353
+
udelay(10);
354
+
355
+
I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
356
+
POSTING_READ(FORCEWAKE_MT);
357
+
358
+
count = 0;
359
+
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
360
+
udelay(10);
361
+
}
362
+
347
363
/*
348
364
* Generally this is called implicitly by the register read function. However,
349
365
* if some sequence requires the GT to not power down then this function should
···
372
356
373
357
/* Forcewake is atomic in case we get in here without the lock */
374
358
if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
375
-
__gen6_gt_force_wake_get(dev_priv);
359
+
dev_priv->display.force_wake_get(dev_priv);
376
360
}
377
361
378
-
static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
362
+
void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
379
363
{
380
364
I915_WRITE_NOTRACE(FORCEWAKE, 0);
381
365
POSTING_READ(FORCEWAKE);
366
+
}
367
+
368
+
void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
369
+
{
370
+
I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
371
+
POSTING_READ(FORCEWAKE_MT);
382
372
}
383
373
384
374
/*
···
395
373
WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
396
374
397
375
if (atomic_dec_and_test(&dev_priv->forcewake_count))
398
-
__gen6_gt_force_wake_put(dev_priv);
376
+
dev_priv->display.force_wake_put(dev_priv);
399
377
}
400
378
401
379
void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
···
925
903
/* We give fast paths for the really cool registers */
926
904
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
927
905
(((dev_priv)->info->gen >= 6) && \
928
-
((reg) < 0x40000) && \
929
-
((reg) != FORCEWAKE))
906
+
((reg) < 0x40000) && \
907
+
((reg) != FORCEWAKE) && \
908
+
((reg) != ECOBUS))
930
909
931
910
#define __i915_read(x, y) \
932
911
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
+14
-4
drivers/gpu/drm/i915/i915_drv.h
+14
-4
drivers/gpu/drm/i915/i915_drv.h
···
107
107
struct opregion_acpi;
108
108
struct opregion_swsci;
109
109
struct opregion_asle;
110
+
struct drm_i915_private;
110
111
111
112
struct intel_opregion {
112
113
struct opregion_header *header;
···
222
221
struct drm_i915_gem_object *obj);
223
222
int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
224
223
int x, int y);
224
+
void (*force_wake_get)(struct drm_i915_private *dev_priv);
225
+
void (*force_wake_put)(struct drm_i915_private *dev_priv);
225
226
/* clock updates for mode set */
226
227
/* cursor updates */
227
228
/* render clock increase/decrease */
···
713
710
714
711
u64 last_count1;
715
712
unsigned long last_time1;
713
+
unsigned long chipset_power;
716
714
u64 last_count2;
717
715
struct timespec last_time2;
718
716
unsigned long gfx_power;
···
1002
998
extern unsigned int i915_fbpercrtc __always_unused;
1003
999
extern int i915_panel_ignore_lid __read_mostly;
1004
1000
extern unsigned int i915_powersave __read_mostly;
1005
-
extern unsigned int i915_semaphores __read_mostly;
1001
+
extern int i915_semaphores __read_mostly;
1006
1002
extern unsigned int i915_lvds_downclock __read_mostly;
1007
1003
extern int i915_panel_use_ssc __read_mostly;
1008
1004
extern int i915_vbt_sdvo_panel_type __read_mostly;
1009
-
extern unsigned int i915_enable_rc6 __read_mostly;
1005
+
extern int i915_enable_rc6 __read_mostly;
1010
1006
extern int i915_enable_fbc __read_mostly;
1011
1007
extern bool i915_enable_hangcheck __read_mostly;
1012
1008
···
1312
1308
extern void intel_detect_pch(struct drm_device *dev);
1313
1309
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1314
1310
1311
+
extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1312
+
extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1313
+
extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1314
+
extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1315
+
1315
1316
/* overlay */
1316
1317
#ifdef CONFIG_DEBUG_FS
1317
1318
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
···
1361
1352
/* We give fast paths for the really cool registers */
1362
1353
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1363
1354
(((dev_priv)->info->gen >= 6) && \
1364
-
((reg) < 0x40000) && \
1365
-
((reg) != FORCEWAKE))
1355
+
((reg) < 0x40000) && \
1356
+
((reg) != FORCEWAKE) && \
1357
+
((reg) != ECOBUS))
1366
1358
1367
1359
#define __i915_read(x, y) \
1368
1360
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
+18
-1
drivers/gpu/drm/i915/i915_gem_execbuffer.c
+18
-1
drivers/gpu/drm/i915/i915_gem_execbuffer.c
···
32
32
#include "i915_drv.h"
33
33
#include "i915_trace.h"
34
34
#include "intel_drv.h"
35
+
#include <linux/dma_remapping.h>
35
36
36
37
struct change_domains {
37
38
uint32_t invalidate_domains;
···
747
746
return 0;
748
747
}
749
748
749
+
static bool
750
+
intel_enable_semaphores(struct drm_device *dev)
751
+
{
752
+
if (INTEL_INFO(dev)->gen < 6)
753
+
return 0;
754
+
755
+
if (i915_semaphores >= 0)
756
+
return i915_semaphores;
757
+
758
+
/* Enable semaphores on SNB when IO remapping is off */
759
+
if (INTEL_INFO(dev)->gen == 6)
760
+
return !intel_iommu_enabled;
761
+
762
+
return 1;
763
+
}
764
+
750
765
static int
751
766
i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
752
767
struct intel_ring_buffer *to)
···
775
758
return 0;
776
759
777
760
/* XXX gpu semaphores are implicated in various hard hangs on SNB */
778
-
if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores)
761
+
if (!intel_enable_semaphores(obj->base.dev))
779
762
return i915_gem_object_wait_rendering(obj);
780
763
781
764
idx = intel_ring_sync_index(from, to);
+26
-4
drivers/gpu/drm/i915/i915_reg.h
+26
-4
drivers/gpu/drm/i915/i915_reg.h
···
3303
3303
/* or SDVOB */
3304
3304
#define HDMIB 0xe1140
3305
3305
#define PORT_ENABLE (1 << 31)
3306
-
#define TRANSCODER_A (0)
3307
-
#define TRANSCODER_B (1 << 30)
3308
-
#define TRANSCODER(pipe) ((pipe) << 30)
3309
-
#define TRANSCODER_MASK (1 << 30)
3306
+
#define TRANSCODER(pipe) ((pipe) << 30)
3307
+
#define TRANSCODER_CPT(pipe) ((pipe) << 29)
3308
+
#define TRANSCODER_MASK (1 << 30)
3309
+
#define TRANSCODER_MASK_CPT (3 << 29)
3310
3310
#define COLOR_FORMAT_8bpc (0)
3311
3311
#define COLOR_FORMAT_12bpc (3 << 26)
3312
3312
#define SDVOB_HOTPLUG_ENABLE (1 << 23)
···
3447
3447
#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
3448
3448
#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3449
3449
3450
+
/* IVB */
3451
+
#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
3452
+
#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
3453
+
#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
3454
+
#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
3455
+
#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
3456
+
#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
3457
+
#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22)
3458
+
3459
+
/* legacy values */
3460
+
#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
3461
+
#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
3462
+
#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
3463
+
#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
3464
+
#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
3465
+
3466
+
#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
3467
+
3450
3468
#define FORCEWAKE 0xA18C
3451
3469
#define FORCEWAKE_ACK 0x130090
3470
+
#define FORCEWAKE_MT 0xa188 /* multi-threaded */
3471
+
#define FORCEWAKE_MT_ACK 0x130040
3472
+
#define ECOBUS 0xa180
3473
+
#define FORCEWAKE_MT_ENABLE (1<<5)
3452
3474
3453
3475
#define GT_FIFO_FREE_ENTRIES 0x120008
3454
3476
#define GT_FIFO_NUM_RESERVED_ENTRIES 20
+79
-10
drivers/gpu/drm/i915/intel_display.c
+79
-10
drivers/gpu/drm/i915/intel_display.c
···
38
38
#include "i915_drv.h"
39
39
#include "i915_trace.h"
40
40
#include "drm_dp_helper.h"
41
-
42
41
#include "drm_crtc_helper.h"
42
+
#include <linux/dma_remapping.h>
43
43
44
44
#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
45
···
4670
4670
/**
4671
4671
* intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4672
4672
* @crtc: CRTC structure
4673
+
* @mode: requested mode
4673
4674
*
4674
4675
* A pipe may be connected to one or more outputs. Based on the depth of the
4675
4676
* attached framebuffer, choose a good color depth to use on the pipe.
···
4682
4681
* HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4683
4682
* Displays may support a restricted set as well, check EDID and clamp as
4684
4683
* appropriate.
4684
+
* DP may want to dither down to 6bpc to fit larger modes
4685
4685
*
4686
4686
* RETURNS:
4687
4687
* Dithering requirement (i.e. false if display bpc and pipe bpc match,
4688
4688
* true if they don't match).
4689
4689
*/
4690
4690
static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4691
-
unsigned int *pipe_bpp)
4691
+
unsigned int *pipe_bpp,
4692
+
struct drm_display_mode *mode)
4692
4693
{
4693
4694
struct drm_device *dev = crtc->dev;
4694
4695
struct drm_i915_private *dev_priv = dev->dev_private;
···
4759
4756
display_bpc = 8;
4760
4757
}
4761
4758
}
4759
+
}
4760
+
4761
+
if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4762
+
DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4763
+
display_bpc = 6;
4762
4764
}
4763
4765
4764
4766
/*
···
5025
5017
pipeconf |= PIPECONF_DOUBLE_WIDE;
5026
5018
else
5027
5019
pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5020
+
}
5021
+
5022
+
/* default to 8bpc */
5023
+
pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5024
+
if (is_dp) {
5025
+
if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5026
+
pipeconf |= PIPECONF_BPP_6 |
5027
+
PIPECONF_DITHER_EN |
5028
+
PIPECONF_DITHER_TYPE_SP;
5029
+
}
5028
5030
}
5029
5031
5030
5032
dpll |= DPLL_VCO_ENABLE;
···
5498
5480
/* determine panel color depth */
5499
5481
temp = I915_READ(PIPECONF(pipe));
5500
5482
temp &= ~PIPE_BPC_MASK;
5501
-
dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5483
+
dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5502
5484
switch (pipe_bpp) {
5503
5485
case 18:
5504
5486
temp |= PIPE_6BPC;
···
7207
7189
work->old_fb_obj = intel_fb->obj;
7208
7190
INIT_WORK(&work->work, intel_unpin_work_fn);
7209
7191
7192
+
ret = drm_vblank_get(dev, intel_crtc->pipe);
7193
+
if (ret)
7194
+
goto free_work;
7195
+
7210
7196
/* We borrow the event spin lock for protecting unpin_work */
7211
7197
spin_lock_irqsave(&dev->event_lock, flags);
7212
7198
if (intel_crtc->unpin_work) {
7213
7199
spin_unlock_irqrestore(&dev->event_lock, flags);
7214
7200
kfree(work);
7201
+
drm_vblank_put(dev, intel_crtc->pipe);
7215
7202
7216
7203
DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7217
7204
return -EBUSY;
···
7234
7211
drm_gem_object_reference(&obj->base);
7235
7212
7236
7213
crtc->fb = fb;
7237
-
7238
-
ret = drm_vblank_get(dev, intel_crtc->pipe);
7239
-
if (ret)
7240
-
goto cleanup_objs;
7241
7214
7242
7215
work->pending_flip_obj = obj;
7243
7216
···
7257
7238
7258
7239
cleanup_pending:
7259
7240
atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7260
-
cleanup_objs:
7261
7241
drm_gem_object_unreference(&work->old_fb_obj->base);
7262
7242
drm_gem_object_unreference(&obj->base);
7263
7243
mutex_unlock(&dev->struct_mutex);
···
7265
7247
intel_crtc->unpin_work = NULL;
7266
7248
spin_unlock_irqrestore(&dev->event_lock, flags);
7267
7249
7250
+
drm_vblank_put(dev, intel_crtc->pipe);
7251
+
free_work:
7268
7252
kfree(work);
7269
7253
7270
7254
return ret;
···
7907
7887
dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7908
7888
}
7909
7889
7890
+
static bool intel_enable_rc6(struct drm_device *dev)
7891
+
{
7892
+
/*
7893
+
* Respect the kernel parameter if it is set
7894
+
*/
7895
+
if (i915_enable_rc6 >= 0)
7896
+
return i915_enable_rc6;
7897
+
7898
+
/*
7899
+
* Disable RC6 on Ironlake
7900
+
*/
7901
+
if (INTEL_INFO(dev)->gen == 5)
7902
+
return 0;
7903
+
7904
+
/*
7905
+
* Enable rc6 on Sandybridge if DMA remapping is disabled
7906
+
*/
7907
+
if (INTEL_INFO(dev)->gen == 6) {
7908
+
DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
7909
+
intel_iommu_enabled ? "true" : "false",
7910
+
!intel_iommu_enabled ? "en" : "dis");
7911
+
return !intel_iommu_enabled;
7912
+
}
7913
+
DRM_DEBUG_DRIVER("RC6 enabled\n");
7914
+
return 1;
7915
+
}
7916
+
7910
7917
void gen6_enable_rps(struct drm_i915_private *dev_priv)
7911
7918
{
7912
7919
u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
···
7970
7923
I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7971
7924
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7972
7925
7973
-
if (i915_enable_rc6)
7926
+
if (intel_enable_rc6(dev_priv->dev))
7974
7927
rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7975
7928
GEN6_RC_CTL_RC6_ENABLE;
7976
7929
···
8419
8372
/* rc6 disabled by default due to repeated reports of hanging during
8420
8373
* boot and resume.
8421
8374
*/
8422
-
if (!i915_enable_rc6)
8375
+
if (!intel_enable_rc6(dev))
8423
8376
return;
8424
8377
8425
8378
mutex_lock(&dev->struct_mutex);
···
8538
8491
8539
8492
/* For FIFO watermark updates */
8540
8493
if (HAS_PCH_SPLIT(dev)) {
8494
+
dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8495
+
dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8496
+
8497
+
/* IVB configs may use multi-threaded forcewake */
8498
+
if (IS_IVYBRIDGE(dev)) {
8499
+
u32 ecobus;
8500
+
8501
+
mutex_lock(&dev->struct_mutex);
8502
+
__gen6_gt_force_wake_mt_get(dev_priv);
8503
+
ecobus = I915_READ(ECOBUS);
8504
+
__gen6_gt_force_wake_mt_put(dev_priv);
8505
+
mutex_unlock(&dev->struct_mutex);
8506
+
8507
+
if (ecobus & FORCEWAKE_MT_ENABLE) {
8508
+
DRM_DEBUG_KMS("Using MT version of forcewake\n");
8509
+
dev_priv->display.force_wake_get =
8510
+
__gen6_gt_force_wake_mt_get;
8511
+
dev_priv->display.force_wake_put =
8512
+
__gen6_gt_force_wake_mt_put;
8513
+
}
8514
+
}
8515
+
8541
8516
if (HAS_PCH_IBX(dev))
8542
8517
dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8543
8518
else if (HAS_PCH_CPT(dev))
+133
-40
drivers/gpu/drm/i915/intel_dp.c
+133
-40
drivers/gpu/drm/i915/intel_dp.c
···
208
208
*/
209
209
210
210
static int
211
-
intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock)
211
+
intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp)
212
212
{
213
213
struct drm_crtc *crtc = intel_dp->base.base.crtc;
214
214
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
215
215
int bpp = 24;
216
216
217
-
if (intel_crtc)
217
+
if (check_bpp)
218
+
bpp = check_bpp;
219
+
else if (intel_crtc)
218
220
bpp = intel_crtc->bpp;
219
221
220
222
return (pixel_clock * bpp + 9) / 10;
···
235
233
struct intel_dp *intel_dp = intel_attached_dp(connector);
236
234
int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
237
235
int max_lanes = intel_dp_max_lane_count(intel_dp);
236
+
int max_rate, mode_rate;
238
237
239
238
if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
240
239
if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
···
245
242
return MODE_PANEL;
246
243
}
247
244
248
-
if (intel_dp_link_required(intel_dp, mode->clock)
249
-
> intel_dp_max_data_rate(max_link_clock, max_lanes))
250
-
return MODE_CLOCK_HIGH;
245
+
mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0);
246
+
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
247
+
248
+
if (mode_rate > max_rate) {
249
+
mode_rate = intel_dp_link_required(intel_dp,
250
+
mode->clock, 18);
251
+
if (mode_rate > max_rate)
252
+
return MODE_CLOCK_HIGH;
253
+
else
254
+
mode->private_flags |= INTEL_MODE_DP_FORCE_6BPC;
255
+
}
251
256
252
257
if (mode->clock < 10000)
253
258
return MODE_CLOCK_LOW;
···
373
362
* clock divider.
374
363
*/
375
364
if (is_cpu_edp(intel_dp)) {
376
-
if (IS_GEN6(dev))
377
-
aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
365
+
if (IS_GEN6(dev) || IS_GEN7(dev))
366
+
aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
378
367
else
379
368
aux_clock_divider = 225; /* eDP input clock at 450Mhz */
380
369
} else if (HAS_PCH_SPLIT(dev))
···
683
672
int lane_count, clock;
684
673
int max_lane_count = intel_dp_max_lane_count(intel_dp);
685
674
int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
675
+
int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0;
686
676
static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
687
677
688
678
if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
···
701
689
for (clock = 0; clock <= max_clock; clock++) {
702
690
int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
703
691
704
-
if (intel_dp_link_required(intel_dp, mode->clock)
692
+
if (intel_dp_link_required(intel_dp, mode->clock, bpp)
705
693
<= link_avail) {
706
694
intel_dp->link_bw = bws[clock];
707
695
intel_dp->lane_count = lane_count;
···
829
817
}
830
818
831
819
/*
832
-
* There are three kinds of DP registers:
820
+
* There are four kinds of DP registers:
833
821
*
834
822
* IBX PCH
835
-
* CPU
823
+
* SNB CPU
824
+
* IVB CPU
836
825
* CPT PCH
837
826
*
838
827
* IBX PCH and CPU are the same for almost everything,
···
886
873
887
874
/* Split out the IBX/CPU vs CPT settings */
888
875
889
-
if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
876
+
if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
877
+
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
878
+
intel_dp->DP |= DP_SYNC_HS_HIGH;
879
+
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
880
+
intel_dp->DP |= DP_SYNC_VS_HIGH;
881
+
intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
882
+
883
+
if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
884
+
intel_dp->DP |= DP_ENHANCED_FRAMING;
885
+
886
+
intel_dp->DP |= intel_crtc->pipe << 29;
887
+
888
+
/* don't miss out required setting for eDP */
889
+
intel_dp->DP |= DP_PLL_ENABLE;
890
+
if (adjusted_mode->clock < 200000)
891
+
intel_dp->DP |= DP_PLL_FREQ_160MHZ;
892
+
else
893
+
intel_dp->DP |= DP_PLL_FREQ_270MHZ;
894
+
} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
890
895
intel_dp->DP |= intel_dp->color_range;
891
896
892
897
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
···
1406
1375
* These are source-specific values; current Intel hardware supports
1407
1376
* a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1408
1377
*/
1409
-
#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1410
-
#define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200
1411
1378
1412
1379
static uint8_t
1413
-
intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1380
+
intel_dp_voltage_max(struct intel_dp *intel_dp)
1414
1381
{
1415
-
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1416
-
case DP_TRAIN_VOLTAGE_SWING_400:
1417
-
return DP_TRAIN_PRE_EMPHASIS_6;
1418
-
case DP_TRAIN_VOLTAGE_SWING_600:
1419
-
return DP_TRAIN_PRE_EMPHASIS_6;
1420
-
case DP_TRAIN_VOLTAGE_SWING_800:
1421
-
return DP_TRAIN_PRE_EMPHASIS_3_5;
1422
-
case DP_TRAIN_VOLTAGE_SWING_1200:
1423
-
default:
1424
-
return DP_TRAIN_PRE_EMPHASIS_0;
1382
+
struct drm_device *dev = intel_dp->base.base.dev;
1383
+
1384
+
if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1385
+
return DP_TRAIN_VOLTAGE_SWING_800;
1386
+
else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1387
+
return DP_TRAIN_VOLTAGE_SWING_1200;
1388
+
else
1389
+
return DP_TRAIN_VOLTAGE_SWING_800;
1390
+
}
1391
+
1392
+
static uint8_t
1393
+
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1394
+
{
1395
+
struct drm_device *dev = intel_dp->base.base.dev;
1396
+
1397
+
if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1398
+
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1399
+
case DP_TRAIN_VOLTAGE_SWING_400:
1400
+
return DP_TRAIN_PRE_EMPHASIS_6;
1401
+
case DP_TRAIN_VOLTAGE_SWING_600:
1402
+
case DP_TRAIN_VOLTAGE_SWING_800:
1403
+
return DP_TRAIN_PRE_EMPHASIS_3_5;
1404
+
default:
1405
+
return DP_TRAIN_PRE_EMPHASIS_0;
1406
+
}
1407
+
} else {
1408
+
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1409
+
case DP_TRAIN_VOLTAGE_SWING_400:
1410
+
return DP_TRAIN_PRE_EMPHASIS_6;
1411
+
case DP_TRAIN_VOLTAGE_SWING_600:
1412
+
return DP_TRAIN_PRE_EMPHASIS_6;
1413
+
case DP_TRAIN_VOLTAGE_SWING_800:
1414
+
return DP_TRAIN_PRE_EMPHASIS_3_5;
1415
+
case DP_TRAIN_VOLTAGE_SWING_1200:
1416
+
default:
1417
+
return DP_TRAIN_PRE_EMPHASIS_0;
1418
+
}
1425
1419
}
1426
1420
}
1427
1421
1428
1422
static void
1429
1423
intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1430
1424
{
1431
-
struct drm_device *dev = intel_dp->base.base.dev;
1432
1425
uint8_t v = 0;
1433
1426
uint8_t p = 0;
1434
1427
int lane;
1435
1428
uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1436
-
int voltage_max;
1429
+
uint8_t voltage_max;
1430
+
uint8_t preemph_max;
1437
1431
1438
1432
for (lane = 0; lane < intel_dp->lane_count; lane++) {
1439
1433
uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
···
1470
1414
p = this_p;
1471
1415
}
1472
1416
1473
-
if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1474
-
voltage_max = I830_DP_VOLTAGE_MAX_CPT;
1475
-
else
1476
-
voltage_max = I830_DP_VOLTAGE_MAX;
1417
+
voltage_max = intel_dp_voltage_max(intel_dp);
1477
1418
if (v >= voltage_max)
1478
1419
v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1479
1420
1480
-
if (p >= intel_dp_pre_emphasis_max(v))
1481
-
p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1421
+
preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1422
+
if (p >= preemph_max)
1423
+
p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1482
1424
1483
1425
for (lane = 0; lane < 4; lane++)
1484
1426
intel_dp->train_set[lane] = v | p;
···
1545
1491
DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1546
1492
"0x%x\n", signal_levels);
1547
1493
return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1494
+
}
1495
+
}
1496
+
1497
+
/* Gen7's DP voltage swing and pre-emphasis control */
1498
+
static uint32_t
1499
+
intel_gen7_edp_signal_levels(uint8_t train_set)
1500
+
{
1501
+
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1502
+
DP_TRAIN_PRE_EMPHASIS_MASK);
1503
+
switch (signal_levels) {
1504
+
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1505
+
return EDP_LINK_TRAIN_400MV_0DB_IVB;
1506
+
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1507
+
return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1508
+
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1509
+
return EDP_LINK_TRAIN_400MV_6DB_IVB;
1510
+
1511
+
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1512
+
return EDP_LINK_TRAIN_600MV_0DB_IVB;
1513
+
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1514
+
return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1515
+
1516
+
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1517
+
return EDP_LINK_TRAIN_800MV_0DB_IVB;
1518
+
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1519
+
return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1520
+
1521
+
default:
1522
+
DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1523
+
"0x%x\n", signal_levels);
1524
+
return EDP_LINK_TRAIN_500MV_0DB_IVB;
1548
1525
}
1549
1526
}
1550
1527
···
1684
1599
DP_LINK_CONFIGURATION_SIZE);
1685
1600
1686
1601
DP |= DP_PORT_EN;
1687
-
if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1602
+
1603
+
if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1688
1604
DP &= ~DP_LINK_TRAIN_MASK_CPT;
1689
1605
else
1690
1606
DP &= ~DP_LINK_TRAIN_MASK;
···
1699
1613
uint8_t link_status[DP_LINK_STATUS_SIZE];
1700
1614
uint32_t signal_levels;
1701
1615
1702
-
if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1616
+
1617
+
if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1618
+
signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1619
+
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1620
+
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1703
1621
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1704
1622
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1705
1623
} else {
···
1712
1622
DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1713
1623
}
1714
1624
1715
-
if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1625
+
if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1716
1626
reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1717
1627
else
1718
1628
reg = DP | DP_LINK_TRAIN_PAT_1;
···
1793
1703
break;
1794
1704
}
1795
1705
1796
-
if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1706
+
if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1707
+
signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1708
+
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1709
+
} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1797
1710
signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1798
1711
DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1799
1712
} else {
···
1804
1711
DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1805
1712
}
1806
1713
1807
-
if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1714
+
if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1808
1715
reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1809
1716
else
1810
1717
reg = DP | DP_LINK_TRAIN_PAT_2;
···
1845
1752
++tries;
1846
1753
}
1847
1754
1848
-
if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1755
+
if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1849
1756
reg = DP | DP_LINK_TRAIN_OFF_CPT;
1850
1757
else
1851
1758
reg = DP | DP_LINK_TRAIN_OFF;
···
1875
1782
udelay(100);
1876
1783
}
1877
1784
1878
-
if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) {
1785
+
if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1879
1786
DP &= ~DP_LINK_TRAIN_MASK_CPT;
1880
1787
I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1881
1788
} else {
···
1887
1794
msleep(17);
1888
1795
1889
1796
if (is_edp(intel_dp)) {
1890
-
if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1797
+
if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1891
1798
DP |= DP_LINK_TRAIN_OFF_CPT;
1892
1799
else
1893
1800
DP |= DP_LINK_TRAIN_OFF;
+1
drivers/gpu/drm/i915/intel_drv.h
+1
drivers/gpu/drm/i915/intel_drv.h
···
110
110
/* drm_display_mode->private_flags */
111
111
#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
112
112
#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
113
+
#define INTEL_MODE_DP_FORCE_6BPC (0x10)
113
114
114
115
static inline void
115
116
intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
+8
drivers/gpu/drm/i915/intel_lvds.c
+8
drivers/gpu/drm/i915/intel_lvds.c
···
715
715
DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
716
716
},
717
717
},
718
+
{
719
+
.callback = intel_no_lvds_dmi_callback,
720
+
.ident = "Asus AT5NM10T-I",
721
+
.matches = {
722
+
DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
723
+
DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
724
+
},
725
+
},
718
726
719
727
{ } /* terminating entry */
720
728
};
+5
-11
drivers/gpu/drm/i915/intel_panel.c
+5
-11
drivers/gpu/drm/i915/intel_panel.c
···
178
178
if (HAS_PCH_SPLIT(dev)) {
179
179
max >>= 16;
180
180
} else {
181
-
if (IS_PINEVIEW(dev)) {
181
+
if (INTEL_INFO(dev)->gen < 4)
182
182
max >>= 17;
183
-
} else {
183
+
else
184
184
max >>= 16;
185
-
if (INTEL_INFO(dev)->gen < 4)
186
-
max &= ~1;
187
-
}
188
185
189
186
if (is_backlight_combination_mode(dev))
190
187
max *= 0xff;
···
200
203
val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
201
204
} else {
202
205
val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
203
-
if (IS_PINEVIEW(dev))
206
+
if (INTEL_INFO(dev)->gen < 4)
204
207
val >>= 1;
205
208
206
209
if (is_backlight_combination_mode(dev)) {
207
210
u8 lbpc;
208
211
209
-
val &= ~1;
210
212
pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
211
213
val *= lbpc;
212
214
}
···
242
246
}
243
247
244
248
tmp = I915_READ(BLC_PWM_CTL);
245
-
if (IS_PINEVIEW(dev)) {
246
-
tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
249
+
if (INTEL_INFO(dev)->gen < 4)
247
250
level <<= 1;
248
-
} else
249
-
tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
251
+
tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
250
252
I915_WRITE(BLC_PWM_CTL, tmp | level);
251
253
}
252
254
+26
-10
drivers/gpu/drm/i915/intel_sdvo.c
+26
-10
drivers/gpu/drm/i915/intel_sdvo.c
···
50
50
#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
51
51
#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
52
52
#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
53
+
#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
53
54
54
55
55
56
static const char *tv_format_names[] = {
···
1087
1086
}
1088
1087
sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1089
1088
}
1090
-
if (intel_crtc->pipe == 1)
1091
-
sdvox |= SDVO_PIPE_B_SELECT;
1089
+
1090
+
if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1091
+
sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1092
+
else
1093
+
sdvox |= TRANSCODER(intel_crtc->pipe);
1094
+
1092
1095
if (intel_sdvo->has_hdmi_audio)
1093
1096
sdvox |= SDVO_AUDIO_ENABLE;
1094
1097
···
1319
1314
return status;
1320
1315
}
1321
1316
1317
+
static bool
1318
+
intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1319
+
struct edid *edid)
1320
+
{
1321
+
bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1322
+
bool connector_is_digital = !!IS_DIGITAL(sdvo);
1323
+
1324
+
DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1325
+
connector_is_digital, monitor_is_digital);
1326
+
return connector_is_digital == monitor_is_digital;
1327
+
}
1328
+
1322
1329
static enum drm_connector_status
1323
1330
intel_sdvo_detect(struct drm_connector *connector, bool force)
1324
1331
{
···
1375
1358
if (edid == NULL)
1376
1359
edid = intel_sdvo_get_analog_edid(connector);
1377
1360
if (edid != NULL) {
1378
-
if (edid->input & DRM_EDID_INPUT_DIGITAL)
1379
-
ret = connector_status_disconnected;
1380
-
else
1361
+
if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1362
+
edid))
1381
1363
ret = connector_status_connected;
1364
+
else
1365
+
ret = connector_status_disconnected;
1366
+
1382
1367
connector->display_info.raw_edid = NULL;
1383
1368
kfree(edid);
1384
1369
} else
···
1421
1402
edid = intel_sdvo_get_analog_edid(connector);
1422
1403
1423
1404
if (edid != NULL) {
1424
-
struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1425
-
bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1426
-
bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector);
1427
-
1428
-
if (connector_is_digital == monitor_is_digital) {
1405
+
if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1406
+
edid)) {
1429
1407
drm_mode_connector_update_edid_property(connector, edid);
1430
1408
drm_add_edid_modes(connector, edid);
1431
1409
}
+5
drivers/iommu/intel-iommu.c
+5
drivers/iommu/intel-iommu.c
···
405
405
int dmar_disabled = 1;
406
406
#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
407
407
408
+
int intel_iommu_enabled = 0;
409
+
EXPORT_SYMBOL_GPL(intel_iommu_enabled);
410
+
408
411
static int dmar_map_gfx = 1;
409
412
static int dmar_forcedac;
410
413
static int intel_iommu_strict;
···
3649
3646
bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
3650
3647
3651
3648
bus_register_notifier(&pci_bus_type, &device_nb);
3649
+
3650
+
intel_iommu_enabled = 1;
3652
3651
3653
3652
return 0;
3654
3653
}
+2
include/linux/dma_remapping.h
+2
include/linux/dma_remapping.h
···
31
31
extern int iommu_calculate_agaw(struct intel_iommu *iommu);
32
32
extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
33
33
extern int dmar_disabled;
34
+
extern int intel_iommu_enabled;
34
35
#else
35
36
static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
36
37
{
···
45
44
{
46
45
}
47
46
#define dmar_disabled (1)
47
+
#define intel_iommu_enabled (0)
48
48
#endif
49
49
50
50